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Searched refs:outDiv (Results 1 – 16 of 16) sorted by relevance

/hal_nxp-latest/mcux/mcux-sdk/boards/evkmimx8mq/
Dclock_config.c52 .outDiv = 4U, /*!< Pll out frequency = 2600 / 4 = 650MHZ */
61 .outDiv = 4U, /*!< Pll out frequency = 2600 / 4 = 650MHZ */
70 .outDiv = 4U, /*!< Pll out frequency = 2600 / 4 = 650MHZ */
80 .outDiv = 1U, /*!< PLL output = 1600 / 2 / 1 = 800MHZ */
90 .outDiv = 1U, /*!< PLL output = 2000 / 2 / 1 = 1000MHZ */
100 .outDiv = 1U, /*!< PLL output = 2000 / 2 / 1 = 1000MHZ */
/hal_nxp-latest/mcux/mcux-sdk/devices/MIMX8MQ5/drivers/
Dfsl_clock.c783 assert((config->refDiv != 0U) && (config->outDiv != 0U)); in CLOCK_InitFracPll()
784 assert((config->outDiv % 2U) == 0U); in CLOCK_InitFracPll()
797 (CCM_ANALOG_AUDIO_PLL1_CFG0_PLL_OUTPUT_DIV_VAL((uint32_t)(config->outDiv) / 2U - 1U)) | in CLOCK_InitFracPll()
838 …uint8_t outDiv = (uint8_t)CCM_BIT_FIELD_EXTRACTION(fracCfg0, CCM_ANALOG_AUDIO_PLL1_CFG0_PLL_OUTP… in CLOCK_GetFracPllFreq() local
848 return (uint32_t)(fracClk / (((uint64_t)outDiv + 1U) * 2U)); in CLOCK_GetFracPllFreq()
864 assert(config->outDiv != 0U); in CLOCK_InitSSCGPll()
893 CCM_ANALOG_SYS_PLL1_CFG2_PLL_OUTPUT_DIV_VAL((uint32_t)(config->outDiv) - 1U) | in CLOCK_InitSSCGPll()
932 …uint8_t outDiv = (uint8_t)CCM_BIT_FIELD_EXTRACTION(sscgCfg2, CCM_ANALOG_SYS_PLL1_CFG2_PLL_OUTPUT_D… in CLOCK_GetSSCGPllFreq() local
951 return (uint32_t)(pll2InputClock * divf2 / outDiv); in CLOCK_GetSSCGPllFreq()
Dfsl_clock.h989 …uint8_t outDiv; /*!< output clock divide, output clock range is 30MHZ to 2000MHZ, must be a … member
1011 uint8_t outDiv; /*!< A 6bit output clock divide, output clock range is 20MHZ to 1200MHZ */ member
/hal_nxp-latest/mcux/mcux-sdk/devices/MIMX8MD7/drivers/
Dfsl_clock.c783 assert((config->refDiv != 0U) && (config->outDiv != 0U)); in CLOCK_InitFracPll()
784 assert((config->outDiv % 2U) == 0U); in CLOCK_InitFracPll()
797 (CCM_ANALOG_AUDIO_PLL1_CFG0_PLL_OUTPUT_DIV_VAL((uint32_t)(config->outDiv) / 2U - 1U)) | in CLOCK_InitFracPll()
838 …uint8_t outDiv = (uint8_t)CCM_BIT_FIELD_EXTRACTION(fracCfg0, CCM_ANALOG_AUDIO_PLL1_CFG0_PLL_OUTP… in CLOCK_GetFracPllFreq() local
848 return (uint32_t)(fracClk / (((uint64_t)outDiv + 1U) * 2U)); in CLOCK_GetFracPllFreq()
864 assert(config->outDiv != 0U); in CLOCK_InitSSCGPll()
893 CCM_ANALOG_SYS_PLL1_CFG2_PLL_OUTPUT_DIV_VAL((uint32_t)(config->outDiv) - 1U) | in CLOCK_InitSSCGPll()
932 …uint8_t outDiv = (uint8_t)CCM_BIT_FIELD_EXTRACTION(sscgCfg2, CCM_ANALOG_SYS_PLL1_CFG2_PLL_OUTPUT_D… in CLOCK_GetSSCGPllFreq() local
951 return (uint32_t)(pll2InputClock * divf2 / outDiv); in CLOCK_GetSSCGPllFreq()
Dfsl_clock.h989 …uint8_t outDiv; /*!< output clock divide, output clock range is 30MHZ to 2000MHZ, must be a … member
1011 uint8_t outDiv; /*!< A 6bit output clock divide, output clock range is 20MHZ to 1200MHZ */ member
/hal_nxp-latest/mcux/mcux-sdk/devices/MIMX8MD6/drivers/
Dfsl_clock.c783 assert((config->refDiv != 0U) && (config->outDiv != 0U)); in CLOCK_InitFracPll()
784 assert((config->outDiv % 2U) == 0U); in CLOCK_InitFracPll()
797 (CCM_ANALOG_AUDIO_PLL1_CFG0_PLL_OUTPUT_DIV_VAL((uint32_t)(config->outDiv) / 2U - 1U)) | in CLOCK_InitFracPll()
838 …uint8_t outDiv = (uint8_t)CCM_BIT_FIELD_EXTRACTION(fracCfg0, CCM_ANALOG_AUDIO_PLL1_CFG0_PLL_OUTP… in CLOCK_GetFracPllFreq() local
848 return (uint32_t)(fracClk / (((uint64_t)outDiv + 1U) * 2U)); in CLOCK_GetFracPllFreq()
864 assert(config->outDiv != 0U); in CLOCK_InitSSCGPll()
893 CCM_ANALOG_SYS_PLL1_CFG2_PLL_OUTPUT_DIV_VAL((uint32_t)(config->outDiv) - 1U) | in CLOCK_InitSSCGPll()
932 …uint8_t outDiv = (uint8_t)CCM_BIT_FIELD_EXTRACTION(sscgCfg2, CCM_ANALOG_SYS_PLL1_CFG2_PLL_OUTPUT_D… in CLOCK_GetSSCGPllFreq() local
951 return (uint32_t)(pll2InputClock * divf2 / outDiv); in CLOCK_GetSSCGPllFreq()
Dfsl_clock.h989 …uint8_t outDiv; /*!< output clock divide, output clock range is 30MHZ to 2000MHZ, must be a … member
1011 uint8_t outDiv; /*!< A 6bit output clock divide, output clock range is 20MHZ to 1200MHZ */ member
/hal_nxp-latest/mcux/mcux-sdk/devices/MIMX8MQ6/drivers/
Dfsl_clock.c783 assert((config->refDiv != 0U) && (config->outDiv != 0U)); in CLOCK_InitFracPll()
784 assert((config->outDiv % 2U) == 0U); in CLOCK_InitFracPll()
797 (CCM_ANALOG_AUDIO_PLL1_CFG0_PLL_OUTPUT_DIV_VAL((uint32_t)(config->outDiv) / 2U - 1U)) | in CLOCK_InitFracPll()
838 …uint8_t outDiv = (uint8_t)CCM_BIT_FIELD_EXTRACTION(fracCfg0, CCM_ANALOG_AUDIO_PLL1_CFG0_PLL_OUTP… in CLOCK_GetFracPllFreq() local
848 return (uint32_t)(fracClk / (((uint64_t)outDiv + 1U) * 2U)); in CLOCK_GetFracPllFreq()
864 assert(config->outDiv != 0U); in CLOCK_InitSSCGPll()
893 CCM_ANALOG_SYS_PLL1_CFG2_PLL_OUTPUT_DIV_VAL((uint32_t)(config->outDiv) - 1U) | in CLOCK_InitSSCGPll()
932 …uint8_t outDiv = (uint8_t)CCM_BIT_FIELD_EXTRACTION(sscgCfg2, CCM_ANALOG_SYS_PLL1_CFG2_PLL_OUTPUT_D… in CLOCK_GetSSCGPllFreq() local
951 return (uint32_t)(pll2InputClock * divf2 / outDiv); in CLOCK_GetSSCGPllFreq()
Dfsl_clock.h989 …uint8_t outDiv; /*!< output clock divide, output clock range is 30MHZ to 2000MHZ, must be a … member
1011 uint8_t outDiv; /*!< A 6bit output clock divide, output clock range is 20MHZ to 1200MHZ */ member
/hal_nxp-latest/mcux/mcux-sdk/devices/MIMX8MQ7/drivers/
Dfsl_clock.c783 assert((config->refDiv != 0U) && (config->outDiv != 0U)); in CLOCK_InitFracPll()
784 assert((config->outDiv % 2U) == 0U); in CLOCK_InitFracPll()
797 (CCM_ANALOG_AUDIO_PLL1_CFG0_PLL_OUTPUT_DIV_VAL((uint32_t)(config->outDiv) / 2U - 1U)) | in CLOCK_InitFracPll()
838 …uint8_t outDiv = (uint8_t)CCM_BIT_FIELD_EXTRACTION(fracCfg0, CCM_ANALOG_AUDIO_PLL1_CFG0_PLL_OUTP… in CLOCK_GetFracPllFreq() local
848 return (uint32_t)(fracClk / (((uint64_t)outDiv + 1U) * 2U)); in CLOCK_GetFracPllFreq()
864 assert(config->outDiv != 0U); in CLOCK_InitSSCGPll()
893 CCM_ANALOG_SYS_PLL1_CFG2_PLL_OUTPUT_DIV_VAL((uint32_t)(config->outDiv) - 1U) | in CLOCK_InitSSCGPll()
932 …uint8_t outDiv = (uint8_t)CCM_BIT_FIELD_EXTRACTION(sscgCfg2, CCM_ANALOG_SYS_PLL1_CFG2_PLL_OUTPUT_D… in CLOCK_GetSSCGPllFreq() local
951 return (uint32_t)(pll2InputClock * divf2 / outDiv); in CLOCK_GetSSCGPllFreq()
Dfsl_clock.h989 …uint8_t outDiv; /*!< output clock divide, output clock range is 30MHZ to 2000MHZ, must be a … member
1011 uint8_t outDiv; /*!< A 6bit output clock divide, output clock range is 20MHZ to 1200MHZ */ member
/hal_nxp-latest/mcux/mcux-sdk/devices/MIMX8MQ5/
Dsystem_MIMX8MQ5_cm4.c83 …uint8_t outDiv = (uint8_t)CCM_BIT_FIELD_VAL(fracCfg0, CCM_ANALOG_AUDIO_PLL1_CFG0_PLL_OUTPUT_DIV_… in GetFracPllFreq() local
107 return (uint32_t)(fracClk / (((uint64_t)outDiv + 1U) * 2U)); in GetFracPllFreq()
134 …uint8_t outDiv = (uint8_t)CCM_BIT_FIELD_VAL(sscgCfg2, CCM_ANALOG_SYS_PLL1_CFG2_PLL_OUTPUT_DIV_VAL_… in GetSSCGPllFreq() local
168 return (uint32_t)(pll2InputClock * divf2 / outDiv); in GetSSCGPllFreq()
/hal_nxp-latest/mcux/mcux-sdk/devices/MIMX8MD7/
Dsystem_MIMX8MD7_cm4.c83 …uint8_t outDiv = (uint8_t)CCM_BIT_FIELD_VAL(fracCfg0, CCM_ANALOG_AUDIO_PLL1_CFG0_PLL_OUTPUT_DIV_… in GetFracPllFreq() local
107 return (uint32_t)(fracClk / (((uint64_t)outDiv + 1U) * 2U)); in GetFracPllFreq()
134 …uint8_t outDiv = (uint8_t)CCM_BIT_FIELD_VAL(sscgCfg2, CCM_ANALOG_SYS_PLL1_CFG2_PLL_OUTPUT_DIV_VAL_… in GetSSCGPllFreq() local
168 return (uint32_t)(pll2InputClock * divf2 / outDiv); in GetSSCGPllFreq()
/hal_nxp-latest/mcux/mcux-sdk/devices/MIMX8MD6/
Dsystem_MIMX8MD6_cm4.c83 …uint8_t outDiv = (uint8_t)CCM_BIT_FIELD_VAL(fracCfg0, CCM_ANALOG_AUDIO_PLL1_CFG0_PLL_OUTPUT_DIV_… in GetFracPllFreq() local
107 return (uint32_t)(fracClk / (((uint64_t)outDiv + 1U) * 2U)); in GetFracPllFreq()
134 …uint8_t outDiv = (uint8_t)CCM_BIT_FIELD_VAL(sscgCfg2, CCM_ANALOG_SYS_PLL1_CFG2_PLL_OUTPUT_DIV_VAL_… in GetSSCGPllFreq() local
168 return (uint32_t)(pll2InputClock * divf2 / outDiv); in GetSSCGPllFreq()
/hal_nxp-latest/mcux/mcux-sdk/devices/MIMX8MQ6/
Dsystem_MIMX8MQ6_cm4.c83 …uint8_t outDiv = (uint8_t)CCM_BIT_FIELD_VAL(fracCfg0, CCM_ANALOG_AUDIO_PLL1_CFG0_PLL_OUTPUT_DIV_… in GetFracPllFreq() local
107 return (uint32_t)(fracClk / (((uint64_t)outDiv + 1U) * 2U)); in GetFracPllFreq()
134 …uint8_t outDiv = (uint8_t)CCM_BIT_FIELD_VAL(sscgCfg2, CCM_ANALOG_SYS_PLL1_CFG2_PLL_OUTPUT_DIV_VAL_… in GetSSCGPllFreq() local
168 return (uint32_t)(pll2InputClock * divf2 / outDiv); in GetSSCGPllFreq()
/hal_nxp-latest/mcux/mcux-sdk/devices/MIMX8MQ7/
Dsystem_MIMX8MQ7_cm4.c83 …uint8_t outDiv = (uint8_t)CCM_BIT_FIELD_VAL(fracCfg0, CCM_ANALOG_AUDIO_PLL1_CFG0_PLL_OUTPUT_DIV_… in GetFracPllFreq() local
107 return (uint32_t)(fracClk / (((uint64_t)outDiv + 1U) * 2U)); in GetFracPllFreq()
134 …uint8_t outDiv = (uint8_t)CCM_BIT_FIELD_VAL(sscgCfg2, CCM_ANALOG_SYS_PLL1_CFG2_PLL_OUTPUT_DIV_VAL_… in GetSSCGPllFreq() local
168 return (uint32_t)(pll2InputClock * divf2 / outDiv); in GetSSCGPllFreq()