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Searched refs:op2 (Results 1 – 11 of 11) sorted by relevance

/hal_nxp-latest/mcux/mcux-sdk/CMSIS/Include/
Dcmsis_armclang_ltm.h901 __STATIC_FORCEINLINE uint32_t __ROR(uint32_t op1, uint32_t op2) in __ROR() argument
903 op2 %= 32U; in __ROR()
904 if (op2 == 0U) in __ROR()
908 return (op1 >> op2) | (op1 << (32U - op2)); in __ROR()
1365 __STATIC_FORCEINLINE uint32_t __SADD8(uint32_t op1, uint32_t op2) in __SADD8() argument
1369 __ASM volatile ("sadd8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); in __SADD8()
1373 __STATIC_FORCEINLINE uint32_t __QADD8(uint32_t op1, uint32_t op2) in __QADD8() argument
1377 __ASM volatile ("qadd8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); in __QADD8()
1381 __STATIC_FORCEINLINE uint32_t __SHADD8(uint32_t op1, uint32_t op2) in __SHADD8() argument
1385 __ASM volatile ("shadd8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); in __SHADD8()
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Dcmsis_gcc.h1021 __STATIC_FORCEINLINE uint32_t __ROR(uint32_t op1, uint32_t op2) in __ROR() argument
1023 op2 %= 32U; in __ROR()
1024 if (op2 == 0U) in __ROR()
1028 return (op1 >> op2) | (op1 << (32U - op2)); in __ROR()
1621 __STATIC_FORCEINLINE uint32_t __SADD8(uint32_t op1, uint32_t op2) in __SADD8() argument
1625 __ASM volatile ("sadd8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); in __SADD8()
1629 __STATIC_FORCEINLINE uint32_t __QADD8(uint32_t op1, uint32_t op2) in __QADD8() argument
1633 __ASM volatile ("qadd8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); in __QADD8()
1637 __STATIC_FORCEINLINE uint32_t __SHADD8(uint32_t op1, uint32_t op2) in __SHADD8() argument
1641 __ASM volatile ("shadd8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); in __SHADD8()
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Dcmsis_armclang.h902 __STATIC_FORCEINLINE uint32_t __ROR(uint32_t op1, uint32_t op2) in __ROR() argument
904 op2 %= 32U; in __ROR()
905 if (op2 == 0U) in __ROR()
909 return (op1 >> op2) | (op1 << (32U - op2)); in __ROR()
1432 __STATIC_FORCEINLINE int32_t __SMMLA (int32_t op1, int32_t op2, int32_t op3) in __SMMLA() argument
1436 __ASM volatile ("smmla %0, %1, %2, %3" : "=r" (result): "r" (op1), "r" (op2), "r" (op3) ); in __SMMLA()
Dcmsis_iccarm.h615 __IAR_FT uint32_t __ROR(uint32_t op1, uint32_t op2) in __ROR() argument
617 return (op1 >> op2) | (op1 << ((sizeof(op1)*8)-op2)); in __ROR()
/hal_nxp-latest/mcux/mcux-sdk/CMSIS/Core/Include/
Dcmsis_armclang_ltm.h258 __STATIC_FORCEINLINE uint32_t __ROR(uint32_t op1, uint32_t op2) in __ROR() argument
260 op2 %= 32U; in __ROR()
261 if (op2 == 0U) in __ROR()
265 return (op1 >> op2) | (op1 << (32U - op2)); in __ROR()
1398 __STATIC_FORCEINLINE uint32_t __SADD8(uint32_t op1, uint32_t op2) in __SADD8() argument
1402 __ASM volatile ("sadd8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); in __SADD8()
1406 __STATIC_FORCEINLINE uint32_t __QADD8(uint32_t op1, uint32_t op2) in __QADD8() argument
1410 __ASM volatile ("qadd8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); in __QADD8()
1414 __STATIC_FORCEINLINE uint32_t __SHADD8(uint32_t op1, uint32_t op2) in __SHADD8() argument
1418 __ASM volatile ("shadd8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); in __SHADD8()
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Dcmsis_gcc.h346 __STATIC_FORCEINLINE uint32_t __ROR(uint32_t op1, uint32_t op2) in __ROR() argument
348 op2 %= 32U; in __ROR()
349 if (op2 == 0U) in __ROR()
353 return (op1 >> op2) | (op1 << (32U - op2)); in __ROR()
1663 __STATIC_FORCEINLINE uint32_t __SADD8(uint32_t op1, uint32_t op2) in __SADD8() argument
1667 __ASM volatile ("sadd8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); in __SADD8()
1671 __STATIC_FORCEINLINE uint32_t __QADD8(uint32_t op1, uint32_t op2) in __QADD8() argument
1675 __ASM ("qadd8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); in __QADD8()
1679 __STATIC_FORCEINLINE uint32_t __SHADD8(uint32_t op1, uint32_t op2) in __SHADD8() argument
1683 __ASM ("shadd8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); in __SHADD8()
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Dcmsis_armclang.h260 __STATIC_FORCEINLINE uint32_t __ROR(uint32_t op1, uint32_t op2) in __ROR() argument
262 op2 %= 32U; in __ROR()
263 if (op2 == 0U) in __ROR()
267 return (op1 >> op2) | (op1 << (32U - op2)); in __ROR()
1491 __STATIC_FORCEINLINE int32_t __SMMLA (int32_t op1, int32_t op2, int32_t op3) in __SMMLA() argument
1495 __ASM volatile ("smmla %0, %1, %2, %3" : "=r" (result): "r" (op1), "r" (op2), "r" (op3) ); in __SMMLA()
Dcmsis_iccarm.h648 __IAR_FT uint32_t __ROR(uint32_t op1, uint32_t op2) in __ROR() argument
650 return (op1 >> op2) | (op1 << ((sizeof(op1)*8)-op2)); in __ROR()
/hal_nxp-latest/mcux/mcux-sdk/CMSIS/DSP/Include/dsp/
Dnone.h120 __STATIC_FORCEINLINE uint32_t __ROR(uint32_t op1, uint32_t op2) in __ROR() argument
122 op2 %= 32U; in __ROR()
123 if (op2 == 0U) in __ROR()
127 return (op1 >> op2) | (op1 << (32U - op2)); in __ROR()
/hal_nxp-latest/mcux/mcux-sdk/drivers/casper/
Dfsl_casper.h377 void CASPER_ECC_equal(int *res, uint32_t *op1, uint32_t *op2);
Dfsl_casper.c1127 void CASPER_ECC_equal(int *res, uint32_t *op1, uint32_t *op2) in CASPER_ECC_equal() argument
1133 CASPER_MEMCPY(b, op2, N_wordlen * sizeof(uint32_t)); in CASPER_ECC_equal()