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Searched refs:mult (Results 1 – 25 of 65) sorted by relevance

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/hal_nxp-latest/mcux/mcux-sdk/devices/MIMX8UD5/
Dsystem_MIMX8UD5_cm33.c64 uint32_t mult; in getPll0Freq() local
76 mult = ((CGC_RTD->PLL0CFG & CGC_PLL0CFG_MULT_MASK) >> CGC_PLL0CFG_MULT_SHIFT); in getPll0Freq()
77 freq *= pll0Multi[mult]; /* Multiplier. */ in getPll0Freq()
84 uint32_t freq, mult; in getPll1Freq() local
100 mult = (CGC_RTD->PLL1CFG & CGC_PLL1CFG_MULT_MASK) >> CGC_PLL1CFG_MULT_SHIFT; in getPll1Freq()
101 freq = freq * mult + (uint32_t)freqTmp; in getPll1Freq()
Dsystem_MIMX8UD5_dsp0.c65 uint32_t mult; in getPll0Freq() local
77 mult = ((CGC_RTD->PLL0CFG & CGC_PLL0CFG_MULT_MASK) >> CGC_PLL0CFG_MULT_SHIFT); in getPll0Freq()
78 freq *= pll0Multi[mult]; /* Multiplier. */ in getPll0Freq()
/hal_nxp-latest/mcux/mcux-sdk/devices/MIMX8UD7/
Dsystem_MIMX8UD7_cm33.c64 uint32_t mult; in getPll0Freq() local
76 mult = ((CGC_RTD->PLL0CFG & CGC_PLL0CFG_MULT_MASK) >> CGC_PLL0CFG_MULT_SHIFT); in getPll0Freq()
77 freq *= pll0Multi[mult]; /* Multiplier. */ in getPll0Freq()
84 uint32_t freq, mult; in getPll1Freq() local
100 mult = (CGC_RTD->PLL1CFG & CGC_PLL1CFG_MULT_MASK) >> CGC_PLL1CFG_MULT_SHIFT; in getPll1Freq()
101 freq = freq * mult + (uint32_t)freqTmp; in getPll1Freq()
Dsystem_MIMX8UD7_dsp0.c65 uint32_t mult; in getPll0Freq() local
77 mult = ((CGC_RTD->PLL0CFG & CGC_PLL0CFG_MULT_MASK) >> CGC_PLL0CFG_MULT_SHIFT); in getPll0Freq()
78 freq *= pll0Multi[mult]; /* Multiplier. */ in getPll0Freq()
Dsystem_MIMX8UD7_dsp1.c65 uint32_t mult; in getPll0Freq() local
77 mult = ((CGC_RTD->PLL0CFG & CGC_PLL0CFG_MULT_MASK) >> CGC_PLL0CFG_MULT_SHIFT); in getPll0Freq()
78 freq *= pll0Multi[mult]; /* Multiplier. */ in getPll0Freq()
/hal_nxp-latest/mcux/mcux-sdk/devices/MIMX8US5/
Dsystem_MIMX8US5_cm33.c64 uint32_t mult; in getPll0Freq() local
76 mult = ((CGC_RTD->PLL0CFG & CGC_PLL0CFG_MULT_MASK) >> CGC_PLL0CFG_MULT_SHIFT); in getPll0Freq()
77 freq *= pll0Multi[mult]; /* Multiplier. */ in getPll0Freq()
84 uint32_t freq, mult; in getPll1Freq() local
100 mult = (CGC_RTD->PLL1CFG & CGC_PLL1CFG_MULT_MASK) >> CGC_PLL1CFG_MULT_SHIFT; in getPll1Freq()
101 freq = freq * mult + (uint32_t)freqTmp; in getPll1Freq()
Dsystem_MIMX8US5_dsp0.c65 uint32_t mult; in getPll0Freq() local
77 mult = ((CGC_RTD->PLL0CFG & CGC_PLL0CFG_MULT_MASK) >> CGC_PLL0CFG_MULT_SHIFT); in getPll0Freq()
78 freq *= pll0Multi[mult]; /* Multiplier. */ in getPll0Freq()
/hal_nxp-latest/mcux/mcux-sdk/devices/MIMX8US3/
Dsystem_MIMX8US3_cm33.c64 uint32_t mult; in getPll0Freq() local
76 mult = ((CGC_RTD->PLL0CFG & CGC_PLL0CFG_MULT_MASK) >> CGC_PLL0CFG_MULT_SHIFT); in getPll0Freq()
77 freq *= pll0Multi[mult]; /* Multiplier. */ in getPll0Freq()
84 uint32_t freq, mult; in getPll1Freq() local
100 mult = (CGC_RTD->PLL1CFG & CGC_PLL1CFG_MULT_MASK) >> CGC_PLL1CFG_MULT_SHIFT; in getPll1Freq()
101 freq = freq * mult + (uint32_t)freqTmp; in getPll1Freq()
Dsystem_MIMX8US3_dsp0.c65 uint32_t mult; in getPll0Freq() local
77 mult = ((CGC_RTD->PLL0CFG & CGC_PLL0CFG_MULT_MASK) >> CGC_PLL0CFG_MULT_SHIFT); in getPll0Freq()
78 freq *= pll0Multi[mult]; /* Multiplier. */ in getPll0Freq()
/hal_nxp-latest/mcux/mcux-sdk/devices/MIMX8UD3/
Dsystem_MIMX8UD3_cm33.c64 uint32_t mult; in getPll0Freq() local
76 mult = ((CGC_RTD->PLL0CFG & CGC_PLL0CFG_MULT_MASK) >> CGC_PLL0CFG_MULT_SHIFT); in getPll0Freq()
77 freq *= pll0Multi[mult]; /* Multiplier. */ in getPll0Freq()
84 uint32_t freq, mult; in getPll1Freq() local
100 mult = (CGC_RTD->PLL1CFG & CGC_PLL1CFG_MULT_MASK) >> CGC_PLL1CFG_MULT_SHIFT; in getPll1Freq()
101 freq = freq * mult + (uint32_t)freqTmp; in getPll1Freq()
Dsystem_MIMX8UD3_dsp0.c65 uint32_t mult; in getPll0Freq() local
77 mult = ((CGC_RTD->PLL0CFG & CGC_PLL0CFG_MULT_MASK) >> CGC_PLL0CFG_MULT_SHIFT); in getPll0Freq()
78 freq *= pll0Multi[mult]; /* Multiplier. */ in getPll0Freq()
/hal_nxp-latest/mcux/mcux-sdk/CMSIS/NN/Include/
Darm_nnsupportfunctions.h702 q63_t mult = 1 << 30; in arm_nn_doubling_high_mult() local
706 mult = 1 - mult; in arm_nn_doubling_high_mult()
709 mult = mult + (q63_t)m1 * m2; in arm_nn_doubling_high_mult()
713 result = (int32_t)(mult / (1ll << 31)); in arm_nn_doubling_high_mult()
739 union arm_nn_long_long mult; in arm_nn_doubling_high_mult_no_sat() local
742 mult.word.low = 1 << 30; in arm_nn_doubling_high_mult_no_sat()
743 mult.word.high = 0; in arm_nn_doubling_high_mult_no_sat()
746 mult.long_long = mult.long_long + (q63_t)m1 * m2; in arm_nn_doubling_high_mult_no_sat()
750 result = (int32_t)(mult.long_long >> 31); in arm_nn_doubling_high_mult_no_sat()
/hal_nxp-latest/mcux/mcux-sdk/CMSIS/NN/Source/SoftmaxFunctions/
Darm_softmax_s8.c89 const int32_t mult, in arm_softmax_s8() argument
128 int32x4_t res = MUL_SAT_MVE(ip, vdupq_n_s32(mult)); in arm_softmax_s8()
146 sum += DIV_POW2(EXP_ON_NEG(MUL_SAT(diff * mask, mult)), ACCUM_BITS); in arm_softmax_s8()
170 tmp_res = MUL_SAT_MVE(ip, vdupq_n_s32(mult)); in arm_softmax_s8()
195 … DIV_POW2(MUL_SAT(shifted_scale, EXP_ON_NEG(MUL_SAT(diff * mask, mult))), bits_over_unit) - 128; in arm_softmax_s8()
231 sum += DIV_POW2(EXP_ON_NEG(MUL_SAT(diff * mask, mult)), ACCUM_BITS); in arm_softmax_s8()
245 … DIV_POW2(MUL_SAT(shifted_scale, EXP_ON_NEG(MUL_SAT(diff * mask, mult))), bits_over_unit) - 128; in arm_softmax_s8()
Darm_softmax_u8.c47 const int32_t mult, in arm_softmax_u8() argument
75 sum += DIV_POW2(EXP_ON_NEG(MUL_SAT(diff * mask, mult)), ACCUM_BITS); in arm_softmax_u8()
89 … DIV_POW2(MUL_SAT(shifted_scale, EXP_ON_NEG(MUL_SAT(diff * mask, mult))), bits_over_unit); in arm_softmax_u8()
/hal_nxp-latest/mcux/mcux-sdk/CMSIS/NN/Source/ConvolutionFunctions/
Darm_nn_depthwise_conv_s8_core.c133 const int32x4_t mult = vldrwq_s32(out_mult); in arm_nn_depthwise_conv_s8_core() local
138 out_0 = arm_requantize_mve_32x4(out_0, mult, shift); in arm_nn_depthwise_conv_s8_core()
139 out_1 = arm_requantize_mve_32x4(out_1, mult, shift); in arm_nn_depthwise_conv_s8_core()
184 const int32x4_t mult = vldrwq_z_s32(out_mult, p); in arm_nn_depthwise_conv_s8_core() local
187 col_0_sum = arm_requantize_mve_32x4(col_0_sum, mult, shift); in arm_nn_depthwise_conv_s8_core()
188 col_1_sum = arm_requantize_mve_32x4(col_1_sum, mult, shift); in arm_nn_depthwise_conv_s8_core()
/hal_nxp-latest/mcux/mcux-sdk/CMSIS/NN/Source/NNSupportFunctions/
Darm_nn_depthwise_conv_nt_t_padded_s8.c111 const int32x4_t mult = vldrwq_s32(out_mult); in arm_nn_depthwise_conv_nt_t_padded_s8() local
116 out_0 = arm_requantize_mve_32x4(out_0, mult, shift); in arm_nn_depthwise_conv_nt_t_padded_s8()
123 out_1 = arm_requantize_mve_32x4(out_1, mult, shift); in arm_nn_depthwise_conv_nt_t_padded_s8()
129 out_2 = arm_requantize_mve_32x4(out_2, mult, shift); in arm_nn_depthwise_conv_nt_t_padded_s8()
135 out_3 = arm_requantize_mve_32x4(out_3, mult, shift); in arm_nn_depthwise_conv_nt_t_padded_s8()
Darm_nn_depthwise_conv_nt_t_s8.c113 const int32x4_t mult = vldrwq_s32(out_mult); in arm_nn_depthwise_conv_nt_t_s8() local
119 out_0 = arm_requantize_mve_32x4(out_0, mult, shift); in arm_nn_depthwise_conv_nt_t_s8()
125 out_1 = arm_requantize_mve_32x4(out_1, mult, shift); in arm_nn_depthwise_conv_nt_t_s8()
131 out_2 = arm_requantize_mve_32x4(out_2, mult, shift); in arm_nn_depthwise_conv_nt_t_s8()
137 out_3 = arm_requantize_mve_32x4(out_3, mult, shift); in arm_nn_depthwise_conv_nt_t_s8()
/hal_nxp-latest/mcux/mcux-sdk/devices/MCIMX7U3/drivers/
Dfsl_clock.c1104 …assert((33U == config->mult) || (27U == config->mult) || (22U == config->mult) || (20U == config->… in CLOCK_InitAuxPll()
1105 (17U == config->mult) || (16U == config->mult)); in CLOCK_InitAuxPll()
1124 SCG_APLLCFG_MULT(config->mult) | SCG_APLLCFG_PLLS(config->isPfdSelected) | in CLOCK_InitAuxPll()
1411 assert(config->mult < 7U); in CLOCK_InitSysPll()
1430 SCG_SPLLCFG_MULT(config->mult) | SCG_SPLLCFG_PLLS(config->isPfdSelected) | in CLOCK_InitSysPll()
/hal_nxp-latest/mcux/mcux-sdk/devices/MCIMX7U5/drivers/
Dfsl_clock.c1104 …assert((33U == config->mult) || (27U == config->mult) || (22U == config->mult) || (20U == config->… in CLOCK_InitAuxPll()
1105 (17U == config->mult) || (16U == config->mult)); in CLOCK_InitAuxPll()
1124 SCG_APLLCFG_MULT(config->mult) | SCG_APLLCFG_PLLS(config->isPfdSelected) | in CLOCK_InitAuxPll()
1411 assert(config->mult < 7U); in CLOCK_InitSysPll()
1430 SCG_SPLLCFG_MULT(config->mult) | SCG_SPLLCFG_PLLS(config->isPfdSelected) | in CLOCK_InitSysPll()
/hal_nxp-latest/mcux/mcux-sdk/drivers/i2c/
Dfsl_i2c.c172 uint8_t mult; in I2C_SetHoldTime() local
181 for (mult = 0u; mult <= 2u; ++mult) in I2C_SetHoldTime()
188 multiplier = u32flag << mult; in I2C_SetHoldTime()
200 bestMult = mult; in I2C_SetHoldTime()
777 uint8_t mult; in I2C_MasterSetBaudRate() local
782 for (mult = 0u; mult <= 2u; ++mult) in I2C_MasterSetBaudRate()
789 multiplier = u32flag << mult; in I2C_MasterSetBaudRate()
799 bestMult = mult; in I2C_MasterSetBaudRate()
/hal_nxp-latest/mcux/mcux-sdk/boards/twrke18f/
Dclock_config.c193 .mult = 14, /* Multiply Factor is 30 */
305 .mult = 14, /* Multiply Factor is 30 */
425 .mult = 26, /* Multiply Factor is 42 */
/hal_nxp-latest/mcux/mcux-sdk/boards/frdmk32l2a4s/
Dclock_config.c224 .mult = 0, /* Multiply Factor is 16 */
355 .mult = 0, /* Multiply Factor is 16 */
471 .mult = 0, /* Multiply Factor is 16 */
/hal_nxp-latest/mcux/mcux-sdk/devices/MKE18F16/drivers/
Dfsl_clock.c885 uint32_t CLOCK_GetSysPllMultDiv(uint32_t refFreq, uint32_t desireFreq, uint8_t *mult, uint8_t *pred… in CLOCK_GetSysPllMultDiv() argument
950 *mult = mult_cur - SCG_SPLL_MULT_BASE_VALUE; in CLOCK_GetSysPllMultDiv()
977 *mult = ret_mult - SCG_SPLL_MULT_BASE_VALUE; in CLOCK_GetSysPllMultDiv()
1038 …_SPLLCFG_SOURCE(config->src) | SCG_SPLLCFG_PREDIV(config->prediv) | SCG_SPLLCFG_MULT(config->mult); in CLOCK_InitSysPll()
/hal_nxp-latest/mcux/mcux-sdk/devices/MKE14F16/drivers/
Dfsl_clock.c885 uint32_t CLOCK_GetSysPllMultDiv(uint32_t refFreq, uint32_t desireFreq, uint8_t *mult, uint8_t *pred… in CLOCK_GetSysPllMultDiv() argument
950 *mult = mult_cur - SCG_SPLL_MULT_BASE_VALUE; in CLOCK_GetSysPllMultDiv()
977 *mult = ret_mult - SCG_SPLL_MULT_BASE_VALUE; in CLOCK_GetSysPllMultDiv()
1038 …_SPLLCFG_SOURCE(config->src) | SCG_SPLLCFG_PREDIV(config->prediv) | SCG_SPLLCFG_MULT(config->mult); in CLOCK_InitSysPll()
/hal_nxp-latest/mcux/mcux-sdk/devices/MKE16F16/drivers/
Dfsl_clock.c885 uint32_t CLOCK_GetSysPllMultDiv(uint32_t refFreq, uint32_t desireFreq, uint8_t *mult, uint8_t *pred… in CLOCK_GetSysPllMultDiv() argument
950 *mult = mult_cur - SCG_SPLL_MULT_BASE_VALUE; in CLOCK_GetSysPllMultDiv()
977 *mult = ret_mult - SCG_SPLL_MULT_BASE_VALUE; in CLOCK_GetSysPllMultDiv()
1038 …_SPLLCFG_SOURCE(config->src) | SCG_SPLLCFG_PREDIV(config->prediv) | SCG_SPLLCFG_MULT(config->mult); in CLOCK_InitSysPll()

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