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/hal_nxp-latest/mcux/mcux-sdk/devices/MIMX8ML3/drivers/
Dfsl_cache.c457 void L2CACHE_LockdownByWayEnable(uint32_t masterId, uint32_t mask, bool enable) in L2CACHE_LockdownByWayEnable() argument
464 assert(masterId < L2CACHE_LOCKDOWN_REGNUM); in L2CACHE_LockdownByWayEnable()
466 uint32_t dataReg = L2CACHEC->LOCKDOWN[masterId].REG9_D_LOCKDOWN; in L2CACHE_LockdownByWayEnable()
467 uint32_t istrReg = L2CACHEC->LOCKDOWN[masterId].REG9_I_LOCKDOWN; in L2CACHE_LockdownByWayEnable()
472 L2CACHEC->LOCKDOWN[masterId].REG9_D_LOCKDOWN = dataReg | mask; in L2CACHE_LockdownByWayEnable()
474 L2CACHEC->LOCKDOWN[masterId].REG9_I_LOCKDOWN = istrReg | mask; in L2CACHE_LockdownByWayEnable()
479 L2CACHEC->LOCKDOWN[masterId].REG9_D_LOCKDOWN = dataReg & ~mask; in L2CACHE_LockdownByWayEnable()
481 L2CACHEC->LOCKDOWN[masterId].REG9_I_LOCKDOWN = istrReg & ~mask; in L2CACHE_LockdownByWayEnable()
Dfsl_cache.h388 void L2CACHE_LockdownByWayEnable(uint32_t masterId, uint32_t mask, bool enable);
/hal_nxp-latest/mcux/mcux-sdk/devices/MIMXRT1176/drivers/cm7/
Dfsl_cache.c457 void L2CACHE_LockdownByWayEnable(uint32_t masterId, uint32_t mask, bool enable) in L2CACHE_LockdownByWayEnable() argument
464 assert(masterId < L2CACHE_LOCKDOWN_REGNUM); in L2CACHE_LockdownByWayEnable()
466 uint32_t dataReg = L2CACHEC->LOCKDOWN[masterId].REG9_D_LOCKDOWN; in L2CACHE_LockdownByWayEnable()
467 uint32_t istrReg = L2CACHEC->LOCKDOWN[masterId].REG9_I_LOCKDOWN; in L2CACHE_LockdownByWayEnable()
472 L2CACHEC->LOCKDOWN[masterId].REG9_D_LOCKDOWN = dataReg | mask; in L2CACHE_LockdownByWayEnable()
474 L2CACHEC->LOCKDOWN[masterId].REG9_I_LOCKDOWN = istrReg | mask; in L2CACHE_LockdownByWayEnable()
479 L2CACHEC->LOCKDOWN[masterId].REG9_D_LOCKDOWN = dataReg & ~mask; in L2CACHE_LockdownByWayEnable()
481 L2CACHEC->LOCKDOWN[masterId].REG9_I_LOCKDOWN = istrReg & ~mask; in L2CACHE_LockdownByWayEnable()
Dfsl_cache.h388 void L2CACHE_LockdownByWayEnable(uint32_t masterId, uint32_t mask, bool enable);
/hal_nxp-latest/mcux/mcux-sdk/devices/MIMXRT1165/drivers/cm7/
Dfsl_cache.c457 void L2CACHE_LockdownByWayEnable(uint32_t masterId, uint32_t mask, bool enable) in L2CACHE_LockdownByWayEnable() argument
464 assert(masterId < L2CACHE_LOCKDOWN_REGNUM); in L2CACHE_LockdownByWayEnable()
466 uint32_t dataReg = L2CACHEC->LOCKDOWN[masterId].REG9_D_LOCKDOWN; in L2CACHE_LockdownByWayEnable()
467 uint32_t istrReg = L2CACHEC->LOCKDOWN[masterId].REG9_I_LOCKDOWN; in L2CACHE_LockdownByWayEnable()
472 L2CACHEC->LOCKDOWN[masterId].REG9_D_LOCKDOWN = dataReg | mask; in L2CACHE_LockdownByWayEnable()
474 L2CACHEC->LOCKDOWN[masterId].REG9_I_LOCKDOWN = istrReg | mask; in L2CACHE_LockdownByWayEnable()
479 L2CACHEC->LOCKDOWN[masterId].REG9_D_LOCKDOWN = dataReg & ~mask; in L2CACHE_LockdownByWayEnable()
481 L2CACHEC->LOCKDOWN[masterId].REG9_I_LOCKDOWN = istrReg & ~mask; in L2CACHE_LockdownByWayEnable()
Dfsl_cache.h388 void L2CACHE_LockdownByWayEnable(uint32_t masterId, uint32_t mask, bool enable);
/hal_nxp-latest/mcux/mcux-sdk/devices/MIMXRT1189/drivers/cm7/
Dfsl_cache.c457 void L2CACHE_LockdownByWayEnable(uint32_t masterId, uint32_t mask, bool enable) in L2CACHE_LockdownByWayEnable() argument
464 assert(masterId < L2CACHE_LOCKDOWN_REGNUM); in L2CACHE_LockdownByWayEnable()
466 uint32_t dataReg = L2CACHEC->LOCKDOWN[masterId].REG9_D_LOCKDOWN; in L2CACHE_LockdownByWayEnable()
467 uint32_t istrReg = L2CACHEC->LOCKDOWN[masterId].REG9_I_LOCKDOWN; in L2CACHE_LockdownByWayEnable()
472 L2CACHEC->LOCKDOWN[masterId].REG9_D_LOCKDOWN = dataReg | mask; in L2CACHE_LockdownByWayEnable()
474 L2CACHEC->LOCKDOWN[masterId].REG9_I_LOCKDOWN = istrReg | mask; in L2CACHE_LockdownByWayEnable()
479 L2CACHEC->LOCKDOWN[masterId].REG9_D_LOCKDOWN = dataReg & ~mask; in L2CACHE_LockdownByWayEnable()
481 L2CACHEC->LOCKDOWN[masterId].REG9_I_LOCKDOWN = istrReg & ~mask; in L2CACHE_LockdownByWayEnable()
Dfsl_cache.h388 void L2CACHE_LockdownByWayEnable(uint32_t masterId, uint32_t mask, bool enable);
/hal_nxp-latest/mcux/mcux-sdk/drivers/cache/armv7-m7/
Dfsl_cache.c457 void L2CACHE_LockdownByWayEnable(uint32_t masterId, uint32_t mask, bool enable) in L2CACHE_LockdownByWayEnable() argument
464 assert(masterId < L2CACHE_LOCKDOWN_REGNUM); in L2CACHE_LockdownByWayEnable()
466 uint32_t dataReg = L2CACHEC->LOCKDOWN[masterId].REG9_D_LOCKDOWN; in L2CACHE_LockdownByWayEnable()
467 uint32_t istrReg = L2CACHEC->LOCKDOWN[masterId].REG9_I_LOCKDOWN; in L2CACHE_LockdownByWayEnable()
472 L2CACHEC->LOCKDOWN[masterId].REG9_D_LOCKDOWN = dataReg | mask; in L2CACHE_LockdownByWayEnable()
474 L2CACHEC->LOCKDOWN[masterId].REG9_I_LOCKDOWN = istrReg | mask; in L2CACHE_LockdownByWayEnable()
479 L2CACHEC->LOCKDOWN[masterId].REG9_D_LOCKDOWN = dataReg & ~mask; in L2CACHE_LockdownByWayEnable()
481 L2CACHEC->LOCKDOWN[masterId].REG9_I_LOCKDOWN = istrReg & ~mask; in L2CACHE_LockdownByWayEnable()
Dfsl_cache.h388 void L2CACHE_LockdownByWayEnable(uint32_t masterId, uint32_t mask, bool enable);
/hal_nxp-latest/mcux/mcux-sdk/devices/MIMX8ML4/drivers/
Dfsl_cache.c457 void L2CACHE_LockdownByWayEnable(uint32_t masterId, uint32_t mask, bool enable) in L2CACHE_LockdownByWayEnable() argument
464 assert(masterId < L2CACHE_LOCKDOWN_REGNUM); in L2CACHE_LockdownByWayEnable()
466 uint32_t dataReg = L2CACHEC->LOCKDOWN[masterId].REG9_D_LOCKDOWN; in L2CACHE_LockdownByWayEnable()
467 uint32_t istrReg = L2CACHEC->LOCKDOWN[masterId].REG9_I_LOCKDOWN; in L2CACHE_LockdownByWayEnable()
472 L2CACHEC->LOCKDOWN[masterId].REG9_D_LOCKDOWN = dataReg | mask; in L2CACHE_LockdownByWayEnable()
474 L2CACHEC->LOCKDOWN[masterId].REG9_I_LOCKDOWN = istrReg | mask; in L2CACHE_LockdownByWayEnable()
479 L2CACHEC->LOCKDOWN[masterId].REG9_D_LOCKDOWN = dataReg & ~mask; in L2CACHE_LockdownByWayEnable()
481 L2CACHEC->LOCKDOWN[masterId].REG9_I_LOCKDOWN = istrReg & ~mask; in L2CACHE_LockdownByWayEnable()
Dfsl_cache.h388 void L2CACHE_LockdownByWayEnable(uint32_t masterId, uint32_t mask, bool enable);
/hal_nxp-latest/mcux/mcux-sdk/devices/MIMXRT1173/drivers/cm7/
Dfsl_cache.c457 void L2CACHE_LockdownByWayEnable(uint32_t masterId, uint32_t mask, bool enable) in L2CACHE_LockdownByWayEnable() argument
464 assert(masterId < L2CACHE_LOCKDOWN_REGNUM); in L2CACHE_LockdownByWayEnable()
466 uint32_t dataReg = L2CACHEC->LOCKDOWN[masterId].REG9_D_LOCKDOWN; in L2CACHE_LockdownByWayEnable()
467 uint32_t istrReg = L2CACHEC->LOCKDOWN[masterId].REG9_I_LOCKDOWN; in L2CACHE_LockdownByWayEnable()
472 L2CACHEC->LOCKDOWN[masterId].REG9_D_LOCKDOWN = dataReg | mask; in L2CACHE_LockdownByWayEnable()
474 L2CACHEC->LOCKDOWN[masterId].REG9_I_LOCKDOWN = istrReg | mask; in L2CACHE_LockdownByWayEnable()
479 L2CACHEC->LOCKDOWN[masterId].REG9_D_LOCKDOWN = dataReg & ~mask; in L2CACHE_LockdownByWayEnable()
481 L2CACHEC->LOCKDOWN[masterId].REG9_I_LOCKDOWN = istrReg & ~mask; in L2CACHE_LockdownByWayEnable()
Dfsl_cache.h388 void L2CACHE_LockdownByWayEnable(uint32_t masterId, uint32_t mask, bool enable);
/hal_nxp-latest/mcux/mcux-sdk/devices/MIMXRT1171/drivers/cm7/
Dfsl_cache.c457 void L2CACHE_LockdownByWayEnable(uint32_t masterId, uint32_t mask, bool enable) in L2CACHE_LockdownByWayEnable() argument
464 assert(masterId < L2CACHE_LOCKDOWN_REGNUM); in L2CACHE_LockdownByWayEnable()
466 uint32_t dataReg = L2CACHEC->LOCKDOWN[masterId].REG9_D_LOCKDOWN; in L2CACHE_LockdownByWayEnable()
467 uint32_t istrReg = L2CACHEC->LOCKDOWN[masterId].REG9_I_LOCKDOWN; in L2CACHE_LockdownByWayEnable()
472 L2CACHEC->LOCKDOWN[masterId].REG9_D_LOCKDOWN = dataReg | mask; in L2CACHE_LockdownByWayEnable()
474 L2CACHEC->LOCKDOWN[masterId].REG9_I_LOCKDOWN = istrReg | mask; in L2CACHE_LockdownByWayEnable()
479 L2CACHEC->LOCKDOWN[masterId].REG9_D_LOCKDOWN = dataReg & ~mask; in L2CACHE_LockdownByWayEnable()
481 L2CACHEC->LOCKDOWN[masterId].REG9_I_LOCKDOWN = istrReg & ~mask; in L2CACHE_LockdownByWayEnable()
Dfsl_cache.h388 void L2CACHE_LockdownByWayEnable(uint32_t masterId, uint32_t mask, bool enable);
/hal_nxp-latest/mcux/mcux-sdk/devices/MIMXRT1172/drivers/cm7/
Dfsl_cache.c457 void L2CACHE_LockdownByWayEnable(uint32_t masterId, uint32_t mask, bool enable) in L2CACHE_LockdownByWayEnable() argument
464 assert(masterId < L2CACHE_LOCKDOWN_REGNUM); in L2CACHE_LockdownByWayEnable()
466 uint32_t dataReg = L2CACHEC->LOCKDOWN[masterId].REG9_D_LOCKDOWN; in L2CACHE_LockdownByWayEnable()
467 uint32_t istrReg = L2CACHEC->LOCKDOWN[masterId].REG9_I_LOCKDOWN; in L2CACHE_LockdownByWayEnable()
472 L2CACHEC->LOCKDOWN[masterId].REG9_D_LOCKDOWN = dataReg | mask; in L2CACHE_LockdownByWayEnable()
474 L2CACHEC->LOCKDOWN[masterId].REG9_I_LOCKDOWN = istrReg | mask; in L2CACHE_LockdownByWayEnable()
479 L2CACHEC->LOCKDOWN[masterId].REG9_D_LOCKDOWN = dataReg & ~mask; in L2CACHE_LockdownByWayEnable()
481 L2CACHEC->LOCKDOWN[masterId].REG9_I_LOCKDOWN = istrReg & ~mask; in L2CACHE_LockdownByWayEnable()
Dfsl_cache.h388 void L2CACHE_LockdownByWayEnable(uint32_t masterId, uint32_t mask, bool enable);
/hal_nxp-latest/mcux/mcux-sdk/devices/MIMXRT1166/drivers/cm7/
Dfsl_cache.c457 void L2CACHE_LockdownByWayEnable(uint32_t masterId, uint32_t mask, bool enable) in L2CACHE_LockdownByWayEnable() argument
464 assert(masterId < L2CACHE_LOCKDOWN_REGNUM); in L2CACHE_LockdownByWayEnable()
466 uint32_t dataReg = L2CACHEC->LOCKDOWN[masterId].REG9_D_LOCKDOWN; in L2CACHE_LockdownByWayEnable()
467 uint32_t istrReg = L2CACHEC->LOCKDOWN[masterId].REG9_I_LOCKDOWN; in L2CACHE_LockdownByWayEnable()
472 L2CACHEC->LOCKDOWN[masterId].REG9_D_LOCKDOWN = dataReg | mask; in L2CACHE_LockdownByWayEnable()
474 L2CACHEC->LOCKDOWN[masterId].REG9_I_LOCKDOWN = istrReg | mask; in L2CACHE_LockdownByWayEnable()
479 L2CACHEC->LOCKDOWN[masterId].REG9_D_LOCKDOWN = dataReg & ~mask; in L2CACHE_LockdownByWayEnable()
481 L2CACHEC->LOCKDOWN[masterId].REG9_I_LOCKDOWN = istrReg & ~mask; in L2CACHE_LockdownByWayEnable()
Dfsl_cache.h388 void L2CACHE_LockdownByWayEnable(uint32_t masterId, uint32_t mask, bool enable);
/hal_nxp-latest/mcux/mcux-sdk/devices/MIMXRT1175/drivers/cm7/
Dfsl_cache.c457 void L2CACHE_LockdownByWayEnable(uint32_t masterId, uint32_t mask, bool enable) in L2CACHE_LockdownByWayEnable() argument
464 assert(masterId < L2CACHE_LOCKDOWN_REGNUM); in L2CACHE_LockdownByWayEnable()
466 uint32_t dataReg = L2CACHEC->LOCKDOWN[masterId].REG9_D_LOCKDOWN; in L2CACHE_LockdownByWayEnable()
467 uint32_t istrReg = L2CACHEC->LOCKDOWN[masterId].REG9_I_LOCKDOWN; in L2CACHE_LockdownByWayEnable()
472 L2CACHEC->LOCKDOWN[masterId].REG9_D_LOCKDOWN = dataReg | mask; in L2CACHE_LockdownByWayEnable()
474 L2CACHEC->LOCKDOWN[masterId].REG9_I_LOCKDOWN = istrReg | mask; in L2CACHE_LockdownByWayEnable()
479 L2CACHEC->LOCKDOWN[masterId].REG9_D_LOCKDOWN = dataReg & ~mask; in L2CACHE_LockdownByWayEnable()
481 L2CACHEC->LOCKDOWN[masterId].REG9_I_LOCKDOWN = istrReg & ~mask; in L2CACHE_LockdownByWayEnable()
Dfsl_cache.h388 void L2CACHE_LockdownByWayEnable(uint32_t masterId, uint32_t mask, bool enable);
/hal_nxp-latest/mcux/mcux-sdk/devices/MIMX8ML6/drivers/
Dfsl_cache.c457 void L2CACHE_LockdownByWayEnable(uint32_t masterId, uint32_t mask, bool enable) in L2CACHE_LockdownByWayEnable() argument
464 assert(masterId < L2CACHE_LOCKDOWN_REGNUM); in L2CACHE_LockdownByWayEnable()
466 uint32_t dataReg = L2CACHEC->LOCKDOWN[masterId].REG9_D_LOCKDOWN; in L2CACHE_LockdownByWayEnable()
467 uint32_t istrReg = L2CACHEC->LOCKDOWN[masterId].REG9_I_LOCKDOWN; in L2CACHE_LockdownByWayEnable()
472 L2CACHEC->LOCKDOWN[masterId].REG9_D_LOCKDOWN = dataReg | mask; in L2CACHE_LockdownByWayEnable()
474 L2CACHEC->LOCKDOWN[masterId].REG9_I_LOCKDOWN = istrReg | mask; in L2CACHE_LockdownByWayEnable()
479 L2CACHEC->LOCKDOWN[masterId].REG9_D_LOCKDOWN = dataReg & ~mask; in L2CACHE_LockdownByWayEnable()
481 L2CACHEC->LOCKDOWN[masterId].REG9_I_LOCKDOWN = istrReg & ~mask; in L2CACHE_LockdownByWayEnable()
Dfsl_cache.h388 void L2CACHE_LockdownByWayEnable(uint32_t masterId, uint32_t mask, bool enable);
/hal_nxp-latest/mcux/mcux-sdk/devices/MIMXRT1187/drivers/cm7/
Dfsl_cache.c457 void L2CACHE_LockdownByWayEnable(uint32_t masterId, uint32_t mask, bool enable) in L2CACHE_LockdownByWayEnable() argument
464 assert(masterId < L2CACHE_LOCKDOWN_REGNUM); in L2CACHE_LockdownByWayEnable()
466 uint32_t dataReg = L2CACHEC->LOCKDOWN[masterId].REG9_D_LOCKDOWN; in L2CACHE_LockdownByWayEnable()
467 uint32_t istrReg = L2CACHEC->LOCKDOWN[masterId].REG9_I_LOCKDOWN; in L2CACHE_LockdownByWayEnable()
472 L2CACHEC->LOCKDOWN[masterId].REG9_D_LOCKDOWN = dataReg | mask; in L2CACHE_LockdownByWayEnable()
474 L2CACHEC->LOCKDOWN[masterId].REG9_I_LOCKDOWN = istrReg | mask; in L2CACHE_LockdownByWayEnable()
479 L2CACHEC->LOCKDOWN[masterId].REG9_D_LOCKDOWN = dataReg & ~mask; in L2CACHE_LockdownByWayEnable()
481 L2CACHEC->LOCKDOWN[masterId].REG9_I_LOCKDOWN = istrReg & ~mask; in L2CACHE_LockdownByWayEnable()

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