1 /* 2 * Copyright 2021 NXP 3 * All rights reserved. 4 * 5 * SPDX-License-Identifier: BSD-3-Clause 6 */ 7 8 #ifndef _FSL_SDIOSLV_SDU_H_ 9 #define _FSL_SDIOSLV_SDU_H_ 10 11 #include "fsl_common.h" 12 #include "cis_table.h" 13 14 /*! 15 * @addtogroup sdioslv_sdu_driver 16 * @{ 17 */ 18 19 /******************************************************************************* 20 * Definitions 21 ******************************************************************************/ 22 23 #define SDU_INT_CPU_NUM kSDIOSLV_INT_CPUNum3 24 #define SDU_USED_FUN_NUM 1U 25 #define SDU_USED_PORT_NUM 32U 26 27 /*! @brief Maximum functions supported by SDU */ 28 #define SDU_MAX_FUNCTION_NUM 7U 29 30 /*! @brief Maximum data ports supported by SDU per function */ 31 #define SDU_MAX_PORT_NUM (32U) 32 33 #define sdu_fbr_fnN_base(FN) (SDU_FN0_CARD_BASE + 0x10U + (0x10U * (FN))) 34 #define sdu_fbr_fnN_fn_code(FN) (sdu_fbr_fnN_base(FN) + 0x0U) 35 36 #define sdu_fbr_fnN_fn_code_code_HI 3U 37 #define sdu_fbr_fnN_fn_code_code_LO 0U 38 39 40 /*! @brief MACRO used to access register of SDU */ 41 #define SDU_REGS8(x) (*((volatile uint8_t *)x)) 42 /*! @brief MACRO used to read SDU register */ 43 #define SDU_READ_REGS8(reg, val) ((val) = SDU_REGS8(reg)) 44 /*! @brief MACRO used to write SDU register */ 45 #define SDU_WRITE_REGS8(reg, val) (SDU_REGS8(reg) = (val)) 46 /*! @brief MACRO used to set bits of SDU register */ 47 #define SDU_REGS8_SETBITS(reg, val) (SDU_REGS8(reg) |= (uint8_t)(val)) 48 /*! @brief MACRO used to clear bits of SDU register */ 49 #define SDU_REGS8_CLRBITS(reg, val) (SDU_REGS8(reg) = (uint8_t)(SDU_REGS8(reg) & ~(val))) 50 51 /*! @brief Address of scratch register (group 2, offset 0) within function */ 52 #define SDU_SCRATCH2_OFFSET0_ADDR 0xE8U 53 54 /*! @brief SDU SDIO configuration base (SDU_FN0_CARD_BASE defined in device) */ 55 #define SDU_SDIO_CFG_BASE SDU_FN0_CARD_BASE 56 57 /*! @brief Address offset of CCR between two functions */ 58 #define SDIO_CCR_FUNC_OFFSET 0x00000100U 59 60 /*! @brief SDIO I/O Enable */ 61 #define SDIO_IO_ENABLE (SDU_SDIO_CFG_BASE + 0x02U) 62 63 /*! @brief SDIO Bus Speed Select */ 64 #define SDIO_FUNC0_BSS (SDU_SDIO_CFG_BASE + 0x13U) 65 #define SDIO_FUNC0_BSS_SUPPORT_MASK 0x1U 66 #define SDIO_FUNC0_BSS_MODE_BIT 0x1U 67 #define SDIO_FUNC0_BSS_MODE_MASK 0xEU 68 69 /*! @brief Interrupt mask register for function 0 */ 70 #define SDIO_CCR_FUNC0_CARD_INT_MSK (SDU_SDIO_CFG_BASE + 0x91U) 71 72 /*! @brief Bit Def. Host Transfer Status (HostTransferStatus) */ 73 #define SDIO_CCR_HOST_DnLdReStart (1U << 0U) 74 #define SDIO_CCR_HOST_UpLdReStart (1U << 1U) 75 #define SDIO_CCR_HOST_DnLdCRC_err (1U << 2U) 76 77 /*! @brief Bit Def. Card To Host Interrupt Event (CardToHostEvent) */ 78 #define SDIO_CCR_CS_DnLdRdy (1U << 0U) 79 #define SDIO_CCR_CS_UpLdRdy (1U << 1U) 80 #define SDIO_CCR_CS_ReadCISRdy (1U << 2U) 81 #define SDIO_CCR_CS_CmdUpLdRdy (1U << 6U) 82 #define SDIO_CCR_CS_CmdDnLdRdy (1U << 7U) 83 84 /*! @brief Bit Def. Card Interrupt Mask (CardIntMask) */ 85 #define SDIO_CCR_CIM_DnLdOvr (1U << 0U) 86 #define SDIO_CCR_CIM_UpLdOvr (1U << 1U) 87 #define SDIO_CCR_CIM_Abort (1U << 2U) 88 #define SDIO_CCR_CIM_PwrDn (1U << 3U) 89 #define SDIO_CCR_CIM_PwrUp (1U << 4U) 90 #define SDIO_CCR_CIM_CmdUpLdOvr (1U << 10U) 91 #define SDIO_CCR_CIM_CmdDnLdOvr (1U << 11U) 92 93 #define SDIO_CCR_CIM_MASK 0x0C07U 94 95 /*! @brief Bit Def. Card Interrupt Status (CardIntStatus) */ 96 #define SDIO_CCR_CIC_DnLdOvr ((uint32_t)1U << 0U) 97 #define SDIO_CCR_CIC_UpLdOvr ((uint32_t)1U << 1U) 98 #define SDIO_CCR_CIC_Abort ((uint32_t)1U << 2U) 99 #define SDIO_CCR_CIC_PwrDn ((uint32_t)1U << 3U) 100 #define SDIO_CCR_CIC_PwrUp ((uint32_t)1U << 4U) 101 #define SDIO_CCR_CIC_CmdUpLdOvr ((uint32_t)1U << 10U) 102 #define SDIO_CCR_CIC_CmdDnLdOvr ((uint32_t)1U << 11U) 103 #define SDIO_CCR_CIC_ALL \ 104 (SDIO_CCR_CIC_DnLdOvr | SDIO_CCR_CIC_UpLdOvr | SDIO_CCR_CIC_CmdUpLdOvr | SDIO_CCR_CIC_CmdDnLdOvr) 105 106 #define SDIO_CCR_CIC_MASK 0x0C1FU 107 108 /*! @brief Bit Def. Default setting ISR bit clear after read (CardIntMode) */ 109 #define CARD_INT_MODE_MSK 0x00000C03U 110 111 /*! @brief Bit Def. Command port configuration register (CmdPortConfig) */ 112 #define CMD_TX_LEN_BIT_OFFSET (0U) 113 #define CMD_RD_LEN_BIT_OFFSET (2U) 114 115 /*! @brief Bit Def. Config2 register (Config2) */ 116 #define CONFIG2_ASYNC_INT (1U << 3U) 117 #define CONFIG2_CMD53_NEW_MODE (1U << 8U) 118 #define CONFIG2_DNLD_RDY_AUTO_RESET (1U << 10U) 119 #define CONFIG2_UPLD_RDY_AUTO_RESET (1U << 11U) 120 #define CONFIG2_TX_LEN_BIT_OFFSET (12U) 121 #define CONFIG2_RD_LEN_BIT_OFFSET (14U) 122 123 #define CONFIG2_DEFAULT_SETTING \ 124 (CONFIG2_ASYNC_INT | CONFIG2_CMD53_NEW_MODE | CONFIG2_DNLD_RDY_AUTO_RESET | CONFIG2_UPLD_RDY_AUTO_RESET) 125 126 127 /*! @name Driver version */ 128 /*@{*/ 129 /*! @brief Driver version 1.0.0. */ 130 #define FSL_SDIOSLV_SDU_DRIVER_VERSION (MAKE_VERSION(1U, 0U, 0U)) 131 /*@}*/ 132 133 /*! @brief SDIO status */ 134 enum _sdioslv_status 135 { 136 kStatus_SDIOSLV_CmdPending = MAKE_STATUS(kStatusGroup_SDIOSLV, 0U), /*!< previous command is under working. */ 137 kStatus_SDIOSLV_SendFull = MAKE_STATUS(kStatusGroup_SDIOSLV, 1U), /*!< all data slots are occupied. */ 138 kStatus_SDIOSLV_FuncEnabled = MAKE_STATUS(kStatusGroup_SDIOSLV, 2U), /*!< function enabled */ 139 kStatus_SDIOSLV_FuncDisabled = MAKE_STATUS(kStatusGroup_SDIOSLV, 3U), /*!< function disabled */ 140 kStatus_SDIOSLV_FuncSuspended = MAKE_STATUS(kStatusGroup_SDIOSLV, 4U), /*!< function suspended */ 141 kStatus_SDIOSLV_FuncResumed = MAKE_STATUS(kStatusGroup_SDIOSLV, 5U), /*!< function resumed */ 142 kStatus_SDIOSLV_FuncSendComplete = MAKE_STATUS(kStatusGroup_SDIOSLV, 6U), /*!< function send complete */ 143 kStatus_SDIOSLV_FuncReadComplete = MAKE_STATUS(kStatusGroup_SDIOSLV, 7U), /*!< function read complete */ 144 kStatus_SDIOSLV_FuncRequestBuffer = MAKE_STATUS(kStatusGroup_SDIOSLV, 8U), /*!< function request read buffer */ 145 }; 146 147 /*! @brief SDIO card function number */ 148 typedef enum _sdioslv_int_cpu_num 149 { 150 kSDIOSLV_INT_CPUNum1 = 1U, /*!< sdio interrupt to CPU1 */ 151 kSDIOSLV_INT_CPUNum2 = 2U, /*!< sdio interrupt to CPU2 */ 152 kSDIOSLV_INT_CPUNum3 = 4U, /*!< sdio interrupt to CPU3 */ 153 } sdioslv_int_cpu_num_t; 154 155 /*! @brief SDIO card function number */ 156 typedef enum _sdioslv_func_num 157 { 158 kSDIOSLV_FunctionNum1 = 1U, /*!< sdio function1 */ 159 kSDIOSLV_FunctionNum2 = 2U, /*!< sdio function2 */ 160 kSDIOSLV_FunctionNum3 = 3U, /*!< sdio function3 */ 161 kSDIOSLV_FunctionNum4 = 4U, /*!< sdio function4 */ 162 kSDIOSLV_FunctionNum5 = 5U, /*!< sdio function5 */ 163 kSDIOSLV_FunctionNum6 = 6U, /*!< sdio function6 */ 164 kSDIOSLV_FunctionNum7 = 7U, /*!< sdio function7 */ 165 } sdioslv_func_t; 166 167 /*! @brief SDIO port number (per function) */ 168 typedef enum _sdioslv_port_num 169 { 170 kSDIOSLV_DataPortNum0 = 0U, /*!< sdio dataport0 */ 171 kSDIOSLV_DataPortNum1 = 1U, /*!< sdio dataport1 */ 172 kSDIOSLV_DataPortNum2 = 2U, /*!< sdio dataport2 */ 173 kSDIOSLV_DataPortNum3 = 3U, /*!< sdio dataport3 */ 174 kSDIOSLV_DataPortNum4 = 4U, /*!< sdio dataport4 */ 175 kSDIOSLV_DataPortNum5 = 5U, /*!< sdio dataport5 */ 176 kSDIOSLV_DataPortNum6 = 6U, /*!< sdio dataport6 */ 177 kSDIOSLV_DataPortNum7 = 7U, /*!< sdio dataport7 */ 178 kSDIOSLV_DataPortNum8 = 8U, /*!< sdio dataport8 */ 179 kSDIOSLV_DataPortNum9 = 9U, /*!< sdio dataport9 */ 180 kSDIOSLV_DataPortNum10 = 10U, /*!< sdio dataport10 */ 181 kSDIOSLV_DataPortNum11 = 11U, /*!< sdio dataport11 */ 182 kSDIOSLV_DataPortNum12 = 12U, /*!< sdio dataport12 */ 183 kSDIOSLV_DataPortNum13 = 13U, /*!< sdio dataport13 */ 184 kSDIOSLV_DataPortNum14 = 14U, /*!< sdio dataport14 */ 185 kSDIOSLV_DataPortNum15 = 15U, /*!< sdio dataport15 */ 186 kSDIOSLV_DataPortNum16 = 16U, /*!< sdio dataport16 */ 187 kSDIOSLV_DataPortNum17 = 17U, /*!< sdio dataport17 */ 188 kSDIOSLV_DataPortNum18 = 18U, /*!< sdio dataport18 */ 189 kSDIOSLV_DataPortNum19 = 19U, /*!< sdio dataport19 */ 190 kSDIOSLV_DataPortNum20 = 20U, /*!< sdio dataport20 */ 191 kSDIOSLV_DataPortNum21 = 21U, /*!< sdio dataport21 */ 192 kSDIOSLV_DataPortNum22 = 22U, /*!< sdio dataport22 */ 193 kSDIOSLV_DataPortNum23 = 23U, /*!< sdio dataport23 */ 194 kSDIOSLV_DataPortNum24 = 24U, /*!< sdio dataport24 */ 195 kSDIOSLV_DataPortNum25 = 25U, /*!< sdio dataport25 */ 196 kSDIOSLV_DataPortNum26 = 26U, /*!< sdio dataport26 */ 197 kSDIOSLV_DataPortNum27 = 27U, /*!< sdio dataport27 */ 198 kSDIOSLV_DataPortNum28 = 28U, /*!< sdio dataport28 */ 199 kSDIOSLV_DataPortNum29 = 29U, /*!< sdio dataport29 */ 200 kSDIOSLV_DataPortNum30 = 30U, /*!< sdio dataport30 */ 201 kSDIOSLV_DataPortNum31 = 31U, /*!< sdio dataport31 */ 202 kSDIOSLV_CmdPortNum0 = 32U, /*!< sdio cmdport0 */ 203 } sdioslv_port_t; 204 205 /*! @brief SDIO Bus Speed */ 206 typedef enum _sdioslv_bus_speed 207 { 208 kSDIOSLV_SDR12_MODE = 0U, /*!< SDR12 mode => 25Mhz */ 209 kSDIOSLV_SDR25_MODE = 1U, /*!< SDR25 mode => 50Mhz */ 210 kSDIOSLV_SDR50_MODE = 2U, /*!< SDR50 mode => 100Mhz */ 211 kSDIOSLV_SDR104_MODE = 3U, /*!< SDR104 mode => 208Mhz */ 212 } sdioslv_bus_speed_t; 213 214 /*! @brief Scratch register group */ 215 typedef enum _sdioslv_scratch_group 216 { 217 kSDIOSLV_ScratchGroup0 = 0U, /*!< sdio scratch1 in FW18 0xnD4 n:1..7 16 bits */ 218 kSDIOSLV_ScratchGroup1 = 1U, /*!< sdio scratch2 in FW18 0xnB0 n:1..7 16 bits */ 219 kSDIOSLV_ScratchGroup2 = 2U, /*!< sdio scratch group 2 in SDU 0xnE8 n:1..7 32 bits */ 220 kSDIOSLV_ScratchGroup3 = 3U, /*!< sdio scratch group 3 in SDU 0xnEC n:1..7 32 bits */ 221 kSDIOSLV_ScratchGroup4 = 4U, /*!< sdio scratch group 4 in SDU 0xnF0 n:1..7 32 bits */ 222 kSDIOSLV_ScratchGroup5 = 5U, /*!< sdio scratch group 5 in SDU 0xnF4 n:1..7 32 bits */ 223 kSDIOSLV_ScratchGroup6 = 6U, /*!< sdio scratch group 6 in SDU 0xnF8 n:1..7 32 bits */ 224 kSDIOSLV_ScratchGroup7 = 7U, /*!< sdio scratch group 7 in SDU 0xnFC n:1..7 32 bits */ 225 } sdioslv_scratch_group_t; 226 227 /*! @brief Scratch register offset in a group */ 228 typedef enum _sdioslv_scratch_offset 229 { 230 kSDIOSLV_ScratchOffset0 = 0U, /*!< sdio scratchoffset0 */ 231 kSDIOSLV_ScratchOffset1 = 1U, /*!< sdio scratchoffset1 */ 232 kSDIOSLV_ScratchOffset3 = 3U, /*!< sdio scratchoffset2 */ 233 kSDIOSLV_ScratchOffset4 = 4U, /*!< sdio scratchoffset3 */ 234 } sdioslv_scratch_offset_t; 235 236 237 /*! @brief SDU register map version 4 */ 238 typedef struct _sdioslv_sdu_regmap 239 { 240 uint32_t HostToCardEvent; /*!< 0x100/200.../700 */ 241 uint32_t HostIntCause; /*!< 0x104/204.../704 */ 242 uint32_t HostIntMask; /*!< 0x108/208.../708 */ 243 uint32_t HostIntStatus; /*!< 0x10C/20C.../70C */ 244 uint32_t RdBitMap; /*!< 0x110/210.../710 */ 245 uint32_t WrBitMap; /*!< 0x114/214.../714 */ 246 uint16_t RdLen[32]; /*!< 0x118/218.../718 */ 247 uint8_t HostTransferStatus; /*!< 0x158/258.../758 */ 248 uint8_t FunctionCardIntMsk; /*!< 0x159/259.../759 */ 249 uint8_t Card_Q_PTR_RANGE0; /*!< 0x15A/25A.../75A */ 250 uint8_t Card_Q_PTR_RANGE1; /*!< 0x15B/25B.../75B */ 251 uint16_t CardToHostEvent; /*!< 0x15C/25C.../75C */ 252 uint8_t reserved2[2]; 253 uint32_t CardIntMask; /*!< 0x160/260.../760 */ 254 uint32_t CardIntStatus; /*!< 0x164/264.../764 */ 255 uint32_t CardIntMode; /*!< 0x168/268.../768 */ 256 uint32_t SqReadBase; /*!< 0x16C/26C.../76C */ 257 uint32_t SqWriteBase; /*!< 0x170/270.../770 */ 258 uint8_t RdIdx; /*!< 0x174/274.../774 */ 259 uint8_t WrIdx; /*!< 0x175/275.../775 */ 260 uint8_t Reserved6[2]; /*!< 0x176/276.../776 */ 261 uint8_t Card_APU_SLP_RDY_EN; /*!< 0x178/278.../778 */ 262 uint8_t Reserved7[3]; 263 uint8_t Card_HOST_ERR_WKUP_EN; /*!< 0x17C/27C.../77C */ 264 uint8_t Reserved8[3]; 265 uint8_t HOST_ERR_CMD0; /*!< 0x180/280.../780 */ 266 uint8_t HOST_ERR_CMD1; /*!< 0x181/281.../781 */ 267 uint8_t HOST_ERR_CMD2; /*!< 0x182/282.../782 */ 268 uint8_t HOST_ERR_CMD3; /*!< 0x183/283.../783 */ 269 uint8_t HOST_ERR_CMD4; /*!< 0x184/284.../784 */ 270 uint8_t HOST_ERR_CMD5; /*!< 0x185/285.../785 */ 271 uint8_t Reserved9[2]; 272 uint32_t PktWrBitmapClr; /*!< 0x188/288.../788 */ 273 uint32_t PktRdBitmapClr; /*!< 0x18C/28C.../78C */ 274 uint32_t HostIntActMskEn; /*!< 0x190/290.../790 */ 275 uint32_t HostIntActMskClr; /*!< 0x194/294.../794 */ 276 uint32_t HostIntActMskStat; /*!< 0x198/298.../798 */ 277 uint32_t CardIntActMskEn; /*!< 0x19C/29C.../79C */ 278 uint32_t CardIntActMskClr; /*!< 0x1A0/2A0.../7A0 */ 279 uint32_t CardIntActMskStat; /*!< 0x1A4/2A4.../7A4 */ 280 uint32_t TestbusBitSelect; /*!< 0x1A8/2A8.../7A8 */ 281 uint32_t TestbusBitSelect1; /*!< 0x1AC/2AC.../7AC */ 282 uint16_t Scratch2; /*!< 0x1B0/2B0.../7B0 */ 283 uint8_t Scratch[6]; /*!< 0x1B2/2B2.../7B2 */ 284 uint32_t CmdPortSqWriteBase; /*!< 0x1B8/2B8.../7B8 */ 285 uint32_t CmdPortSqReadBase; /*!< 0x1BC/2BC.../7BC */ 286 uint16_t CmdPortRdLen; /*!< 0x1C0/2C0.../7C0 */ 287 uint16_t Reserved10; /*!< 0x1C2/2C2.../7C2 */ 288 uint32_t CmdPortConfig; /*!< 0x1C4/2C4.../7C4 */ 289 uint8_t ChipRev; /*!< 0x1C8/2C8.../7C8 */ 290 uint8_t reserved11; 291 uint8_t SDUMinorIPRev; /*!< 0x1CA/2CA.../7CA */ 292 uint8_t SDUMajorIPRev; /*!< 0x1CB/2CB.../7CB */ 293 uint32_t Card_PKT_END_RADDR; /*!< 0x1CC/2CC.../7CC */ 294 uint32_t Card_PKT_END_WADDR; /*!< 0x1D0/2D0.../7D0 */ 295 uint16_t Scratch1; /*!< 0x1D4/2D4.../7D4 */ 296 uint8_t Ocr2; /*!< 0x1D6/2D6.../7D6 */ 297 uint8_t Config; /*!< 0x1D7/2D7.../7D7 */ 298 uint32_t Config2; /*!< 0x1D8/2D8.../7D8 */ 299 uint32_t Debug; /*!< 0x1DC/2DC.../7DC */ 300 uint32_t DmaAddr; /*!< 0x1E0/2E0.../7E0 */ 301 uint8_t IoPort[3]; /*!< 0x1E4/2E4.../7E4 */ 302 } sdioslv_sdu_regmap_t; 303 304 305 /*! @brief SDIO CIS table callback. */ 306 typedef void (*sdioslv_cis_table_callback_t)(const uint32_t SDU_BASE); 307 308 /*! @brief Data structure to configure SDIO handle for specific function. */ 309 typedef struct sdio_slave_config 310 { 311 uint8_t fun_num; /*!< SDIO function number (1..7). */ 312 sdioslv_int_cpu_num_t cpu_num; /*!< Specify interrupt should be generated to which CPU */ 313 uint8_t used_port_num; /*!< How many data ports are used inside this function */ 314 uint8_t cmd_tx_format; /*!< Command Tx length format. 0: no tx_len, 1: 2 bytes, 2: 3 bytes */ 315 uint8_t cmd_rd_format; /*!< Command Rx length format. 0: blk_num * blk_size, 1: CMD_PORT_RD_LEN */ 316 uint8_t data_tx_format; /*!< Data Tx length format. 0: no tx_len, 1: 2 bytes, 2: 3 bytes */ 317 uint8_t data_rd_format; /*!< Data Rx length format. 318 0: blk_num * blk_size, 1: PORT_RD_LEN[15:0], 2: PORT1_RD_LEN[7:0] && PORT0_RD_LEN[15:0] */ 319 sdioslv_cis_table_callback_t cis_table_callback; /*!< Callback function for initializing the CIS table. */ 320 } sdio_slave_config_t; 321 322 323 /******************************************************************************* 324 * API 325 ******************************************************************************/ 326 327 #if defined(__cplusplus) 328 extern "C" { 329 #endif 330 331 /*! 332 * @name Initialization and deinitialization 333 * @{ 334 */ 335 336 /*! 337 * @brief SDIOSLV Init0. 338 * 339 * Call this API to Init SDIOSLV phase0. 340 * 341 * @param void None. 342 * @retval void None. 343 */ 344 void SDIOSLV_Init0(void); 345 346 /*! 347 * @brief SDIOSLV Init1. 348 * 349 * Call this API to Init SDIOSLV phase1. 350 * 351 * @param base FN FSR pointer. 352 * @param config Configure for SDIO Slave. 353 * @retval #kStatus_Success command is ready to be sent to host driver. 354 * @retval #kStatus_InvalidArgument Invalid argument. 355 */ 356 status_t SDIOSLV_Init1(SDU_FN_CARD_Type *base, sdio_slave_config_t *config); 357 358 359 /* @} */ 360 361 /*! 362 * @name Cmd/Data Send/Refill 363 * @{ 364 */ 365 366 /*! 367 * @brief SDIOSLV send command. 368 * 369 * Call this API to send command to host driver. 370 * The callback is always invoked from theinterrupt context. 371 * 372 * @param regmap FN FSR pointer. 373 * @param data_addr Data Address. 374 * @param data_len Data Length. 375 * @retval #kStatus_Success command is ready to be sent to host driver. 376 * @retval #kStatus_InvalidArgument Invalid argument. 377 */ 378 status_t SDIOSLV_SendCmdNonBlocking(sdioslv_sdu_regmap_t *regmap, uint8_t *data_addr, uint16_t data_len); 379 380 /*! 381 * @brief SDIOSLV provide command buffer. 382 * 383 * Call this API to provide receive command buffer to SDU driver. 384 * 385 * @param regmap FN FSR pointer. 386 * @param data_addr Data Address. 387 * @param data_len Data Length. 388 * @retval #kStatus_Success buffer refill sucessfully. 389 * @retval #kStatus_Fail fail to refill buffer. 390 */ 391 status_t SDIOSLV_RefillCmdBuffer(sdioslv_sdu_regmap_t *regmap, uint8_t *data_addr); 392 393 /*! 394 * @brief SDIOSLV send data transfer. 395 * 396 * Call this API to send data to host driver. 397 * The callback is always invoked from theinterrupt context. 398 * 399 * @param regmap FN FSR pointer. 400 * @param port Data Port. 401 * @param data_addr Data Address. 402 * @param data_len Data Length. 403 * @retval #kStatus_Success buffer is added to data slot with problem. 404 * @retval #kStatus_InvalidArgument Invalid argument. 405 * @retval #kStatus_SDIOSLV_SendFull all data slots are occupied, application 406 */ 407 status_t SDIOSLV_SendDataNonBlocking(sdioslv_sdu_regmap_t *regmap, sdioslv_port_t tx_port, uint8_t *data_addr, uint16_t data_len); 408 409 /*! 410 * @brief SDIOSLV provide receive data buffer. 411 * 412 * Call this API to provide receive data buffer to SDU driver. 413 * 414 * @param regmap FN FSR pointer. 415 * @param port Data Port. 416 * @param data_addr Data Address. 417 * @param data_len Data Length. 418 * @retval #kStatus_Success refill buffer sucessfully. 419 * @retval #kStatus_Fail fail to refill buffer. 420 */ 421 status_t SDIOSLV_RefillDataBuffer(sdioslv_sdu_regmap_t *regmap, sdioslv_port_t port, uint8_t *data_addr); 422 423 /* @} */ 424 425 /*! 426 * @name Control and Status 427 * @{ 428 */ 429 430 /*! 431 * @brief Get SDIO bus speed selection. 432 * 433 * Call this API to get current bus speed selected for SDIO. 434 * 435 * @param void None. 436 * @retval sdioslv_bus_speed_t Bus speed selected for SDIO. 437 */ 438 sdioslv_bus_speed_t SDIOSLV_GetBusSpeed(void); 439 440 /*! 441 * @brief Get SDIO the block size in FBR. 442 * 443 * For block mode, block size equals to block size in FBR. 444 * 445 * @param handle Created by SDIOSLV_CreateHanle(). 446 * @retval the block size in FBR. 447 */ 448 uint32_t SDIOSLV_GetBlockSize(uint8_t fn_num); 449 450 /* @} */ 451 452 /*! 453 * @name Scratch register read/write 454 * @{ 455 */ 456 457 /*! 458 * @brief SDIOSLV read scratch register of SDU. 459 * 460 * Call this API to read scratch register of SDU (based on group and offset). 461 * 462 * @param fun_num Specify which function. 463 * @param group Specify which group scratch register. 464 * @param offset Specify offset of the scratch group. 465 * @param value Value read from the register. 466 * @retval #kStatus_Success read sucessfully. 467 * @retval #kStatus_Fail fail to read. 468 */ 469 status_t SDIOSLV_ReadScratchRegister(sdioslv_func_t fun_num, 470 sdioslv_scratch_group_t group, 471 sdioslv_scratch_offset_t offset, 472 uint8_t *value); 473 474 /*! 475 * @brief SDIOSLV write value to scratch register of SDU. 476 * 477 * Call this API to write value to scratch register of SDU (based on group and offset). 478 * 479 * @param fun_num Specify which function. 480 * @param group Specify which group scratch register. 481 * @param offset Specify offset of the scratch group. 482 * @param value Value write to the register. 483 * @retval #kStatus_Success write sucessfully. 484 * @retval #kStatus_Fail fail to write. 485 */ 486 status_t SDIOSLV_WriteScratchRegister(sdioslv_func_t fun_num, 487 sdioslv_scratch_group_t group, 488 sdioslv_scratch_offset_t offset, 489 uint8_t value); 490 491 /* @} */ 492 493 #if defined(__cplusplus) 494 } 495 #endif 496 497 /* @}*/ 498 499 #endif /* _FSL_SDIOSLV_SDU_H_ */ 500
