1 /* 2 * Copyright 2021-2022 NXP 3 * All rights reserved. 4 * 5 * SPDX-License-Identifier: BSD-3-Clause 6 */ 7 #ifndef FSL_RTD_CMC_H_ 8 #define FSL_RTD_CMC_H_ 9 10 #include "fsl_common.h" 11 12 /*! 13 * @addtogroup rtd_cmc 14 * @{ 15 */ 16 /******************************************************************************* 17 * Definitions 18 ******************************************************************************/ 19 /*! @name Driver version */ 20 /*! @{ */ 21 /*! @brief RTD_CMC driver version 2.0.2. */ 22 #define FSL_RTD_CMC_DRIVER_VERSION (MAKE_VERSION(2, 0, 2)) 23 /*! @} */ 24 25 /*! 26 * @brief RTD_CMC power mode Protection enumeration. 27 */ 28 enum _rtd_cmc_power_mode_protection 29 { 30 kRTDCMC_AllowSleepMode = CMC_RTD_PMPROT_AS_MASK, /*!< Allow Sleep mode. */ 31 kRTDCMC_AllowDeepSleepMode = CMC_RTD_PMPROT_ADS_MASK, /*!< Allow Deep Sleep mode. */ 32 kRTDCMC_AllowPowerDownMode = CMC_RTD_PMPROT_APD_MASK, /*!< Allow Power Down mode. */ 33 kRTDCMC_AllowDeepPowerDownMode = CMC_RTD_PMPROT_ADPD_MASK, /*!< Allow Deep Power Down mode. */ 34 kRTDCMC_AllowHoldMode = CMC_RTD_PMPROT_AHLD_MASK, /*!< Allow Hold mode. */ 35 kRTDCMC_AllowAllLowPowerModes = 36 (kRTDCMC_AllowSleepMode | kRTDCMC_AllowDeepSleepMode | kRTDCMC_AllowPowerDownMode | 37 kRTDCMC_AllowDeepPowerDownMode | kRTDCMC_AllowHoldMode), /*!< Allow all low power modes. */ 38 }; 39 40 /*! 41 * @brief Wake up sources from the previous low power mode entry. 42 */ 43 enum _rtd_cmc_wakeup_sources 44 { 45 kRTDCMC_WakeupFromResetInterruptOrPowerDown = 46 CMC_CKSTAT_WAKEUP(1U << 0U), /*!< Wakeup source is reset interrupt, or wake up from [Deep] Power Down. */ 47 kRTDCMC_WakeupFromDebugReuqest = CMC_CKSTAT_WAKEUP(1U << 1U), /*!< Wakeup source is debug request. */ 48 kRTDCMC_WakeupFromInterrupt = CMC_CKSTAT_WAKEUP(1U << 2U), /*!< Wakeup source is interrupt. */ 49 kRTDCMC_WakeupFromDMAWakeup = CMC_CKSTAT_WAKEUP(1U << 3U), /*!< Wakeup source is DMA Wakeup. */ 50 kRTDCMC_WakeupFromWUURequest = CMC_CKSTAT_WAKEUP(1U << 4U), /*!< Wakeup source is WUU request. */ 51 }; 52 53 /*! 54 * @brief System Reset Interrupt enable enumeration. 55 */ 56 enum _rtd_cmc_system_reset_interrupt_enable 57 { 58 kRTDCMC_InSystemProgrammingAccessPortResetInterruptEnable = 59 CMC_SRIE_ISP_AP_MASK, /*!< ISP_AP Reset interrupt enable. */ 60 kRTDCMC_LowPowerAcknowledgeTimeoutResetInterruptEnable = CMC_SRIE_LPACK_MASK, /*!< Low Power Acknowledge Timeout 61 Reset interrupt enable. */ 62 kRTDCMC_Watchdog0ResetInterruptEnable = CMC_SRIE_WDOG0_MASK, /*!< Watchdog 0 Reset interrupt enable. */ 63 kRTDCMC_SoftwareResetInterruptEnable = CMC_SRIE_SW_MASK, /*!< Software Reset interrupt enable. */ 64 kRTDCMC_LockupResetInterruptEnable = CMC_SRIE_LOCKUP_MASK, /*!< Lockup Reset interrupt enable. */ 65 kRTDCMC_AppDomainMuSystemResetInterruptEnable = CMC_SRIE_AD_MU_MASK, /* Application Domain MU System Reset 66 interrupt enable. */ 67 kRTDCMC_Watchdog1ResetInterruptEnable = CMC_SRIE_WDOG_S_RTD_MASK, /*!< Watchdog 1 Reset interrupt enable. */ 68 kRTDCMC_Watchdog5ResetInterruptEnable = CMC_SRIE_WDOG_HIFI4_MASK, /*!< Watchdog 5 Reset interrupt enable. */ 69 kRTDCMC_Watchdog2ResetInterruptEnable = CMC_SRIE_WDOG_FUSION_MASK, /*!< Watchdog 2 Reset interrupt enable. */ 70 }; 71 72 /*! 73 * @brief Power switch domain out of reset interrupt enable enumeration. 74 */ 75 enum _rtd_cmc_power_switch_domain_out_of_reset_interrupt_enable 76 { 77 kRTDCMC_FusionPSDomainOutOfResetInterruptEnable = CMC_RTD_PSDORIE_FUSION_MASK, /*!< Fusion power switch domain out 78 of reset interrupt enable. */ 79 kRTDCMC_FusionAlwaysOnPSDomainOutOfResetInterruptEnable = CMC_RTD_PSDORIE_FUSION_AO_MASK, /*!< Fusion always on 80 power switch domain out 81 of reset interrupt 82 enable. */ 83 }; 84 85 /*! 86 * @brief CMC System Reset Interrupt Status flag. 87 */ 88 enum _rtd_cmc_system_reset_interrupt_flag 89 { 90 kRTDCMC_InSystemProgrammingAccessPortResetDAPResetInterruptFlag = 91 CMC_SRIF_ISP_AP_MASK, /*!< DAP Reset interrupt flag. */ 92 kRTDCMC_LowPowerAcknowledgeTimeoutResetFlag = 93 CMC_SRIF_LPACK_MASK, /*!< Low Power Acknowledge Timeout Reset interrupt flag. */ 94 kRTDCMC_Watchdog0ResetInterruptFlag = CMC_SRIF_WDOG0_MASK, /*!< Watchdog 0 Reset interrupt flag. */ 95 kRTDCMC_SoftwareResetInterruptFlag = CMC_SRIF_SW_MASK, /*!< Software Reset interrupt flag. */ 96 kRTDCMC_LockupResetInterruptFlag = CMC_SRIF_LOCKUP_MASK, /*!< Lock up Reset interrupt flag. */ 97 kRTDCMC_AppDomainMuSystemResetInterruptFlag = CMC_SRIF_AD_MU_MASK, /*!< Application Domain MU System Reset 98 interrupt flag. */ 99 kRTDCMC_WatchdogSResetInterruptFlag = CMC_SRIF_WDOG_S_RTD_MASK, /*!< Watchdog S Reset interrupt flag. */ 100 kRTDCMC_WatchdogHifi4ResetInterruptFlag = CMC_SRIF_WDOG_HIFI4_MASK, /*!< Watchdog Hifi4 Reset interrupt flag. */ 101 kRTDCMC_WatchdogFunsionResetInterruptFlag = CMC_SRIF_WDOG_FUSION_MASK, /*!< Watchdog Fusion Reset interrupt flag. */ 102 }; 103 104 /*! 105 * @brief Power switch domain out of reset interrupt flags enumeration. 106 */ 107 enum _rtd_cmc_power_switch_domain_out_of_reset_interrupt_flag 108 { 109 kRTDCMC_FusionPSDomainOutOfResetInterruptFlag = CMC_RTD_PSDORF_FUSION_MASK, /*!< Fusion power switch domain out of 110 reset interrupt flag. */ 111 kRTDCMC_FusionAlwaysOnPSDomainOutOfResetInterruptFlag = CMC_RTD_PSDORF_FUSION_AO_MASK, /*!< Fusion always on power 112 switch domain out of reset 113 interrupt flag. */ 114 }; 115 116 /*! 117 * @brief System reset sources enumeration. 118 */ 119 enum _rtd_cmc_system_reset_sources 120 { 121 kRTDCMC_WakeUpReset = 122 CMC_SRS_WAKEUP_MASK, /*!< The reset caused by a wakeup from Power Down or Deep Power Down mode. */ 123 kRTDCMC_PORReset = CMC_SRS_POR_MASK, /*!< The reset caused by power on reset detection logic. */ 124 kRTDCMC_HLVDReset = CMC_SRS_HLVD_MASK, /*!< The reset caused by a High or Low Voltage Detect. */ 125 kRTDCMC_WarmReset = CMC_SRS_WARM_MASK, /*!< The last reset source is a warm reset source. */ 126 kRTDCMC_FatalReset = CMC_SRS_FATAL_MASK, /*!< The last reset source is a fatal reset source. */ 127 kRTDCMC_PinReset = CMC_SRS_PIN_MASK, /*!< The reset caused by the RESET_b pin. */ 128 kRTDCMC_ISP_APReset = CMC_SRS_ISP_AP_MASK, /*!< The reset caused by a reset request from 129 in-system programming access port. */ 130 kRTDCMC_ResetTimeout = CMC_SRS_RSTACK_MASK, /*!< The reset caused by a timeout or other error condition in the 131 system reset generation. */ 132 kRTDCMC_LowPowerAcknowledgeTimeoutReset = 133 CMC_SRS_LPACK_MASK, /*!< The reset caused by a timeout in low power mode entry logic. */ 134 kRTDCMC_RtdCgcLocReset = CMC_SRS_RTD_CGC_LOC_MASK, /*!< The reset caused by real time domain clock generation and 135 control loss-of-clock reset. */ 136 kRTDCMC_Watchdog0Reset = CMC_SRS_WDOG0_MASK, /*!< The reset caused by a WatchDog 0 timeout. */ 137 kRTDCMC_SoftwareReset = CMC_SRS_SW_MASK, /*!< The reset caused by a software reset request. */ 138 kRTDCMC_LockUpReset = CMC_SRS_LOCKUP_MASK, /*!< The reset caused by the ARM core indication of a LOCKUP event. */ 139 kRTDCMC_AdMuReset = CMC_SRS_AD_MU_MASK, /*!< The reset caused by application domain MU system. */ 140 kRTDCMC_RtdCgcLosReset = CMC_SRS_RTD_CGC_LOS_MASK, /*!< The reset caused by RTD clock generation 141 and control loss of sync. */ 142 kRTDCMC_LpavCgcLosReset = CMC_SRS_LPAV_CGC_LOS_MASK, /*!< The reset caused by LPAV clock generation 143 and control loss of sync. */ 144 kRTDCMC_uPowerReset = CMC_SRS_UPOWER_MASK, /*!< The reset caused by uPOWER WDOG System. */ 145 kRTDCMC_VbatReset = CMC_SRS_VBAT_MASK, /*!< The reset caused by VBAT system reset. */ 146 kRTDCMC_WatchdogSReset = CMC_SRS_WDOG_S_RTD_MASK, /*!< The reset caused by a WatchDog_S RTD timeout. */ 147 kRTDCMC_WatchdogHifi4Reset = CMC_SRS_WDOG_HIFI4_MASK, /*!< The reset caused from the WDOG_HIFI4 timeout. */ 148 kRTDCMC_WatchdogFusionReset = CMC_SRS_WDOG_FUSION_MASK, /*!< The reset caused from the WDOG_FUSION timeout. */ 149 kRTDCMC_JTAGSystemReset = CMC_SRS_JTAG_MASK, /*!< The reset caused by a JTAG system reset request. */ 150 kRTDCMC_SentinelLifeCycleReset = CMC_SRS_SLB_MASK, /*!< The reset caused by sentinel detecting 151 an unexpected lifecycle coding. */ 152 kRTDCMC_SentinelReset = CMC_SRS_SRR_MASK, /*!< The reset caused by sentinel reset request. */ 153 kRTDCMC_SentinelSystemFailReset = CMC_SRS_SSF_MASK, /*!< The reset caused by a sentinel system fail condition. */ 154 }; 155 156 /*! 157 * @brief Indicate the core clock was gated. 158 */ 159 typedef enum _rtd_cmc_core_clock_gate_status 160 { 161 kRTDCMC_CoreClockNotGated = 0U, /*!< Core clock not gated. */ 162 kRTDCMC_CoreClockGated = 1U /*!< Core clock was gated due to low power mode entry. */ 163 } cmc_core_clock_gate_status_t; 164 165 /*! 166 * @brief CMC clock mode enumeration. 167 */ 168 typedef enum _rtd_cmc_clock_mode 169 { 170 kRTDCMC_GateNoneClock = 0x00U, /*!< No clock gating. */ 171 kRTDCMC_GateCoreClock = 0x01U, /*!< Gate Core clock. */ 172 kRTDCMC_GateCorePlatformClock = 0x03U, /*!< Gate Core clock and platform clock. */ 173 kRTDCMC_GateAllSystemClocks = 174 0x07U, /*!< Gate all System clocks, without getting core entering into low power mode. */ 175 } cmc_clock_mode_t; 176 177 /*! 178 * @brief CMC power mode enumeration. 179 */ 180 typedef enum _rtd_cmc_low_power_mode 181 { 182 kRTDCMC_ActiveMode = 0x0U, /*!< Select Active mode. */ 183 kRTDCMC_SleepMode = 0x1U, /*!< Select Sleep mode when a core executes WFI or WFE instruction. */ 184 kRTDCMC_DeepSleepMode = 0x3U, /*!< Select Deep Sleep mode when a core executes WFI or WFE instruction. */ 185 kRTDCMC_PowerDownMode = 0x7U, /*!< Select Power Down mode when a core executes WFI or WFE instruction. */ 186 kRTDCMC_DeepPowerDown = 0xFU, /*!< Select Deep Power Down mode when a core executes WFI or WFE instruction. */ 187 kRTDCMC_HoldMode = 0x1FU, /*!< Select Hold mode */ 188 } cmc_low_power_mode_t; 189 190 typedef enum _rtd_cmc_power_switch_domain_name 191 { 192 kRTDCMC_FusionAlwaysOnPowerSwitchDomain = 0x1U, /*!< Fusion always on power switch domain. */ 193 kRTDCMC_FusionPowerSwitchDomain = 0x2U, /*!< Fusion power switch domain. */ 194 kRTDCMC_RealtimePowerDomain = 0x4U, /*!< Realtime power switch domain */ 195 } rtd_cmc_power_switch_domain_name_t; 196 197 /******************************************************************************* 198 * API 199 ******************************************************************************/ 200 #if defined(__cplusplus) 201 } 202 #endif /* __cplusplus */ 203 204 /*! 205 * @name CLOCK Mode Configurations 206 * @{ 207 */ 208 209 /*! 210 * @brief Sets clock mode. 211 * 212 * This function configs the amount of clock gating when the core asserts 213 * Sleeping due to WFI, WFE or SLEEPONEXIT. 214 * 215 * @param base CMC peripheral base address. 216 * @param mode System clock mode. 217 */ 218 void RTDCMC_SetClockMode(CMC_Type *base, cmc_clock_mode_t mode); 219 220 /*! 221 * @brief Locks the clock mode setting. 222 * 223 * After invoking this function, any clock mode setting will be blocked. 224 * 225 * @param base CMC peripheral base address. 226 */ 227 static inline void RTDCMC_LockClockModeSetting(CMC_Type *base) 228 { 229 base->CKCTRL |= CMC_CKCTRL_LOCK_MASK; 230 } 231 232 /*! @} */ 233 234 /*! 235 * @name Gets/Clears the Clock Mode, the wake up source, the Reset source 236 * @{ 237 */ 238 239 /*! 240 * @brief Gets the core clock gated status. 241 * 242 * This function get the status to indicate whether the core clock is gated. 243 * The core clock gated status can be cleared by software. 244 * 245 * @param base CMC peripheral base address. 246 * @return The status to indicate whether the core clock is gated. 247 */ 248 static inline cmc_core_clock_gate_status_t RTDCMC_GetCoreClockGatedStatus(CMC_Type *base) 249 { 250 return (cmc_core_clock_gate_status_t)(uint32_t)((base->CKSTAT & CMC_CKSTAT_VALID_MASK) >> CMC_CKSTAT_VALID_SHIFT); 251 } 252 253 /*! 254 * @brief Clears the core clock gated status. 255 * 256 * This function clear clock status flag by software. 257 * 258 * @param base CMC peripheral base address. 259 */ 260 static inline void RTDCMC_ClearCoreClockGatedStatus(CMC_Type *base) 261 { 262 base->CKSTAT |= CMC_CKSTAT_VALID_MASK; 263 } 264 265 /*! 266 * @brief Gets the Wakeup Source. 267 * 268 * This function gets the Wakeup sources from the previous low power mode entry. 269 * 270 * @param base CMC peripheral base address. 271 * @return The Wakeup sources from the previous low power mode entry. See @ref _rtd_cmc_wakeup_sources for details. 272 */ 273 static inline uint8_t RTDCMC_GetWakeupSource(CMC_Type *base) 274 { 275 return (uint8_t)((base->CKSTAT & CMC_CKSTAT_WAKEUP_MASK) >> CMC_CKSTAT_WAKEUP_SHIFT); 276 } 277 278 /*! 279 * @brief Gets the Clock mode. 280 * 281 * This function gets the clock mode of the previous low power mode entry. 282 * 283 * @param base CMC peripheral base address. 284 * @return The Low Power status. 285 */ 286 static inline cmc_clock_mode_t RTDCMC_GetClockMode(CMC_Type *base) 287 { 288 return (cmc_clock_mode_t)(uint32_t)((base->CKSTAT & CMC_CKSTAT_CKMODE_MASK) >> CMC_CKSTAT_CKMODE_SHIFT); 289 } 290 291 /*! 292 * @brief Gets the System reset status. 293 * 294 * This function returns the system reset status. Those status 295 * updates on every MAIN Warm Reset to indicate the type/source 296 * of the most recent reset. 297 * 298 * @param base CMC peripheral base address. 299 * @return The most recent system reset status. See @ref _rtd_cmc_system_reset_sources for details. 300 */ 301 static inline uint32_t RTDCMC_GetSystemResetStatus(CMC_Type *base) 302 { 303 return base->SRS; 304 } 305 306 /*! 307 * @brief Gets the sticky system reset status since the last WAKE Cold Reset. 308 * 309 * This function gets all source of system reset that have generated a 310 * system reset since the last WAKE Cold Reset, and that have not been 311 * cleared by software. 312 * 313 * @param base CMC peripheral base address. 314 * @return System reset status that have not been cleared by software. See @ref _rtd_cmc_system_reset_sources for 315 * details. 316 */ 317 static inline uint32_t RTDCMC_GetStickySystemResetStatus(CMC_Type *base) 318 { 319 return base->SSRS; 320 } 321 322 /*! 323 * @brief Clears the sticky system reset status flags. 324 * 325 * @param base CMC peripheral base address. 326 * @param mask Bitmap of the sticky system reset status to be cleared. 327 */ 328 static inline void RTDCMC_ClearStickySystemResetStatus(CMC_Type *base, uint32_t mask) 329 { 330 base->SSRS = mask; 331 } 332 333 /*! @} */ 334 335 /*! 336 * @name Power Mode Configuration 337 * @{ 338 */ 339 340 /*! 341 * @brief Configures all power mode protection settings. 342 * 343 * This function configures the power mode protection settings for 344 * supported power modes. This should be done before set the lowPower mode 345 * for each power doamin. 346 * 347 * The allowed lowpower modes are passed as bit map. For example, to allow 348 * Sleep and DeepSleep, use CMC_SetPowerModeProtection(CMC_base, kRTDCMC_AllowSleepMode|kRTDCMC_AllowDeepSleepMode). 349 * To allow all low power modes, use CMC_SetPowerModeProtection(CMC_base, kRTDCMC_AllowAllLowPowerModes). 350 * 351 * @param base CMC peripheral base address. 352 * @param allowedModes Bitmaps of the allowed power modes. See @ref _rtd_cmc_power_mode_protection for details. 353 */ 354 void RTDCMC_SetPowerModeProtection(CMC_Type *base, uint8_t allowedModes); 355 356 /*! 357 * @brief Locks the power mode protection. 358 * 359 * This function locks the power mode protection. After invoking this function, 360 * any power mode protection setting will be ignored. 361 * 362 * @param base CMC peripheral base address. 363 */ 364 static inline void RTDCMC_LockPowerModeProtectionSetting(CMC_Type *base) 365 { 366 base->RTD_PMPROT |= CMC_RTD_PMPROT_AS_MASK | CMC_RTD_PMPROT_ADS_MASK | CMC_RTD_PMPROT_APD_MASK | 367 CMC_RTD_PMPROT_ADPD_MASK | CMC_RTD_PMPROT_AHLD_MASK; 368 } 369 370 /*! 371 * @brief Enter into the selected low power mode, please make sure the selected power mode has been enabled in the 372 * protection level. 373 * 374 * @param base CMC peripheral base address. 375 * @param lowPowerMode The desired lowPower mode. See @ref cmc_low_power_mode_t for details. 376 */ 377 void RTDCMC_EnterLowPowerMode(CMC_Type *base, cmc_low_power_mode_t lowPowerMode); 378 379 /*! @} */ 380 381 /*! 382 * @name System Reset Interrupts 383 * @{ 384 */ 385 386 /*! 387 * @brief Enable system reset interrupts. 388 * 389 * This function enables the system reset interrupts. The assertion of 390 * non-fatal warm reset can be delayed for 258 cycles of the 32K_CLK clock 391 * while an enabled interrupt is generated. Then Software can perform a graceful 392 * shutdown or abort the non-fatal warm reset provided the pending reset source is cleared 393 * by resetting the reset source and then clearing the pending flag. 394 * 395 * @param base CMC peripheral base address. 396 * @param mask System reset interrupts. See @ref _rtd_cmc_system_reset_interrupt_enable for details. 397 * 398 */ 399 static inline void RTDCMC_EnableSystemResetInterrupt(CMC_Type *base, uint32_t mask) 400 { 401 base->SRIE |= mask; 402 } 403 404 /*! 405 * @brief Disable system reset interrupts. 406 * 407 * This function disables the system reset interrupts. 408 * 409 * @param base CMC peripheral base address. 410 * @param mask System reset interrupts. See @ref _rtd_cmc_system_reset_interrupt_enable for details. 411 */ 412 static inline void RTDCMC_DisableSystemResetInterrupt(CMC_Type *base, uint32_t mask) 413 { 414 base->SRIE &= (uint32_t)(~mask); 415 } 416 417 /*! 418 * @brief Gets System Reset interrupt flags. 419 * 420 * This function returns the System reset interrupt flags. 421 * 422 * @param base CMC peripheral base address. 423 * @return System reset interrupt flags. See @ref _rtd_cmc_system_reset_interrupt_flag for details. 424 */ 425 static inline uint32_t RTDCMC_GetSystemResetInterruptFlags(CMC_Type *base) 426 { 427 return base->SRIF; 428 } 429 430 /*! 431 * @brief Clears System Reset interrupt flags. 432 * 433 * This function clears system reset interrupt flags. The pending reset source 434 * can be cleared by resetting the source of the reset and then clearing the pending 435 * flags. 436 * 437 * @param base CMC peripheral base address. 438 * @param mask System Reset interrupt flags. See @ref _rtd_cmc_system_reset_interrupt_flag for details. 439 * 440 */ 441 static inline void RTDCMC_ClearSystemResetInterruptFlags(CMC_Type *base, uint32_t mask) 442 { 443 base->SRIF = mask; 444 } 445 446 /*! @} */ 447 448 /*! 449 * @name Power Switch Domain Interrupt 450 * @{ 451 */ 452 453 /*! 454 * @brief Enable power switch domain out of reset interrupts. 455 * 456 * @param base CMC peripheral base address. 457 * @param mask Power switch domain out of reset interrupt mask, 458 * should be the OR'ed value of @ref _rtd_cmc_power_switch_domain_out_of_reset_interrupt_enable. 459 */ 460 static inline void RTDCMC_EnablePowerSwitchDomainOutOfResetInterrupt(CMC_Type *base, uint32_t mask) 461 { 462 base->RTD_PSDORIE |= mask; 463 } 464 465 /*! 466 * @brief Disable power switch domain out of reset interrupts. 467 * 468 * @param base CMC peripheral base address. 469 * @param mask Power switch domain out of reset interrupt mask, 470 * should be the OR'ed value of @ref _rtd_cmc_power_switch_domain_out_of_reset_interrupt_enable. 471 */ 472 473 static inline void RTDCMC_DisablePowerSwitchDomainOutOfResetInterrupt(CMC_Type *base, uint32_t mask) 474 { 475 base->RTD_PSDORIE &= ~mask; 476 } 477 478 /*! 479 * @brief Get power switch domain out of reset interrupt flags. 480 * 481 * @param base CMC peripheral base address. 482 * @return Power switch domain out of reset interrupt flags, 483 * shall be the OR'ed value of @ref _rtd_cmc_power_switch_domain_out_of_reset_interrupt_flag. 484 */ 485 static inline uint32_t RTDCMC_GetPowerSwitchDomainOutOfResetInterruptFlags(CMC_Type *base) 486 { 487 return base->RTD_PSDORF; 488 } 489 490 /*! 491 * @brief Clear power switch domain out of reset interrupt flags. 492 * 493 * @param base CMC peripheral base address. 494 * @param mask The mask of power switch domain out of reset interrupt flags to clear. 495 */ 496 static inline void RTDCMC_ClearPowerSwitchDomainOutOfResetInterruptFlags(CMC_Type *base, uint32_t mask) 497 { 498 base->RTD_PSDORF = mask; 499 } 500 501 /*! @} */ 502 503 /*! 504 * @name Real Time Domain Power Switch Domain Status API 505 * @{ 506 */ 507 508 /*! 509 * @brief Check the status of selected power switch domain. 510 * 511 * @param base CMC peripheral base address. 512 * @param domainName The selected domain name, please refer to @ref rtd_cmc_power_switch_domain_name_t. 513 * @retval True The power switch domain is open. 514 * @retval False The power switch domain is closed. 515 */ 516 static inline bool RTDCMC_CheckRealTimeDomainPowerSwitchDomainStatus(CMC_Type *base, 517 rtd_cmc_power_switch_domain_name_t domainName) 518 { 519 return ((base->RTD_PSDS & (uint32_t)domainName) == 0UL); 520 } 521 522 /*! @} */ 523 524 /*! 525 * @name Boot Configuration 526 * @{ 527 */ 528 529 /*! 530 * @brief Gets the logic state of the BOOT_CONFIGn pin. 531 * 532 * This function returns the logic state of the BOOT_CONFIGn pin 533 * on the last negation of RESET_b pin. 534 * 535 * @param base CMC peripheral base address. 536 * @return The logic state of the BOOT_CONFIGn pin on the last negation of RESET_b pin. 537 */ 538 static inline uint8_t RTDCMC_GetBootConfigPinLogic(CMC_Type *base) 539 { 540 return (uint8_t)((base->MR[0] & CMC_MR_BOOTCFG_MASK) >> CMC_MR_BOOTCFG_SHIFT); 541 } 542 543 /*! 544 * @brief Clears Boot_CONFIG pin state. 545 * 546 * @param base CMC peripheral base address. 547 */ 548 static inline void RTDCMC_ClearBootConfig(CMC_Type *base) 549 { 550 base->MR[0] = CMC_MR_BOOTCFG_MASK; 551 } 552 553 /*! 554 * @brief Set the logic state of the BOOT_CONFIGn pin. 555 * 556 * This function force the logic state of the Boot_Confign pin to assert 557 * on next system reset. 558 * 559 * @param base CMC peripheral base address. 560 * @param assert Assert the corresponding pin or not. 561 * true - Assert corresponding pin on next system reset. 562 * false - No effect. 563 * @param bitsMask The mask of the corresponding bits in the Mode register to assert or not on the next system reset. 564 */ 565 static inline void RTDCMC_ForceBootConfiguration(CMC_Type *base, bool assert, uint32_t bitsMask) 566 { 567 if (assert) 568 { 569 base->FM[0] |= CMC_FM_FORCECFG(bitsMask); 570 } 571 else 572 { 573 base->FM[0] &= ~CMC_FM_FORCECFG(bitsMask); 574 } 575 } 576 577 /*! @} */ 578 579 /*! 580 * @name Non Maskable Pin interrupt 581 * @{ 582 */ 583 584 /*! 585 * @brief Enable/Disable Non maskable Pin interrupt. 586 * 587 * @param base CMC peripheral base address. 588 * @param enable Enable or disable Non maskable pin interrupt. 589 * true - enable Non-maskable pin interrupt. 590 * false - disable Non-maskable pin interupt. 591 */ 592 static inline void RTDCMC_EnableNonMaskablePinInterrupt(CMC_Type *base, bool enable) 593 { 594 if (enable) 595 { 596 base->CORECTL |= CMC_CORECTL_NPIE_MASK; 597 } 598 else 599 { 600 base->CORECTL &= ~CMC_CORECTL_NPIE_MASK; 601 } 602 } 603 604 /*! @} */ 605 606 /*! 607 * @name Debug Configuration 608 * @{ 609 */ 610 611 /*! 612 * @brief Enables/Disables debug Operation when the core sleep. 613 * 614 * This function configs what happens to debug when core sleeps. 615 * 616 * @param base CMC peripheral base address. 617 * @param enable Enable or disable Debug when Core is sleeping. 618 * true - Debug remains enabled when the core is sleeping. 619 * false - Debug is disabled when the core is sleeping. 620 */ 621 static inline void RTDCMC_EnableDebugOperation(CMC_Type *base, bool enable) 622 { 623 if (enable) 624 { 625 base->DBGCTL &= ~CMC_DBGCTL_SOD_MASK; 626 } 627 else 628 { 629 base->DBGCTL |= CMC_DBGCTL_SOD_MASK; 630 } 631 } 632 633 /*! @} */ 634 635 #if defined(__cplusplus) 636 extern "C" { 637 #endif /* __cplusplus */ 638 639 /*! @}*/ 640 #endif /* FSL_RTD_CMC_H_ */ 641
