1 /*
2 * Copyright (c) 2016, Freescale Semiconductor, Inc.
3 * Copyright 2016-2017, 2020-2021 NXP
4 * All rights reserved.
5 *
6 * SPDX-License-Identifier: BSD-3-Clause
7 */
8
9 #ifndef FSL_RGPIO_H_
10 #define FSL_RGPIO_H_
11
12 #include "fsl_common.h"
13
14 /*!
15 * @addtogroup rgpio
16 * @{
17 */
18
19 /*******************************************************************************
20 * Definitions
21 ******************************************************************************/
22
23 /*! @name Driver version */
24 /*@{*/
25 /*! @brief RGPIO driver version 2.1.0. */
26 #define FSL_RGPIO_DRIVER_VERSION (MAKE_VERSION(2, 1, 0))
27 /*@}*/
28
29 /*! @brief RGPIO direction definition */
30 typedef enum _rgpio_pin_direction
31 {
32 kRGPIO_DigitalInput = 0U, /*!< Set current pin as digital input*/
33 kRGPIO_DigitalOutput = 1U, /*!< Set current pin as digital output*/
34 } rgpio_pin_direction_t;
35
36 #if defined(FSL_FEATURE_RGPIO_HAS_ATTRIBUTE_CHECKER) && FSL_FEATURE_RGPIO_HAS_ATTRIBUTE_CHECKER
37 /*! @brief RGPIO checker attribute */
38 typedef enum _rgpio_checker_attribute
39 {
40 kRGPIO_UsernonsecureRWUsersecureRWPrivilegedsecureRW =
41 0x00U, /*!< User nonsecure:Read+Write; User Secure:Read+Write; Privileged Secure:Read+Write */
42 kRGPIO_UsernonsecureRUsersecureRWPrivilegedsecureRW =
43 0x01U, /*!< User nonsecure:Read; User Secure:Read+Write; Privileged Secure:Read+Write */
44 kRGPIO_UsernonsecureNUsersecureRWPrivilegedsecureRW =
45 0x02U, /*!< User nonsecure:None; User Secure:Read+Write; Privileged Secure:Read+Write */
46 kRGPIO_UsernonsecureRUsersecureRPrivilegedsecureRW =
47 0x03U, /*!< User nonsecure:Read; User Secure:Read; Privileged Secure:Read+Write */
48 kRGPIO_UsernonsecureNUsersecureRPrivilegedsecureRW =
49 0x04U, /*!< User nonsecure:None; User Secure:Read; Privileged Secure:Read+Write */
50 kRGPIO_UsernonsecureNUsersecureNPrivilegedsecureRW =
51 0x05U, /*!< User nonsecure:None; User Secure:None; Privileged Secure:Read+Write */
52 kRGPIO_UsernonsecureNUsersecureNPrivilegedsecureR =
53 0x06U, /*!< User nonsecure:None; User Secure:None; Privileged Secure:Read */
54 kRGPIO_UsernonsecureNUsersecureNPrivilegedsecureN =
55 0x07U, /*!< User nonsecure:None; User Secure:None; Privileged Secure:None */
56 kRGPIO_IgnoreAttributeCheck = 0x80U, /*!< Ignores the attribute check */
57 } rgpio_checker_attribute_t;
58 #endif
59
60 #if defined(FSL_FEATURE_RGPIO_HAS_IRQ_CONFIG) && FSL_FEATURE_RGPIO_HAS_IRQ_CONFIG
61 /*! @brief Configures the interrupt generation condition. */
62 typedef enum _rgpio_interrupt_sel
63 {
64 kRGPIO_InterruptOutput0 = 0x0U, /*!< Interrupt/DMA request/trigger output 0. */
65 kRGPIO_InterruptOutput1 = 0x1U, /*!< Interrupt/DMA request/trigger output 1. */
66 kRGPIO_InterruptOutput2 = 0x2U, /*!< Interrupt/DMA request/trigger output 2. */
67 kRGPIO_InterruptOutput3 = 0x3U, /*!< Interrupt/DMA request/trigger output 3. */
68 } rgpio_interrupt_sel_t;
69
70 /*! @brief Configures the interrupt generation condition. */
71 typedef enum _rgpio_interrupt_config
72 {
73 kRGPIO_InterruptOrDMADisabled = 0x0U, /*!< Interrupt/DMA request is disabled. */
74 kRGPIO_DMARisingEdge = 0x1U, /*!< DMA request on rising edge. */
75 kRGPIO_DMAFallingEdge = 0x2U, /*!< DMA request on falling edge. */
76 kRGPIO_DMAEitherEdge = 0x3U, /*!< DMA request on either edge. */
77 kRGPIO_FlagRisingEdge = 0x05U, /*!< Flag sets on rising edge. */
78 kRGPIO_FlagFallingEdge = 0x06U, /*!< Flag sets on falling edge. */
79 kRGPIO_FlagEitherEdge = 0x07U, /*!< Flag sets on either edge. */
80 kRGPIO_InterruptLogicZero = 0x8U, /*!< Interrupt when logic zero. */
81 kRGPIO_InterruptRisingEdge = 0x9U, /*!< Interrupt on rising edge. */
82 kRGPIO_InterruptFallingEdge = 0xAU, /*!< Interrupt on falling edge. */
83 kRGPIO_InterruptEitherEdge = 0xBU, /*!< Interrupt on either edge. */
84 kRGPIO_InterruptLogicOne = 0xCU, /*!< Interrupt when logic one. */
85 kRGPIO_ActiveHighTriggerOutputEnable = 0xDU, /*!< Enable active high-trigger output. */
86 kRGPIO_ActiveLowTriggerOutputEnable = 0xEU, /*!< Enable active low-trigger output. */
87 } rgpio_interrupt_config_t;
88 #endif
89
90 /*!
91 * @brief The RGPIO pin configuration structure.
92 *
93 * Each pin can only be configured as either an output pin or an input pin at a time.
94 * If configured as an input pin, leave the outputConfig unused.
95 * Note that in some use cases, the corresponding port property should be configured in advance
96 * with the PORT_SetPinConfig().
97 */
98 typedef struct _rgpio_pin_config
99 {
100 rgpio_pin_direction_t pinDirection; /*!< RGPIO direction, input or output */
101 /* Output configurations; ignore if configured as an input pin */
102 uint8_t outputLogic; /*!< Set a default output logic, which has no use in input */
103 } rgpio_pin_config_t;
104
105 /*! @} */
106
107 /*******************************************************************************
108 * API
109 ******************************************************************************/
110
111 #if defined(__cplusplus)
112 extern "C" {
113 #endif
114
115 /*!
116 * @addtogroup rgpio_driver
117 * @{
118 */
119
120 /*! @name RGPIO Configuration */
121 /*@{*/
122
123 /*!
124 * @brief Initializes a RGPIO pin used by the board.
125 *
126 * To initialize the RGPIO, define a pin configuration, as either input or output, in the user file.
127 * Then, call the RGPIO_PinInit() function.
128 *
129 * This is an example to define an input pin or an output pin configuration.
130 * @code
131 * Define a digital input pin configuration,
132 * rgpio_pin_config_t config =
133 * {
134 * kRGPIO_DigitalInput,
135 * 0,
136 * }
137 * Define a digital output pin configuration,
138 * rgpio_pin_config_t config =
139 * {
140 * kRGPIO_DigitalOutput,
141 * 0,
142 * }
143 * @endcode
144 *
145 * @param base RGPIO peripheral base pointer (RGPIOA, RGPIOB, RGPIOC, and so on.)
146 * @param pin RGPIO port pin number
147 * @param config RGPIO pin configuration pointer
148 */
149 void RGPIO_PinInit(RGPIO_Type *base, uint32_t pin, const rgpio_pin_config_t *config);
150
151 /*!
152 * @brief Gets the RGPIO instance according to the RGPIO base
153 *
154 * @param base RGPIO peripheral base pointer(PTA, PTB, PTC, etc.)
155 * @retval RGPIO instance
156 */
157 uint32_t RGPIO_GetInstance(RGPIO_Type *base);
158 /*@}*/
159
160 /*! @name RGPIO Output Operations */
161 /*@{*/
162
163 /*!
164 * @brief Sets the output level of the multiple RGPIO pins to the logic 1 or 0.
165 *
166 * @param base RGPIO peripheral base pointer (RGPIOA, RGPIOB, RGPIOC, and so on.)
167 * @param pin RGPIO pin number
168 * @param output RGPIO pin output logic level.
169 * - 0: corresponding pin output low-logic level.
170 * - 1: corresponding pin output high-logic level.
171 */
RGPIO_PinWrite(RGPIO_Type * base,uint32_t pin,uint8_t output)172 static inline void RGPIO_PinWrite(RGPIO_Type *base, uint32_t pin, uint8_t output)
173 {
174 if (output == 0U)
175 {
176 base->PCOR = 1UL << pin;
177 }
178 else
179 {
180 base->PSOR = 1UL << pin;
181 }
182 }
183
184 /*!
185 * @brief Sets the output level of the multiple RGPIO pins to the logic 1 or 0.
186 * @deprecated Do not use this function. It has been superceded by @ref RGPIO_PinWrite.
187 */
RGPIO_WritePinOutput(RGPIO_Type * base,uint32_t pin,uint8_t output)188 static inline void RGPIO_WritePinOutput(RGPIO_Type *base, uint32_t pin, uint8_t output)
189 {
190 RGPIO_PinWrite(base, pin, output);
191 }
192
193 /*!
194 * @brief Sets the output level of the multiple RGPIO pins to the logic 1.
195 *
196 * @param base RGPIO peripheral base pointer (RGPIOA, RGPIOB, RGPIOC, and so on.)
197 * @param mask RGPIO pin number macro
198 */
RGPIO_PortSet(RGPIO_Type * base,uint32_t mask)199 static inline void RGPIO_PortSet(RGPIO_Type *base, uint32_t mask)
200 {
201 base->PSOR = mask;
202 }
203
204 /*!
205 * @brief Sets the output level of the multiple RGPIO pins to the logic 1.
206 * @deprecated Do not use this function. It has been superceded by @ref RGPIO_PortSet.
207 */
RGPIO_SetPinsOutput(RGPIO_Type * base,uint32_t mask)208 static inline void RGPIO_SetPinsOutput(RGPIO_Type *base, uint32_t mask)
209 {
210 RGPIO_PortSet(base, mask);
211 }
212
213 /*!
214 * @brief Sets the output level of the multiple RGPIO pins to the logic 0.
215 *
216 * @param base RGPIO peripheral base pointer (RGPIOA, RGPIOB, RGPIOC, and so on.)
217 * @param mask RGPIO pin number macro
218 */
RGPIO_PortClear(RGPIO_Type * base,uint32_t mask)219 static inline void RGPIO_PortClear(RGPIO_Type *base, uint32_t mask)
220 {
221 base->PCOR = mask;
222 }
223
224 /*!
225 * @brief Sets the output level of the multiple RGPIO pins to the logic 0.
226 * @deprecated Do not use this function. It has been superceded by @ref RGPIO_PortClear.
227 *
228 * @param base RGPIO peripheral base pointer (RGPIOA, RGPIOB, RGPIOC, and so on.)
229 * @param mask RGPIO pin number macro
230 */
RGPIO_ClearPinsOutput(RGPIO_Type * base,uint32_t mask)231 static inline void RGPIO_ClearPinsOutput(RGPIO_Type *base, uint32_t mask)
232 {
233 RGPIO_PortClear(base, mask);
234 }
235
236 /*!
237 * @brief Reverses the current output logic of the multiple RGPIO pins.
238 *
239 * @param base RGPIO peripheral base pointer (RGPIOA, RGPIOB, RGPIOC, and so on.)
240 * @param mask RGPIO pin number macro
241 */
RGPIO_PortToggle(RGPIO_Type * base,uint32_t mask)242 static inline void RGPIO_PortToggle(RGPIO_Type *base, uint32_t mask)
243 {
244 base->PTOR = mask;
245 }
246
247 /*!
248 * @brief Reverses the current output logic of the multiple RGPIO pins.
249 * @deprecated Do not use this function. It has been superceded by @ref RGPIO_PortToggle.
250 */
RGPIO_TogglePinsOutput(RGPIO_Type * base,uint32_t mask)251 static inline void RGPIO_TogglePinsOutput(RGPIO_Type *base, uint32_t mask)
252 {
253 RGPIO_PortToggle(base, mask);
254 }
255 /*@}*/
256
257 /*! @name RGPIO Input Operations */
258 /*@{*/
259
260 /*!
261 * @brief Reads the current input value of the RGPIO port.
262 *
263 * @param base RGPIO peripheral base pointer (RGPIOA, RGPIOB, RGPIOC, and so on.)
264 * @param pin RGPIO pin number
265 * @retval RGPIO port input value
266 * - 0: corresponding pin input low-logic level.
267 * - 1: corresponding pin input high-logic level.
268 */
RGPIO_PinRead(RGPIO_Type * base,uint32_t pin)269 static inline uint32_t RGPIO_PinRead(RGPIO_Type *base, uint32_t pin)
270 {
271 return (((base->PDIR) >> pin) & 0x01U);
272 }
273
274 /*!
275 * @brief Reads the current input value of the RGPIO port.
276 * @deprecated Do not use this function. It has been superceded by @ref RGPIO_PinRead.
277 */
RGPIO_ReadPinInput(RGPIO_Type * base,uint32_t pin)278 static inline uint32_t RGPIO_ReadPinInput(RGPIO_Type *base, uint32_t pin)
279 {
280 return RGPIO_PinRead(base, pin);
281 }
282
283 #if defined(FSL_FEATURE_RGPIO_HAS_PORT_INPUT_DISABLE) && FSL_FEATURE_RGPIO_HAS_PORT_INPUT_DISABLE
284 /*!
285 * @param base RGPIO peripheral base pointer (RGPIOA, RGPIOB, RGPIOC, and so on.)
286 * @param mask RGPIO pin number mask
287 * @param enable RGPIO digital input enable/disable flag.
288 */
RGPIO_EnablePortInput(RGPIO_Type * base,uint32_t mask,bool enable)289 static inline void RGPIO_EnablePortInput(RGPIO_Type *base, uint32_t mask, bool enable)
290 {
291 if (enable)
292 {
293 base->PIDR &= ~mask;
294 }
295 else
296 {
297 base->PIDR |= mask;
298 }
299 }
300 #endif
301
302 /*@}*/
303
304 #if defined(FSL_FEATURE_SOC_PORT_COUNT) && FSL_FEATURE_SOC_PORT_COUNT
305 /*! @name RGPIO Interrupt */
306 /*@{*/
307
308 /*!
309 * @brief Reads the RGPIO port interrupt status flag.
310 *
311 * If a pin is configured to generate the DMA request, the corresponding flag
312 * is cleared automatically at the completion of the requested DMA transfer.
313 * Otherwise, the flag remains set until a logic one is written to that flag.
314 * If configured for a level sensitive interrupt that remains asserted, the flag
315 * is set again immediately.
316 *
317 * @param base RGPIO peripheral base pointer (RGPIOA, RGPIOB, RGPIOC, and so on.)
318 * @retval The current RGPIO port interrupt status flag, for example, 0x00010001 means the
319 * pin 0 and 17 have the interrupt.
320 */
321 uint32_t RGPIO_PortGetInterruptFlags(RGPIO_Type *base);
322
323 /*!
324 * @brief Reads the RGPIO port interrupt status flag.
325 * @deprecated Do not use this function. It has been superceded by @ref RGPIO_PortGetInterruptFlags.
326 */
RGPIO_GetPinsInterruptFlags(RGPIO_Type * base)327 static inline uint32_t RGPIO_GetPinsInterruptFlags(RGPIO_Type *base)
328 {
329 return RGPIO_PortGetInterruptFlags(base);
330 }
331
332 /*!
333 * @brief Clears multiple RGPIO pin interrupt status flags.
334 *
335 * @param base RGPIO peripheral base pointer (RGPIOA, RGPIOB, RGPIOC, and so on.)
336 * @param mask RGPIO pin number macro
337 */
338 void RGPIO_PortClearInterruptFlags(RGPIO_Type *base, uint32_t mask);
339
340 /*!
341 * @brief Clears multiple RGPIO pin interrupt status flags.
342 * @deprecated Do not use this function. It has been superceded by @ref RGPIO_PortClearInterruptFlags.
343 */
RGPIO_ClearPinsInterruptFlags(RGPIO_Type * base,uint32_t mask)344 static inline void RGPIO_ClearPinsInterruptFlags(RGPIO_Type *base, uint32_t mask)
345 {
346 RGPIO_PortClearInterruptFlags(base, mask);
347 }
348 #endif
349 #if defined(FSL_FEATURE_RGPIO_HAS_ATTRIBUTE_CHECKER) && FSL_FEATURE_RGPIO_HAS_ATTRIBUTE_CHECKER
350 /*!
351 * @brief The RGPIO module supports a device-specific number of data ports, organized as 32-bit
352 * words. Each 32-bit data port includes a GACR register, which defines the byte-level
353 * attributes required for a successful access to the RGPIO programming model. The attribute controls for the 4 data
354 * bytes in the GACR follow a standard little endian
355 * data convention.
356 *
357 * @param base RGPIO peripheral base pointer (RGPIOA, RGPIOB, RGPIOC, and so on.)
358 * @param mask RGPIO pin number macro
359 */
360 void RGPIO_CheckAttributeBytes(RGPIO_Type *base, rgpio_checker_attribute_t attribute);
361 #endif
362
363 #if defined(FSL_FEATURE_RGPIO_HAS_IRQ_CONFIG) && FSL_FEATURE_RGPIO_HAS_IRQ_CONFIG
364 /*!
365 * @brief Configures the gpio pin interrupt/DMA request.
366 *
367 * @param base RGPIO peripheral base pointer.
368 * @param pin RGPIO pin number.
369 * @param sel RGPIO pin interrupt selection(0-3).
370 * @param config RGPIO pin interrupt configuration.
371 */
RGPIO_SetPinInterruptConfig(RGPIO_Type * base,uint32_t pin,rgpio_interrupt_sel_t sel,rgpio_interrupt_config_t config)372 static inline void RGPIO_SetPinInterruptConfig(RGPIO_Type *base,
373 uint32_t pin,
374 rgpio_interrupt_sel_t sel,
375 rgpio_interrupt_config_t config)
376 {
377 base->ICR[pin] =
378 (base->ICR[pin] & ~(RGPIO_ICR_IRQC_MASK | RGPIO_ICR_IRQS_MASK)) | RGPIO_ICR_IRQC(config) | RGPIO_ICR_IRQS(sel);
379 }
380
381 /*!
382 * @brief Sets the gpio interrupt configuration in ICR register for multiple pins.
383 *
384 * @param base RGPIO peripheral base pointer (RGPIOA, RGPIOB, RGPIOC, and so on.)
385 * @param mask RGPIO pin number macro.
386 * @param sel RGPIO pin interrupt selection(0-3).
387 * @param config RGPIO pin interrupt configuration.
388 */
_SetMultipleInterruptPinsConfig(RGPIO_Type * base,uint32_t mask,rgpio_interrupt_sel_t sel,rgpio_interrupt_config_t config)389 static inline void _SetMultipleInterruptPinsConfig(RGPIO_Type *base,
390 uint32_t mask,
391 rgpio_interrupt_sel_t sel,
392 rgpio_interrupt_config_t config)
393 {
394 if (0U != (mask & 0xFFFFU))
395 {
396 base->GICLR =
397 ((uint32_t)sel << RGPIO_ICR_IRQS_SHIFT) | ((uint32_t)config << RGPIO_ICR_IRQC_SHIFT) | (mask & 0xFFFFU);
398 }
399 mask = mask >> 16;
400 if (0U != mask)
401 {
402 base->GICHR =
403 ((uint32_t)sel << RGPIO_ICR_IRQS_SHIFT) | ((uint32_t)config << RGPIO_ICR_IRQC_SHIFT) | (mask & 0xFFFFU);
404 }
405 }
406
407 /*!
408 * @brief Reads the whole gpio status flag.
409 *
410 * If a pin is configured to generate the DMA request, the corresponding flag
411 * is cleared automatically at the completion of the requested DMA transfer.
412 * Otherwise, the flag remains set until a logic one is written to that flag.
413 * If configured for a level sensitive interrupt that remains asserted, the flag
414 * is set again immediately.
415 *
416 * @param base RGPIO peripheral base pointer.
417 * @param sel RGPIO pin interrupt selection(0-3).
418 * @return Current gpio interrupt status flags, for example, 0x00010001 means the
419 * pin 0 and 16 have the interrupt.
420 */
RGPIO_GetPinsInterruptFlags(RGPIO_Type * base,rgpio_interrupt_sel_t sel)421 static inline uint32_t RGPIO_GetPinsInterruptFlags(RGPIO_Type *base, rgpio_interrupt_sel_t sel)
422 {
423 return base->ISFR[(uint8_t)sel];
424 }
425
426 /*!
427 * @brief Clears the multiple pin interrupt status flag.
428 *
429 * @param base RGPIO peripheral base pointer.
430 * @param sel RGPIO pin interrupt selection(0-3).
431 * @param mask RGPIO pin number macro.
432 */
RGPIO_ClearPinsInterruptFlags(RGPIO_Type * base,rgpio_interrupt_sel_t sel,uint32_t mask)433 static inline void RGPIO_ClearPinsInterruptFlags(RGPIO_Type *base, rgpio_interrupt_sel_t sel, uint32_t mask)
434 {
435 base->ISFR[(uint8_t)sel] = mask;
436 }
437 #endif
438
439 /*@}*/
440 /*! @} */
441
442 /*!
443 * @addtogroup fgpio_driver
444 * @{
445 */
446
447 /*
448 * Introduces the FGPIO feature.
449 *
450 * The FGPIO registers are aliased to the IOPORT interface.
451 * Accesses via the IOPORT interface occur in parallel with any instruction fetches and
452 * complete in a single cycle. This aliased Fast GPIO memory map is called FGPIO.
453 */
454
455 #if defined(FSL_FEATURE_SOC_FGPIO_COUNT) && FSL_FEATURE_SOC_FGPIO_COUNT
456
457 /*! @name FGPIO Configuration */
458 /*@{*/
459
460 #if defined(FSL_FEATURE_PCC_HAS_FGPIO_CLOCK_GATE_CONTROL) && FSL_FEATURE_PCC_HAS_FGPIO_CLOCK_GATE_CONTROL
461 /*!
462 * @brief Initializes the FGPIO peripheral.
463 *
464 * This function ungates the FGPIO clock.
465 *
466 * @param base FGPIO peripheral base pointer (FGPIOA, FGPIOB, FGPIOC, and so on.)
467 */
468 void FGPIO_PortInit(FGPIO_Type *base);
469
470 /*!
471 * @brief Initializes the FGPIO peripheral.
472 * @deprecated Do not use this function. It has been superceded by @ref FGPIO_PortInit.
473 */
FGPIO_Init(FGPIO_Type * base)474 static inline void FGPIO_Init(FGPIO_Type *base)
475 {
476 FGPIO_PortInit(base);
477 }
478 #endif
479 /*!
480 * @brief Initializes a FGPIO pin used by the board.
481 *
482 * To initialize the FGPIO driver, define a pin configuration, as either input or output, in the user file.
483 * Then, call the FGPIO_PinInit() function.
484 *
485 * This is an example to define an input pin or an output pin configuration:
486 * @code
487 * Define a digital input pin configuration,
488 * rgpio_pin_config_t config =
489 * {
490 * kRGPIO_DigitalInput,
491 * 0,
492 * }
493 * Define a digital output pin configuration,
494 * rgpio_pin_config_t config =
495 * {
496 * kRGPIO_DigitalOutput,
497 * 0,
498 * }
499 * @endcode
500 *
501 * @param base FGPIO peripheral base pointer (FGPIOA, FGPIOB, FGPIOC, and so on.)
502 * @param pin FGPIO port pin number
503 * @param config FGPIO pin configuration pointer
504 */
505 void FGPIO_PinInit(FGPIO_Type *base, uint32_t pin, const rgpio_pin_config_t *config);
506
507 /*!
508 * @brief Gets the FGPIO instance according to the RGPIO base
509 *
510 * @param base FGPIO peripheral base pointer(PTA, PTB, PTC, etc.)
511 * @retval FGPIO instance
512 */
513 uint32_t FGPIO_GetInstance(FGPIO_Type *base);
514 /*@}*/
515
516 /*! @name FGPIO Output Operations */
517 /*@{*/
518
519 /*!
520 * @brief Sets the output level of the multiple FGPIO pins to the logic 1 or 0.
521 *
522 * @param base FGPIO peripheral base pointer (FGPIOA, FGPIOB, FGPIOC, and so on.)
523 * @param pin FGPIO pin number
524 * @param output FGPIOpin output logic level.
525 * - 0: corresponding pin output low-logic level.
526 * - 1: corresponding pin output high-logic level.
527 */
FGPIO_PinWrite(FGPIO_Type * base,uint32_t pin,uint8_t output)528 static inline void FGPIO_PinWrite(FGPIO_Type *base, uint32_t pin, uint8_t output)
529 {
530 if (output == 0U)
531 {
532 base->PCOR = 1UL << pin;
533 }
534 else
535 {
536 base->PSOR = 1UL << pin;
537 }
538 }
539
540 /*!
541 * @brief Sets the output level of the multiple FGPIO pins to the logic 1 or 0.
542 * @deprecated Do not use this function. It has been superceded by @ref FGPIO_PinWrite.
543 */
FGPIO_WritePinOutput(FGPIO_Type * base,uint32_t pin,uint8_t output)544 static inline void FGPIO_WritePinOutput(FGPIO_Type *base, uint32_t pin, uint8_t output)
545 {
546 FGPIO_PinWrite(base, pin, output);
547 }
548
549 /*!
550 * @brief Sets the output level of the multiple FGPIO pins to the logic 1.
551 *
552 * @param base FGPIO peripheral base pointer (FGPIOA, FGPIOB, FGPIOC, and so on.)
553 * @param mask FGPIO pin number macro
554 */
FGPIO_PortSet(FGPIO_Type * base,uint32_t mask)555 static inline void FGPIO_PortSet(FGPIO_Type *base, uint32_t mask)
556 {
557 base->PSOR = mask;
558 }
559
560 /*!
561 * @brief Sets the output level of the multiple FGPIO pins to the logic 1.
562 * @deprecated Do not use this function. It has been superceded by @ref FGPIO_PortSet.
563 */
FGPIO_SetPinsOutput(FGPIO_Type * base,uint32_t mask)564 static inline void FGPIO_SetPinsOutput(FGPIO_Type *base, uint32_t mask)
565 {
566 FGPIO_PortSet(base, mask);
567 }
568
569 /*!
570 * @brief Sets the output level of the multiple FGPIO pins to the logic 0.
571 *
572 * @param base FGPIO peripheral base pointer (FGPIOA, FGPIOB, FGPIOC, and so on.)
573 * @param mask FGPIO pin number macro
574 */
FGPIO_PortClear(FGPIO_Type * base,uint32_t mask)575 static inline void FGPIO_PortClear(FGPIO_Type *base, uint32_t mask)
576 {
577 base->PCOR = mask;
578 }
579
580 /*!
581 * @brief Sets the output level of the multiple FGPIO pins to the logic 0.
582 * @deprecated Do not use this function. It has been superceded by @ref FGPIO_PortClear.
583 */
FGPIO_ClearPinsOutput(FGPIO_Type * base,uint32_t mask)584 static inline void FGPIO_ClearPinsOutput(FGPIO_Type *base, uint32_t mask)
585 {
586 FGPIO_PortClear(base, mask);
587 }
588
589 /*!
590 * @brief Reverses the current output logic of the multiple FGPIO pins.
591 *
592 * @param base FGPIO peripheral base pointer (FGPIOA, FGPIOB, FGPIOC, and so on.)
593 * @param mask FGPIO pin number macro
594 */
FGPIO_PortToggle(FGPIO_Type * base,uint32_t mask)595 static inline void FGPIO_PortToggle(FGPIO_Type *base, uint32_t mask)
596 {
597 base->PTOR = mask;
598 }
599
600 /*!
601 * @brief Reverses the current output logic of the multiple FGPIO pins.
602 * @deprecated Do not use this function. It has been superceded by @ref FGPIO_PortToggle.
603 */
FGPIO_TogglePinsOutput(FGPIO_Type * base,uint32_t mask)604 static inline void FGPIO_TogglePinsOutput(FGPIO_Type *base, uint32_t mask)
605 {
606 FGPIO_PortToggle(base, mask);
607 }
608 /*@}*/
609
610 /*! @name FGPIO Input Operations */
611 /*@{*/
612
613 /*!
614 * @brief Reads the current input value of the FGPIO port.
615 *
616 * @param base FGPIO peripheral base pointer (FGPIOA, FGPIOB, FGPIOC, and so on.)
617 * @param pin FGPIO pin number
618 * @retval FGPIO port input value
619 * - 0: corresponding pin input low-logic level.
620 * - 1: corresponding pin input high-logic level.
621 */
FGPIO_PinRead(FGPIO_Type * base,uint32_t pin)622 static inline uint32_t FGPIO_PinRead(FGPIO_Type *base, uint32_t pin)
623 {
624 return (((base->PDIR) >> pin) & 0x01U);
625 }
626
627 /*!
628 * @brief Reads the current input value of the FGPIO port.
629 * @deprecated Do not use this function. It has been superceded by @ref FGPIO_PinRead
630 */
FGPIO_ReadPinInput(FGPIO_Type * base,uint32_t pin)631 static inline uint32_t FGPIO_ReadPinInput(FGPIO_Type *base, uint32_t pin)
632 {
633 return FGPIO_PinRead(base, pin);
634 }
635 /*@}*/
636
637 #if defined(FSL_FEATURE_SOC_PORT_COUNT) && FSL_FEATURE_SOC_PORT_COUNT
638 /*! @name FGPIO Interrupt */
639 /*@{*/
640
641 /*!
642 * @brief Reads the FGPIO port interrupt status flag.
643 *
644 * If a pin is configured to generate the DMA request, the corresponding flag
645 * is cleared automatically at the completion of the requested DMA transfer.
646 * Otherwise, the flag remains set until a logic one is written to that flag.
647 * If configured for a level-sensitive interrupt that remains asserted, the flag
648 * is set again immediately.
649 *
650 * @param base FGPIO peripheral base pointer (FGPIOA, FGPIOB, FGPIOC, and so on.)
651 * @retval The current FGPIO port interrupt status flags, for example, 0x00010001 means the
652 * pin 0 and 17 have the interrupt.
653 */
654 uint32_t FGPIO_PortGetInterruptFlags(FGPIO_Type *base);
655
656 /*!
657 * @brief Reads the FGPIO port interrupt status flag.
658 * @deprecated Do not use this function. It has been superceded by @ref FGPIO_PortGetInterruptFlags.
659 */
FGPIO_GetPinsInterruptFlags(FGPIO_Type * base)660 static inline uint32_t FGPIO_GetPinsInterruptFlags(FGPIO_Type *base)
661 {
662 return FGPIO_PortGetInterruptFlags(base);
663 }
664
665 /*!
666 * @brief Clears the multiple FGPIO pin interrupt status flag.
667 *
668 * @param base FGPIO peripheral base pointer (FGPIOA, FGPIOB, FGPIOC, and so on.)
669 * @param mask FGPIO pin number macro
670 */
671 void FGPIO_PortClearInterruptFlags(FGPIO_Type *base, uint32_t mask);
672
673 /*!
674 * @brief Clears the multiple FGPIO pin interrupt status flag.
675 * @deprecated Do not use this function. It has been superceded by @ref FGPIO_PortClearInterruptFlags.
676 */
FGPIO_ClearPinsInterruptFlags(FGPIO_Type * base,uint32_t mask)677 static inline void FGPIO_ClearPinsInterruptFlags(FGPIO_Type *base, uint32_t mask)
678 {
679 FGPIO_PortClearInterruptFlags(base, mask);
680 }
681 #endif
682 #if defined(FSL_FEATURE_RGPIO_HAS_ATTRIBUTE_CHECKER) && FSL_FEATURE_RGPIO_HAS_ATTRIBUTE_CHECKER
683 /*!
684 * @brief The FGPIO module supports a device-specific number of data ports, organized as 32-bit
685 * words. Each 32-bit data port includes a GACR register, which defines the byte-level
686 * attributes required for a successful access to the RGPIO programming model. The attribute controls for the 4 data
687 * bytes in the GACR follow a standard little endian
688 * data convention.
689 *
690 * @param base FGPIO peripheral base pointer (FGPIOA, FGPIOB, FGPIOC, and so on.)
691 * @param mask FGPIO pin number macro
692 */
693 void FGPIO_CheckAttributeBytes(FGPIO_Type *base, rgpio_checker_attribute_t attribute);
694 #endif
695
696 /*@}*/
697
698 #endif /* FSL_FEATURE_SOC_FGPIO_COUNT */
699
700 #if defined(__cplusplus)
701 }
702 #endif
703
704 /*!
705 * @}
706 */
707
708 #endif /* FSL_RGPIO_H_*/
709
