1 /*
2 * Copyright (c) 2016, Freescale Semiconductor, Inc.
3 * Copyright 2016-2023 NXP
4 * All rights reserved.
5 *
6 * SPDX-License-Identifier: BSD-3-Clause
7 */
8 #ifndef FSL_LPADC_H_
9 #define FSL_LPADC_H_
10
11 #include "fsl_common.h"
12
13 /*!
14 * @addtogroup lpadc
15 * @{
16 */
17
18 /*! @file */
19
20 /*******************************************************************************
21 * Definitions
22 ******************************************************************************/
23
24 /*! @name Driver version */
25 /*! @{ */
26 /*! @brief LPADC driver version 2.8.4. */
27 #define FSL_LPADC_DRIVER_VERSION (MAKE_VERSION(2, 8, 4))
28 /*! @} */
29
30 #if (defined(FSL_FEATURE_LPADC_OFSTRIM_COUNT) && (FSL_FEATURE_LPADC_OFSTRIM_COUNT == 1))
31 #define ADC_OFSTRIM_OFSTRIM_MAX (ADC_OFSTRIM_OFSTRIM_MASK >> ADC_OFSTRIM_OFSTRIM_SHIFT)
32 #define ADC_OFSTRIM_OFSTRIM_SIGN ((ADC_OFSTRIM_OFSTRIM_MAX + 1U) >> 1U)
33
34 #elif (defined(FSL_FEATURE_LPADC_OFSTRIM_COUNT) && (FSL_FEATURE_LPADC_OFSTRIM_COUNT == 2))
35 #define ADC_OFSTRIM_OFSTRIM_A_MAX (ADC_OFSTRIM_OFSTRIM_A_MASK >> ADC_OFSTRIM_OFSTRIM_A_SHIFT)
36 #define ADC_OFSTRIM_OFSTRIM_B_MAX (ADC_OFSTRIM_OFSTRIM_B_MASK >> ADC_OFSTRIM_OFSTRIM_B_SHIFT)
37 #define ADC_OFSTRIM_OFSTRIM_A_SIGN ((ADC_OFSTRIM_OFSTRIM_A_MAX + 1U) >> 1U)
38 #define ADC_OFSTRIM_OFSTRIM_B_SIGN ((ADC_OFSTRIM_OFSTRIM_B_MAX + 1U) >> 1U)
39 #endif /* defined(FSL_FEATURE_LPADC_OFSTRIM_COUNT) */
40
41 /*!
42 * @brief Define the MACRO function to get command status from status value.
43 *
44 * The statusVal is the return value from LPADC_GetStatusFlags().
45 */
46 #define LPADC_GET_ACTIVE_COMMAND_STATUS(statusVal) ((statusVal & ADC_STAT_CMDACT_MASK) >> ADC_STAT_CMDACT_SHIFT)
47
48 /*!
49 * @brief Define the MACRO function to get trigger status from status value.
50 *
51 * The statusVal is the return value from LPADC_GetStatusFlags().
52 */
53 #define LPADC_GET_ACTIVE_TRIGGER_STATUE(statusVal) ((statusVal & ADC_STAT_TRGACT_MASK) >> ADC_STAT_TRGACT_SHIFT)
54
55 /* Map macros to the unified name. */
56 #if !defined(ADC_STAT_FOF0_MASK)
57 #ifdef ADC_STAT_FOF_MASK
58 #define ADC_STAT_FOF0_MASK ADC_STAT_FOF_MASK
59 #else
60 #error "ADC_STAT_FOF0_MASK not defined"
61 #endif /* ifdef(ADC_STAT_FOF_MASK) */
62 #endif /* !defined(ADC_STAT_FOF0_MASK) */
63
64 #if !defined(ADC_STAT_RDY0_MASK)
65 #ifdef ADC_STAT_RDY_MASK
66 #define ADC_STAT_RDY0_MASK ADC_STAT_RDY_MASK
67 #else
68 #error "ADC_STAT_RDY0_MASK not defined"
69 #endif /* ifdef ADC_STAT_RDY_MASK */
70 #endif /* !defined(ADC_STAT_RDY0_MASK) */
71
72 #if !defined(ADC_IE_FOFIE0_MASK)
73 #ifdef ADC_IE_FOFIE_MASK
74 #define ADC_IE_FOFIE0_MASK ADC_IE_FOFIE_MASK
75 #else
76 #error "ADC_IE_FOFIE0_MASK not defined"
77 #endif /* ifdef ADC_IE_FOFIE_MASK */
78 #endif /* !defined(ADC_IE_FOFIE0_MASK) */
79
80 #if !defined(ADC_IE_FWMIE0_MASK)
81 #ifdef ADC_IE_FWMIE_MASK
82 #define ADC_IE_FWMIE0_MASK ADC_IE_FWMIE_MASK
83 #else
84 #error "ADC_IE_FWMIE0_MASK not defined"
85 #endif /* ifdef ADC_IE_FWMIE_MASK */
86 #endif /* !defined(ADC_IE_FWMIE0_MASK) */
87
88 /*!
89 * @brief Define hardware flags of the module.
90 */
91 enum _lpadc_status_flags
92 {
93 kLPADC_ResultFIFO0OverflowFlag = ADC_STAT_FOF0_MASK, /*!< Indicates that more data has been written to the Result
94 FIFO 0 than it can hold. */
95 kLPADC_ResultFIFO0ReadyFlag = ADC_STAT_RDY0_MASK, /*!< Indicates when the number of valid datawords in the result
96 FIFO 0 is greater than the setting watermark level. */
97
98 #if (defined(FSL_FEATURE_LPADC_FIFO_COUNT) && (FSL_FEATURE_LPADC_FIFO_COUNT == 2U))
99 kLPADC_ResultFIFO1OverflowFlag = ADC_STAT_FOF1_MASK, /*!< Indicates that more data has been written to the Result
100 FIFO 1 than it can hold. */
101 kLPADC_ResultFIFO1ReadyFlag = ADC_STAT_RDY1_MASK, /*!< Indicates when the number of valid datawords in the result
102 FIFO 1 is greater than the setting watermark level. */
103 #endif /* (defined(FSL_FEATURE_LPADC_FIFO_COUNT) && (FSL_FEATURE_LPADC_FIFO_COUNT == 2U)) */
104
105 #if (defined(FSL_FEATURE_LPADC_HAS_STAT_TEXC_INT) && (FSL_FEATURE_LPADC_HAS_STAT_TEXC_INT == 1U))
106 kLPADC_TriggerExceptionFlag = ADC_STAT_TEXC_INT_MASK, /*!< Indicates that a trigger exception event has occurred. */
107 #endif /* (defined(FSL_FEATURE_LPADC_HAS_STAT_TEXC_INT) && (FSL_FEATURE_LPADC_HAS_STAT_TEXC_INT == 1U)) */
108
109 #if (defined(FSL_FEATURE_LPADC_HAS_STAT_TCOMP_INT) && (FSL_FEATURE_LPADC_HAS_STAT_TCOMP_INT == 1U))
110 kLPADC_TriggerCompletionFlag = ADC_STAT_TCOMP_INT_MASK, /*!< Indicates that a trigger completion event has occurred.
111 */
112 #endif /* (defined(FSL_FEATURE_LPADC_HAS_STAT_TCOMP_INT) && (FSL_FEATURE_LPADC_HAS_STAT_TCOMP_INT == 1U)) */
113
114 #if (defined(FSL_FEATURE_LPADC_HAS_STAT_CAL_RDY) && (FSL_FEATURE_LPADC_HAS_STAT_CAL_RDY == 1U))
115 kLPADC_CalibrationReadyFlag = ADC_STAT_CAL_RDY_MASK, /*!< Indicates that the calibration process is done. */
116 #endif /* (defined(FSL_FEATURE_LPADC_HAS_STAT_CAL_RDY) && (FSL_FEATURE_LPADC_HAS_STAT_CAL_RDY == 1U)) */
117
118 #if (defined(FSL_FEATURE_LPADC_HAS_STAT_ADC_ACTIVE) && (FSL_FEATURE_LPADC_HAS_STAT_ADC_ACTIVE == 1U))
119 kLPADC_ActiveFlag = ADC_STAT_ADC_ACTIVE_MASK, /*!< Indicates that the ADC is in active state. */
120 #endif /* (defined(FSL_FEATURE_LPADC_HAS_STAT_ADC_ACTIVE) && (FSL_FEATURE_LPADC_HAS_STAT_ADC_ACTIVE == 1U)) */
121
122 kLPADC_ResultFIFOOverflowFlag = kLPADC_ResultFIFO0OverflowFlag, /*!< To compilitable with old version, do not
123 recommend using this, please use @ref
124 kLPADC_ResultFIFO0OverflowFlag as instead. */
125
126 kLPADC_ResultFIFOReadyFlag = kLPADC_ResultFIFO0ReadyFlag, /*!< To compilitable with old version, do not
127 recommend using this, please use @ref
128 kLPADC_ResultFIFO0ReadyFlag as instead. */
129 };
130
131 /*!
132 * @brief Define interrupt switchers of the module.
133 *
134 * Note: LPADC of different chips supports different number of trigger sources,
135 * please check the Reference Manual for details.
136 */
137 enum _lpadc_interrupt_enable
138 {
139 kLPADC_ResultFIFO0OverflowInterruptEnable = ADC_IE_FOFIE0_MASK, /*!< Configures ADC to generate overflow interrupt
140 requests when FOF0 flag is asserted. */
141 kLPADC_FIFO0WatermarkInterruptEnable = ADC_IE_FWMIE0_MASK, /*!< Configures ADC to generate watermark interrupt
142 requests when RDY0 flag is asserted. */
143 kLPADC_ResultFIFOOverflowInterruptEnable = kLPADC_ResultFIFO0OverflowInterruptEnable, /*!< To compilitable with old
144 version, do not recommend using this,
145 please use
146 #kLPADC_ResultFIFO0OverflowInterruptEnable
147 as instead. */
148 kLPADC_FIFOWatermarkInterruptEnable = kLPADC_FIFO0WatermarkInterruptEnable, /*!< To compilitable with old version,
149 do not recommend using this, please
150 use
151 #kLPADC_FIFO0WatermarkInterruptEnable
152 as instead. */
153
154 #if (defined(FSL_FEATURE_LPADC_FIFO_COUNT) && (FSL_FEATURE_LPADC_FIFO_COUNT == 2U))
155 kLPADC_ResultFIFO1OverflowInterruptEnable = ADC_IE_FOFIE1_MASK, /*!< Configures ADC to generate overflow interrupt
156 requests when FOF1 flag is asserted. */
157 kLPADC_FIFO1WatermarkInterruptEnable = ADC_IE_FWMIE1_MASK, /*!< Configures ADC to generate watermark interrupt
158 requests when RDY1 flag is asserted. */
159 #endif /* (defined(FSL_FEATURE_LPADC_FIFO_COUNT) && (FSL_FEATURE_LPADC_FIFO_COUNT == 2U)) */
160
161 #if (defined(FSL_FEATURE_LPADC_HAS_IE_TEXC_IE) && (FSL_FEATURE_LPADC_HAS_IE_TEXC_IE == 1U))
162 kLPADC_TriggerExceptionInterruptEnable = ADC_IE_TEXC_IE_MASK, /*!< Configures ADC to generate trigger exception
163 interrupt. */
164 #endif /* (defined(FSL_FEATURE_LPADC_HAS_IE_TEXC_IE) && (FSL_FEATURE_LPADC_HAS_IE_TEXC_IE == 1U)) */
165
166 #if (defined(FSL_FEATURE_LPADC_HAS_IE_TCOMP_IE) && (FSL_FEATURE_LPADC_HAS_IE_TCOMP_IE == 1U))
167 kLPADC_Trigger0CompletionInterruptEnable = ADC_IE_TCOMP_IE(1UL << 0UL), /*!< Configures ADC to generate interrupt
168 when trigger 0 completion. */
169 kLPADC_Trigger1CompletionInterruptEnable = ADC_IE_TCOMP_IE(1UL << 1UL), /*!< Configures ADC to generate interrupt
170 when trigger 1 completion. */
171 kLPADC_Trigger2CompletionInterruptEnable = ADC_IE_TCOMP_IE(1UL << 2UL), /*!< Configures ADC to generate interrupt
172 when trigger 2 completion. */
173 kLPADC_Trigger3CompletionInterruptEnable = ADC_IE_TCOMP_IE(1UL << 3UL), /*!< Configures ADC to generate interrupt
174 when trigger 3 completion. */
175 kLPADC_Trigger4CompletionInterruptEnable = ADC_IE_TCOMP_IE(1UL << 4UL), /*!< Configures ADC to generate interrupt
176 when trigger 4 completion. */
177 kLPADC_Trigger5CompletionInterruptEnable = ADC_IE_TCOMP_IE(1UL << 5UL), /*!< Configures ADC to generate interrupt
178 when trigger 5 completion. */
179 kLPADC_Trigger6CompletionInterruptEnable = ADC_IE_TCOMP_IE(1UL << 6UL), /*!< Configures ADC to generate interrupt
180 when trigger 6 completion. */
181 kLPADC_Trigger7CompletionInterruptEnable = ADC_IE_TCOMP_IE(1UL << 7UL), /*!< Configures ADC to generate interrupt
182 when trigger 7 completion. */
183 kLPADC_Trigger8CompletionInterruptEnable = ADC_IE_TCOMP_IE(1UL << 8UL), /*!< Configures ADC to generate interrupt
184 when trigger 8 completion. */
185 kLPADC_Trigger9CompletionInterruptEnable = ADC_IE_TCOMP_IE(1UL << 9UL), /*!< Configures ADC to generate interrupt
186 when trigger 9 completion. */
187 kLPADC_Trigger10CompletionInterruptEnable = ADC_IE_TCOMP_IE(1UL << 10UL), /*!< Configures ADC to generate interrupt
188 when trigger 10 completion. */
189 kLPADC_Trigger11CompletionInterruptEnable = ADC_IE_TCOMP_IE(1UL << 11UL), /*!< Configures ADC to generate interrupt
190 when trigger 11 completion. */
191 kLPADC_Trigger12CompletionInterruptEnable = ADC_IE_TCOMP_IE(1UL << 12UL), /*!< Configures ADC to generate interrupt
192 when trigger 12 completion. */
193 kLPADC_Trigger13CompletionInterruptEnable = ADC_IE_TCOMP_IE(1UL << 13UL), /*!< Configures ADC to generate interrupt
194 when trigger 13 completion. */
195 kLPADC_Trigger14CompletionInterruptEnable = ADC_IE_TCOMP_IE(1UL << 14UL), /*!< Configures ADC to generate interrupt
196 when trigger 14 completion. */
197 kLPADC_Trigger15CompletionInterruptEnable = ADC_IE_TCOMP_IE(1UL << 15UL), /*!< Configures ADC to generate interrupt
198 when trigger 15 completion. */
199 #endif /* #if (defined(FSL_FEATURE_LPADC_HAS_IE_TCOMP_IE) && (FSL_FEATURE_LPADC_HAS_IE_TCOMP_IE == 1U)) */
200 };
201
202 #if (defined(FSL_FEATURE_LPADC_HAS_TSTAT) && (FSL_FEATURE_LPADC_HAS_TSTAT))
203 /*!
204 * @brief The enumerator of lpadc trigger status flags, including interrupted flags and completed flags.
205 *
206 * Note: LPADC of different chips supports different number of trigger sources,
207 * please check the Reference Manual for details.
208 */
209 enum _lpadc_trigger_status_flags
210 {
211 kLPADC_Trigger0InterruptedFlag = 1UL << 0UL, /*!< Trigger 0 is interrupted by a high priority exception. */
212 kLPADC_Trigger1InterruptedFlag = 1UL << 1UL, /*!< Trigger 1 is interrupted by a high priority exception. */
213 kLPADC_Trigger2InterruptedFlag = 1UL << 2UL, /*!< Trigger 2 is interrupted by a high priority exception. */
214 kLPADC_Trigger3InterruptedFlag = 1UL << 3UL, /*!< Trigger 3 is interrupted by a high priority exception. */
215 kLPADC_Trigger4InterruptedFlag = 1UL << 4UL, /*!< Trigger 4 is interrupted by a high priority exception. */
216 kLPADC_Trigger5InterruptedFlag = 1UL << 5UL, /*!< Trigger 5 is interrupted by a high priority exception. */
217 kLPADC_Trigger6InterruptedFlag = 1UL << 6UL, /*!< Trigger 6 is interrupted by a high priority exception. */
218 kLPADC_Trigger7InterruptedFlag = 1UL << 7UL, /*!< Trigger 7 is interrupted by a high priority exception. */
219 kLPADC_Trigger8InterruptedFlag = 1UL << 8UL, /*!< Trigger 8 is interrupted by a high priority exception. */
220 kLPADC_Trigger9InterruptedFlag = 1UL << 9UL, /*!< Trigger 9 is interrupted by a high priority exception. */
221 kLPADC_Trigger10InterruptedFlag = 1UL << 10UL, /*!< Trigger 10 is interrupted by a high priority exception. */
222 kLPADC_Trigger11InterruptedFlag = 1UL << 11UL, /*!< Trigger 11 is interrupted by a high priority exception. */
223 kLPADC_Trigger12InterruptedFlag = 1UL << 12UL, /*!< Trigger 12 is interrupted by a high priority exception. */
224 kLPADC_Trigger13InterruptedFlag = 1UL << 13UL, /*!< Trigger 13 is interrupted by a high priority exception. */
225 kLPADC_Trigger14InterruptedFlag = 1UL << 14UL, /*!< Trigger 14 is interrupted by a high priority exception. */
226 kLPADC_Trigger15InterruptedFlag = 1UL << 15UL, /*!< Trigger 15 is interrupted by a high priority exception. */
227
228 kLPADC_Trigger0CompletedFlag = 1UL << 16UL, /*!< Trigger 0 is completed and
229 trigger 0 has enabled completion interrupts. */
230 kLPADC_Trigger1CompletedFlag = 1UL << 17UL, /*!< Trigger 1 is completed and
231 trigger 1 has enabled completion interrupts. */
232 kLPADC_Trigger2CompletedFlag = 1UL << 18UL, /*!< Trigger 2 is completed and
233 trigger 2 has enabled completion interrupts. */
234 kLPADC_Trigger3CompletedFlag = 1UL << 19UL, /*!< Trigger 3 is completed and
235 trigger 3 has enabled completion interrupts. */
236 kLPADC_Trigger4CompletedFlag = 1UL << 20UL, /*!< Trigger 4 is completed and
237 trigger 4 has enabled completion interrupts. */
238 kLPADC_Trigger5CompletedFlag = 1UL << 21UL, /*!< Trigger 5 is completed and
239 trigger 5 has enabled completion interrupts. */
240 kLPADC_Trigger6CompletedFlag = 1UL << 22UL, /*!< Trigger 6 is completed and
241 trigger 6 has enabled completion interrupts. */
242 kLPADC_Trigger7CompletedFlag = 1UL << 23UL, /*!< Trigger 7 is completed and
243 trigger 7 has enabled completion interrupts. */
244 kLPADC_Trigger8CompletedFlag = 1UL << 24UL, /*!< Trigger 8 is completed and
245 trigger 8 has enabled completion interrupts. */
246 kLPADC_Trigger9CompletedFlag = 1UL << 25UL, /*!< Trigger 9 is completed and
247 trigger 9 has enabled completion interrupts. */
248 kLPADC_Trigger10CompletedFlag = 1UL << 26UL, /*!< Trigger 10 is completed and
249 trigger 10 has enabled completion interrupts. */
250 kLPADC_Trigger11CompletedFlag = 1UL << 27UL, /*!< Trigger 11 is completed and
251 trigger 11 has enabled completion interrupts. */
252 kLPADC_Trigger12CompletedFlag = 1UL << 28UL, /*!< Trigger 12 is completed and
253 trigger 12 has enabled completion interrupts. */
254 kLPADC_Trigger13CompletedFlag = 1UL << 29UL, /*!< Trigger 13 is completed and
255 trigger 13 has enabled completion interrupts. */
256 kLPADC_Trigger14CompletedFlag = 1UL << 30UL, /*!< Trigger 14 is completed and
257 trigger 14 has enabled completion interrupts. */
258 kLPADC_Trigger15CompletedFlag = 1UL << 31UL, /*!< Trigger 15 is completed and
259 trigger 15 has enabled completion interrupts. */
260 };
261 #endif /* (defined(FSL_FEATURE_LPADC_HAS_TSTAT) && (FSL_FEATURE_LPADC_HAS_TSTAT)) */
262
263 /*!
264 * @brief Define enumeration of sample scale mode.
265 *
266 * The sample scale mode is used to reduce the selected ADC analog channel input voltage level by a factor. The maximum
267 * possible voltage on the ADC channel input should be considered when selecting a scale mode to ensure that the
268 * reducing factor always results voltage level at or below the VREFH reference. This reducing capability allows
269 * conversion of analog inputs higher than VREFH. A-side and B-side channel inputs are both scaled using the scale mode.
270 */
271 typedef enum _lpadc_sample_scale_mode
272 {
273 kLPADC_SamplePartScale = 0U, /*!< Use divided input voltage signal.
274 (For scale select,please refer to the reference manual). */
275 kLPADC_SampleFullScale = 1U, /*!< Full scale (Factor of 1). */
276 } lpadc_sample_scale_mode_t;
277
278 /*!
279 * @brief Define enumeration of channel sample mode.
280 *
281 * The channel sample mode configures the channel with single-end/differential/dual-single-end, side A/B.
282 */
283 typedef enum _lpadc_sample_channel_mode
284 {
285 kLPADC_SampleChannelSingleEndSideA = 0x0U, /*!< Single-end mode, only A-side channel is converted. */
286 #if !(defined(FSL_FEATURE_LPADC_HAS_B_SIDE_CHANNELS) && (FSL_FEATURE_LPADC_HAS_B_SIDE_CHANNELS == 0U))
287 kLPADC_SampleChannelSingleEndSideB = 0x1U, /*!< Single-end mode, only B-side channel is converted. */
288 #if defined(FSL_FEATURE_LPADC_HAS_CMDL_DIFF) && FSL_FEATURE_LPADC_HAS_CMDL_DIFF
289 kLPADC_SampleChannelDiffBothSideAB = 0x2U, /*!< Differential mode, the ADC result is (CHnA-CHnB). */
290 kLPADC_SampleChannelDiffBothSideBA = 0x3U, /*!< Differential mode, the ADC result is (CHnB-CHnA). */
291 #endif /* defined(FSL_FEATURE_LPADC_HAS_CMDL_DIFF) && FSL_FEATURE_LPADC_HAS_CMDL_DIFF */
292 #if defined(FSL_FEATURE_LPADC_HAS_CMDL_CTYPE) && FSL_FEATURE_LPADC_HAS_CMDL_CTYPE
293 kLPADC_SampleChannelDiffBothSide = 0x02U, /*!< Differential mode, the ADC result is (CHnA-CHnB). */
294 kLPADC_SampleChannelDualSingleEndBothSide = 0x03U, /*!< Dual-Single-Ended Mode. Both A side and B side
295 channels are converted independently. */
296 #endif /* defined(FSL_FEATURE_LPADC_HAS_CMDL_CTYPE) && FSL_FEATURE_LPADC_HAS_CMDL_CTYPE */
297 #endif /* !(defined(FSL_FEATURE_LPADC_HAS_B_SIDE_CHANNELS) && (FSL_FEATURE_LPADC_HAS_B_SIDE_CHANNELS == 0U)) */
298 } lpadc_sample_channel_mode_t;
299
300 /*!
301 * @brief Define enumeration of hardware average selection.
302 *
303 * It Selects how many ADC conversions are averaged to create the ADC result. An internal storage buffer is used to
304 * capture temporary results while the averaging iterations are executed.
305 *
306 * @note Some enumerator values are not available on some devices, mainly depends on the size of AVGS field in CMDH
307 * register.
308 */
309 typedef enum _lpadc_hardware_average_mode
310 {
311 kLPADC_HardwareAverageCount1 = 0U, /*!< Single conversion. */
312 kLPADC_HardwareAverageCount2 = 1U, /*!< 2 conversions averaged. */
313 kLPADC_HardwareAverageCount4 = 2U, /*!< 4 conversions averaged. */
314 kLPADC_HardwareAverageCount8 = 3U, /*!< 8 conversions averaged. */
315 kLPADC_HardwareAverageCount16 = 4U, /*!< 16 conversions averaged. */
316 kLPADC_HardwareAverageCount32 = 5U, /*!< 32 conversions averaged. */
317 kLPADC_HardwareAverageCount64 = 6U, /*!< 64 conversions averaged. */
318 kLPADC_HardwareAverageCount128 = 7U, /*!< 128 conversions averaged. */
319 #if (defined(FSL_FEATURE_LPADC_CONVERSIONS_AVERAGED_BITFIELD_WIDTH) && \
320 (FSL_FEATURE_LPADC_CONVERSIONS_AVERAGED_BITFIELD_WIDTH == 4U))
321 kLPADC_HardwareAverageCount256 = 8U, /*!< 256 conversions averaged. */
322 kLPADC_HardwareAverageCount512 = 9U, /*!< 512 conversions averaged. */
323 kLPADC_HardwareAverageCount1024 = 10U, /*!< 1024 conversions averaged. */
324 #endif /* (defined(FSL_FEATURE_LPADC_CONVERSIONS_AVERAGED_BITFIELD_WIDTH) && \
325 (FSL_FEATURE_LPADC_CONVERSIONS_AVERAGED_BITFIELD_WIDTH == 4U))*/
326 } lpadc_hardware_average_mode_t;
327
328 /*!
329 * @brief Define enumeration of sample time selection.
330 *
331 * The shortest sample time maximizes conversion speed for lower impedance inputs. Extending sample time allows higher
332 * impedance inputs to be accurately sampled. Longer sample times can also be used to lower overall power consumption
333 * when command looping and sequencing is configured and high conversion rates are not required.
334 */
335 typedef enum _lpadc_sample_time_mode
336 {
337 kLPADC_SampleTimeADCK3 = 0U, /*!< 3 ADCK cycles total sample time. */
338 kLPADC_SampleTimeADCK5 = 1U, /*!< 5 ADCK cycles total sample time. */
339 kLPADC_SampleTimeADCK7 = 2U, /*!< 7 ADCK cycles total sample time. */
340 kLPADC_SampleTimeADCK11 = 3U, /*!< 11 ADCK cycles total sample time. */
341 kLPADC_SampleTimeADCK19 = 4U, /*!< 19 ADCK cycles total sample time. */
342 kLPADC_SampleTimeADCK35 = 5U, /*!< 35 ADCK cycles total sample time. */
343 kLPADC_SampleTimeADCK67 = 6U, /*!< 69 ADCK cycles total sample time. */
344 kLPADC_SampleTimeADCK131 = 7U, /*!< 131 ADCK cycles total sample time. */
345 } lpadc_sample_time_mode_t;
346
347 /*!
348 * @brief Define enumeration of hardware compare mode.
349 *
350 * After an ADC channel input is sampled and converted and any averaging iterations are performed, this mode setting
351 * guides operation of the automatic compare function to optionally only store when the compare operation is true.
352 * When compare is enabled, the conversion result is compared to the compare values.
353 */
354 typedef enum _lpadc_hardware_compare_mode
355 {
356 kLPADC_HardwareCompareDisabled = 0U, /*!< Compare disabled. */
357 kLPADC_HardwareCompareStoreOnTrue = 2U, /*!< Compare enabled. Store on true. */
358 kLPADC_HardwareCompareRepeatUntilTrue = 3U, /*!< Compare enabled. Repeat channel acquisition until true. */
359 } lpadc_hardware_compare_mode_t;
360
361 #if defined(FSL_FEATURE_LPADC_HAS_CMDL_MODE) && FSL_FEATURE_LPADC_HAS_CMDL_MODE
362 /*!
363 * @brief Define enumeration of conversion resolution mode.
364 *
365 * Configure the resolution bit in specific conversion type. For detailed resolution accuracy, see to
366 * #lpadc_sample_channel_mode_t
367 */
368 typedef enum _lpadc_conversion_resolution_mode
369 {
370 kLPADC_ConversionResolutionStandard = 0U, /*!< Standard resolution. Single-ended 12-bit conversion, Differential
371 13-bit conversion with 2's complement output. */
372 kLPADC_ConversionResolutionHigh = 1U, /*!< High resolution. Single-ended 16-bit conversion; Differential 16-bit
373 conversion with 2's complement output. */
374 } lpadc_conversion_resolution_mode_t;
375 #endif /* defined(FSL_FEATURE_LPADC_HAS_CMDL_MODE) && FSL_FEATURE_LPADC_HAS_CMDL_MODE */
376
377 #if defined(FSL_FEATURE_LPADC_HAS_CTRL_CAL_AVGS) && FSL_FEATURE_LPADC_HAS_CTRL_CAL_AVGS
378 /*!
379 * @brief Define enumeration of conversion averages mode.
380 *
381 * Configure the converion average number for auto-calibration.
382 * @note Some enumerator values are not available on some devices, mainly depends on the size of CAL_AVGS field in CTRL
383 * register.
384 */
385 typedef enum _lpadc_conversion_average_mode
386 {
387 kLPADC_ConversionAverage1 = 0U, /*!< Single conversion. */
388 kLPADC_ConversionAverage2 = 1U, /*!< 2 conversions averaged. */
389 kLPADC_ConversionAverage4 = 2U, /*!< 4 conversions averaged. */
390 kLPADC_ConversionAverage8 = 3U, /*!< 8 conversions averaged. */
391 kLPADC_ConversionAverage16 = 4U, /*!< 16 conversions averaged. */
392 kLPADC_ConversionAverage32 = 5U, /*!< 32 conversions averaged. */
393 kLPADC_ConversionAverage64 = 6U, /*!< 64 conversions averaged. */
394 kLPADC_ConversionAverage128 = 7U, /*!< 128 conversions averaged. */
395 #if (defined(FSL_FEATURE_LPADC_CONVERSIONS_AVERAGED_BITFIELD_WIDTH) && \
396 (FSL_FEATURE_LPADC_CONVERSIONS_AVERAGED_BITFIELD_WIDTH == 4U))
397 kLPADC_ConversionAverage256 = 8U, /*!< 256 conversions averaged. */
398 kLPADC_ConversionAverage512 = 9U, /*!< 512 conversions averaged. */
399 kLPADC_ConversionAverage1024 = 10U, /*!< 1024 conversions averaged. */
400 #endif /* (defined(FSL_FEATURE_LPADC_CONVERSIONS_AVERAGED_BITFIELD_WIDTH) && \
401 (FSL_FEATURE_LPADC_CONVERSIONS_AVERAGED_BITFIELD_WIDTH == 4U))*/
402 } lpadc_conversion_average_mode_t;
403 #endif /* defined(FSL_FEATURE_LPADC_HAS_CTRL_CAL_AVGS) && FSL_FEATURE_LPADC_HAS_CTRL_CAL_AVGS */
404
405 /*!
406 * @brief Define enumeration of reference voltage source.
407 *
408 * For detail information, need to check the SoC's specification.
409 */
410 typedef enum _lpadc_reference_voltage_mode
411 {
412 kLPADC_ReferenceVoltageAlt1 = 0U, /*!< Option 1 setting. */
413 kLPADC_ReferenceVoltageAlt2 = 1U, /*!< Option 2 setting. */
414 kLPADC_ReferenceVoltageAlt3 = 2U, /*!< Option 3 setting. */
415 } lpadc_reference_voltage_source_t;
416
417 /*!
418 * @brief Define enumeration of power configuration.
419 *
420 * Configures the ADC for power and performance. In the highest power setting the highest conversion rates will be
421 * possible. Refer to the device data sheet for power and performance capabilities for each setting.
422 */
423 typedef enum _lpadc_power_level_mode
424 {
425 kLPADC_PowerLevelAlt1 = 0U, /*!< Lowest power setting. */
426 kLPADC_PowerLevelAlt2 = 1U, /*!< Next lowest power setting. */
427 kLPADC_PowerLevelAlt3 = 2U, /*!< ... */
428 kLPADC_PowerLevelAlt4 = 3U, /*!< Highest power setting. */
429 } lpadc_power_level_mode_t;
430
431 #if (defined(FSL_FEATURE_LPADC_HAS_CTRL_CALOFSMODE) && FSL_FEATURE_LPADC_HAS_CTRL_CALOFSMODE)
432 /*!
433 * @brief Define enumeration of offset calibration mode.
434 *
435 */
436 typedef enum _lpadc_offset_calibration_mode
437 {
438 kLPADC_OffsetCalibration12bitMode = 0U, /*!< 12 bit offset calibration mode. */
439 kLPADC_OffsetCalibration16bitMode = 1U, /*!< 16 bit offset calibration mode. */
440 } lpadc_offset_calibration_mode_t;
441 #endif /* FSL_FEATURE_LPADC_HAS_CTRL_CALOFSMODE */
442
443 /*!
444 * @brief Define enumeration of trigger priority policy.
445 *
446 * This selection controls how higher priority triggers are handled.
447 * @note \b kLPADC_TriggerPriorityPreemptSubsequently is not available on some devices, mainly depends on the size of
448 * TPRICTRL field in CFG register.
449 */
450 typedef enum _lpadc_trigger_priority_policy
451 {
452 kLPADC_ConvPreemptImmediatelyNotAutoResumed = 0x0U, /*!< If a higher priority trigger is detected during command
453 processing, the current conversion is aborted and the new
454 command specified by the trigger is started, when higher
455 priority conversion finishes, the preempted conversion is not
456 automatically resumed or restarted. */
457 kLPADC_ConvPreemptSoftlyNotAutoResumed = 0x1U, /*!< If a higher priority trigger is received during command
458 processing, the current conversion is completed (including averaging
459 iterations and compare function if enabled) and stored to the result
460 FIFO before the higher priority trigger/command is initiated, when
461 higher priority conversion finishes, the preempted conversion is not
462 resumed or restarted. */
463
464 #if defined(FSL_FEATURE_LPADC_HAS_CFG_TRES) && FSL_FEATURE_LPADC_HAS_CFG_TRES
465 kLPADC_ConvPreemptImmediatelyAutoRestarted = 0x4U, /*!< If a higher priority trigger is detected during command
466 processing, the current conversion is aborted and the new
467 command specified by the trigger is started, when higher
468 priority conversion finishes, the preempted conversion will
469 automatically be restarted. */
470 kLPADC_ConvPreemptSoftlyAutoRestarted = 0x5U, /*!< If a higher priority trigger is received during command
471 processing, the current conversion is completed (including averaging
472 iterations and compare function if enabled) and stored to the result
473 FIFO before the higher priority trigger/command is initiated, when
474 higher priority conversion finishes, the preempted conversion will
475 automatically be restarted. */
476 #endif /* defined(FSL_FEATURE_LPADC_HAS_CFG_TRES) && FSL_FEATURE_LPADC_HAS_CFG_TRES */
477
478 #if defined(FSL_FEATURE_LPADC_HAS_CFG_TCMDRES) && FSL_FEATURE_LPADC_HAS_CFG_TCMDRES
479 kLPADC_ConvPreemptImmediatelyAutoResumed = 0xCU, /*!< If a higher priority trigger is detected during command
480 processing, the current conversion is aborted and the new
481 command specified by the trigger is started, when higher
482 priority conversion finishes, the preempted conversion will
483 automatically be resumed. */
484 kLPADC_ConvPreemptSoftlyAutoResumed = 0xDU, /*!< If a higher priority trigger is received during command
485 processing, the current conversion is completed (including averaging
486 iterations and compare function if enabled) and stored to the result
487 FIFO before the higher priority trigger/command is initiated, when
488 higher priority conversion finishes, the preempted conversion will
489 be automatically be resumed. */
490 #endif /* defined(FSL_FEATURE_LPADC_HAS_CFG_TCMDRES) && FSL_FEATURE_LPADC_HAS_CFG_TCMDRES */
491
492 kLPADC_TriggerPriorityPreemptImmediately =
493 kLPADC_ConvPreemptImmediatelyNotAutoResumed, /*!< Legacy support is not recommended as it only ensures
494 compatibility with older versions. */
495 kLPADC_TriggerPriorityPreemptSoftly =
496 kLPADC_ConvPreemptSoftlyNotAutoResumed, /*!< Legacy support is not recommended as it only ensures compatibility
497 with older versions. */
498
499 #if (defined(FSL_FEATURE_LPADC_CFG_TPRICTRL_BITFIELD_WIDTH) && (FSL_FEATURE_LPADC_CFG_TPRICTRL_BITFIELD_WIDTH == 2U))
500 kLPADC_ConvPreemptSubsequentlyNotAutoResumed = 0x2U, /*!< If a higher priority trigger is received during command
501 processing, the current command will be completed (averaging,
502 looping, compare) before servicing the higher priority trigger, when
503 higher priority conversion finishes, the preempted conversion will
504 not automatically be restarted or resumed. */
505
506 #if defined(FSL_FEATURE_LPADC_HAS_CFG_TRES) && FSL_FEATURE_LPADC_HAS_CFG_TRES
507 kLPADC_ConvPreemptSubsequentlyAutoRestarted = 0x6U, /*!< If a higher priority trigger is received during command
508 processing, the current command will be completed (averaging,
509 looping, compare) before servicing the higher priority trigger, when
510 higher priority conversion finishes, the preempted conversion will
511 be automatically restarted. */
512 #endif /* defined(FSL_FEATURE_LPADC_HAS_CFG_TRES) && FSL_FEATURE_LPADC_HAS_CFG_TRES */
513
514 #if defined(FSL_FEATURE_LPADC_HAS_CFG_TCMDRES) && FSL_FEATURE_LPADC_HAS_CFG_TCMDRES
515 kLPADC_ConvPreemptSubsequentlyAutoResumed = 0xEU, /*!< If a higher priority trigger is received during command
516 processing, the current command will be completed (averaging,
517 looping, compare) before servicing the higher priority trigger, when
518 higher priority conversion finishes, the preempted conversion will
519 be automatically resumed. */
520 #endif /* defined(FSL_FEATURE_LPADC_HAS_CFG_TCMDRES) && FSL_FEATURE_LPADC_HAS_CFG_TCMDRES */
521
522 kLPADC_TriggerPriorityPreemptSubsequently =
523 kLPADC_ConvPreemptSubsequentlyNotAutoResumed, /*!< Legacy support is not recommended as it only ensures
524 compatibility with older versions. */
525 #endif /* #if (defined(FSL_FEATURE_LPADC_CFG_TPRICTRL_BITFIELD_WIDTH) && \
526 (FSL_FEATURE_LPADC_CFG_TPRICTRL_BITFIELD_WIDTH == 2U)) */
527
528 #if defined(FSL_FEATURE_LPADC_HAS_CFG_HPT_EXDI) && FSL_FEATURE_LPADC_HAS_CFG_HPT_EXDI
529 kLPADC_TriggerPriorityExceptionDisabled = 0x10U, /*!< High priority trigger exception disabled. */
530 #endif /* defined(FSL_FEATURE_LPADC_HAS_CFG_HPT_EXDI) && FSL_FEATURE_LPADC_HAS_CFG_HPT_EXDI */
531 } lpadc_trigger_priority_policy_t;
532
533 #if ((defined(FSL_FEATURE_LPADC_HAS_CTRL_CALHS)) && FSL_FEATURE_LPADC_HAS_CTRL_CALHS)
534 /*!
535 * @brief Define enumeration of tune value.
536 */
537 typedef enum _lpadc_tune_value
538 {
539 kLPADC_TuneValue0 = 0U, /*!< Tune value 0. */
540 kLPADC_TuneValue1 = 1U, /*!< Tune value 1. */
541 kLPADC_TuneValue2 = 2U, /*!< Tune value 2. */
542 kLPADC_TuneValue3 = 3U, /*!< Tune value 3. */
543 } lpadc_tune_value_t;
544 #endif /* ((defined(FSL_FEATURE_LPADC_HAS_CTRL_CALHS)) && FSL_FEATURE_LPADC_HAS_CTRL_CALHS) */
545
546 /*!
547 * @brief LPADC global configuration.
548 *
549 * This structure would used to keep the settings for initialization.
550 */
551 typedef struct
552 {
553 #if defined(FSL_FEATURE_LPADC_HAS_CFG_ADCKEN) && FSL_FEATURE_LPADC_HAS_CFG_ADCKEN
554 bool enableInternalClock; /*!< Enables the internally generated clock source. The clock source is used in clock
555 selection logic at the chip level and is optionally used for the ADC clock source. */
556 #endif /* FSL_FEATURE_LPADC_HAS_CFG_ADCKEN */
557 #if defined(FSL_FEATURE_LPADC_HAS_CFG_VREF1RNG) && FSL_FEATURE_LPADC_HAS_CFG_VREF1RNG
558 bool enableVref1LowVoltage; /*!< If voltage reference option1 input is below 1.8V, it should be "true".
559 If voltage reference option1 input is above 1.8V, it should be "false". */
560 #endif /* FSL_FEATURE_LPADC_HAS_CFG_VREF1RNG */
561 bool enableInDozeMode; /*!< Control system transition to Stop and Wait power modes while ADC is converting. When
562 enabled in Doze mode, immediate entries to Wait or Stop are allowed. When disabled, the
563 ADC will wait for the current averaging iteration/FIFO storage to complete before
564 acknowledging stop or wait mode entry. */
565 #if defined(FSL_FEATURE_LPADC_HAS_CTRL_CAL_AVGS) && FSL_FEATURE_LPADC_HAS_CTRL_CAL_AVGS
566 lpadc_conversion_average_mode_t conversionAverageMode; /*!< Auto-Calibration Averages. */
567 #endif /* FSL_FEATURE_LPADC_HAS_CTRL_CAL_AVGS */
568 bool enableAnalogPreliminary; /*!< ADC analog circuits are pre-enabled and ready to execute conversions without
569 startup delays(at the cost of higher DC current consumption). */
570 uint32_t powerUpDelay; /*!< When the analog circuits are not pre-enabled, the ADC analog circuits are only powered
571 while the ADC is active and there is a counted delay defined by this field after an
572 initial trigger transitions the ADC from its Idle state to allow time for the analog
573 circuits to stabilize. The startup delay count of (powerUpDelay * 4) ADCK cycles must
574 result in a longer delay than the analog startup time. */
575 lpadc_reference_voltage_source_t referenceVoltageSource; /*!< Selects the voltage reference high used for
576 conversions.*/
577
578 #if defined(FSL_FEATURE_LPADC_HAS_CFG_PWRSEL) && (FSL_FEATURE_LPADC_HAS_CFG_PWRSEL == 1U)
579 lpadc_power_level_mode_t powerLevelMode; /*!< Power Configuration Selection. */
580 #endif /* defined(FSL_FEATURE_LPADC_HAS_CFG_PWRSEL) && (FSL_FEATURE_LPADC_HAS_CFG_PWRSEL == 1U) */
581 lpadc_trigger_priority_policy_t triggerPriorityPolicy; /*!< Control how higher priority triggers are handled, see to
582 lpadc_trigger_priority_policy_t. */
583 bool enableConvPause; /*!< Enables the ADC pausing function. When enabled, a programmable delay is inserted during
584 command execution sequencing between LOOP iterations, between commands in a sequence, and
585 between conversions when command is executing in "Compare Until True" configuration. */
586 uint32_t convPauseDelay; /*!< Controls the duration of pausing during command execution sequencing. The pause delay
587 is a count of (convPauseDelay*4) ADCK cycles. Only available when ADC pausing
588 function is enabled. The available value range is in 9-bit. */
589 #if (defined(FSL_FEATURE_LPADC_FIFO_COUNT) && (FSL_FEATURE_LPADC_FIFO_COUNT == 2))
590 /* for FIFO0. */
591 uint32_t FIFO0Watermark; /*!< FIFO0Watermark is a programmable threshold setting. When the number of datawords
592 stored in the ADC Result FIFO0 is greater than the value in this field, the ready flag
593 would be asserted to indicate stored data has reached the programmable threshold. */
594 /* for FIFO1. */
595 uint32_t FIFO1Watermark; /*!< FIFO1Watermark is a programmable threshold setting. When the number of datawords
596 stored in the ADC Result FIFO1 is greater than the value in this field, the ready flag
597 would be asserted to indicate stored data has reached the programmable threshold. */
598 #else
599 /* for FIFO. */
600 uint32_t FIFOWatermark; /*!< FIFOWatermark is a programmable threshold setting. When the number of datawords stored
601 in the ADC Result FIFO is greater than the value in this field, the ready flag would be
602 asserted to indicate stored data has reached the programmable threshold. */
603 #endif /* FSL_FEATURE_LPADC_FIFO_COUNT */
604 #if (defined(FSL_FEATURE_LPADC_HAS_TSTAT) && (FSL_FEATURE_LPADC_HAS_TSTAT))
605
606 #endif /* FSL_FEATURE_LPADC_HAS_TSTAT */
607 } lpadc_config_t;
608
609 /*!
610 * @brief Define structure to keep the configuration for conversion command.
611 */
612 typedef struct
613 {
614 #if defined(FSL_FEATURE_LPADC_HAS_CMDL_CSCALE) && FSL_FEATURE_LPADC_HAS_CMDL_CSCALE
615 lpadc_sample_scale_mode_t sampleScaleMode; /*!< Sample scale mode. */
616 #endif /* FSL_FEATURE_LPADC_HAS_CMDL_CSCALE */
617 #if defined(FSL_FEATURE_LPADC_HAS_CMDL_ALTB_CSCALE) && FSL_FEATURE_LPADC_HAS_CMDL_ALTB_CSCALE
618 lpadc_sample_scale_mode_t channelBScaleMode; /*!< Alternate channe B Scale mode. */
619 #endif /* FSL_FEATURE_LPADC_HAS_CMDL_ALTB_CSCALE */
620 lpadc_sample_channel_mode_t sampleChannelMode; /*!< Channel sample mode. */
621 uint32_t channelNumber; /*!< Channel number, select the channel or channel pair. */
622 #if defined(FSL_FEATURE_LPADC_HAS_CMDL_ALTB_ADCH) && FSL_FEATURE_LPADC_HAS_CMDL_ALTB_ADCH
623 uint32_t channelBNumber; /*!< Alternate Channel B number, select the channel. */
624 #endif
625 uint32_t chainedNextCommandNumber; /*!< Selects the next command to be executed after this command completes.
626 1-15 is available, 0 is to terminate the chain after this command. */
627 bool enableAutoChannelIncrement; /*!< Loop with increment: when disabled, the "loopCount" field selects the number
628 of times the selected channel is converted consecutively; when enabled, the
629 "loopCount" field defines how many consecutive channels are converted as part
630 of the command execution. */
631 uint32_t loopCount; /*!< Selects how many times this command executes before finish and transition to the next
632 command or Idle state. Command executes LOOP+1 times. 0-15 is available. */
633 lpadc_hardware_average_mode_t hardwareAverageMode; /*!< Hardware average selection. */
634 lpadc_sample_time_mode_t sampleTimeMode; /*!< Sample time selection. */
635
636 lpadc_hardware_compare_mode_t hardwareCompareMode; /*!< Hardware compare selection. */
637 uint32_t hardwareCompareValueHigh; /*!< Compare Value High. The available value range is in 16-bit. */
638 uint32_t hardwareCompareValueLow; /*!< Compare Value Low. The available value range is in 16-bit. */
639 #if defined(FSL_FEATURE_LPADC_HAS_CMDL_MODE) && FSL_FEATURE_LPADC_HAS_CMDL_MODE
640 lpadc_conversion_resolution_mode_t conversionResolutionMode; /*!< Conversion resolution mode. */
641 #endif /* FSL_FEATURE_LPADC_HAS_CMDL_MODE */
642 #if defined(FSL_FEATURE_LPADC_HAS_CMDH_WAIT_TRIG) && FSL_FEATURE_LPADC_HAS_CMDH_WAIT_TRIG
643 bool enableWaitTrigger; /*!< Wait for trigger assertion before execution: when disabled, this command will be
644 automatically executed; when enabled, the active trigger must be asserted again before
645 executing this command. */
646 #endif /* FSL_FEATURE_LPADC_HAS_CMDH_WAIT_TRIG */
647 #if defined(FSL_FEATURE_LPADC_HAS_CMDL_ALTBEN) && FSL_FEATURE_LPADC_HAS_CMDL_ALTBEN
648 bool enableChannelB; /*! Enable alternate Channel B */
649 #endif /* FSL_FEATURE_LPADC_HAS_CMDL_ALTBEN */
650 } lpadc_conv_command_config_t;
651
652 /*!
653 * @brief Define structure to keep the configuration for conversion trigger.
654 */
655 typedef struct
656 {
657 uint32_t targetCommandId; /*!< Select the command from command buffer to execute upon detect of the associated
658 trigger event. */
659 uint32_t delayPower; /*!< Select the trigger delay duration to wait at the start of servicing a trigger event.
660 When this field is clear, then no delay is incurred. When this field is set to a non-zero
661 value, the duration for the delay is 2^delayPower ADCK cycles. The available value range
662 is 4-bit. */
663 uint32_t priority; /*!< Sets the priority of the associated trigger source. If two or more triggers have the same
664 priority level setting, the lower order trigger event has the higher priority. The lower
665 value for this field is for the higher priority, the available value range is 1-bit. */
666 #if (defined(FSL_FEATURE_LPADC_FIFO_COUNT) && (FSL_FEATURE_LPADC_FIFO_COUNT == 2))
667 uint8_t channelAFIFOSelect; /* SAR Result Destination For Channel A. */
668 uint8_t channelBFIFOSelect; /* SAR Result Destination For Channel B. */
669 #endif /* FSL_FEATURE_LPADC_FIFO_COUNT */
670 bool enableHardwareTrigger; /*!< Enable hardware trigger source to initiate conversion on the rising edge of the
671 input trigger source or not. THe software trigger is always available. */
672 } lpadc_conv_trigger_config_t;
673
674 /*!
675 * @brief Define the structure to keep the conversion result.
676 */
677 typedef struct
678 {
679 uint32_t commandIdSource; /*!< Indicate the command buffer being executed that generated this result. */
680 uint32_t loopCountIndex; /*!< Indicate the loop count value during command execution that generated this result. */
681 uint32_t triggerIdSource; /*!< Indicate the trigger source that initiated a conversion and generated this result. */
682 uint16_t convValue; /*!< Data result. */
683 } lpadc_conv_result_t;
684
685 #if defined(FSL_FEATURE_LPADC_HAS_CTRL_CALOFS) && FSL_FEATURE_LPADC_HAS_CTRL_CALOFS
686 /*!
687 * @brief A structure of calibration value.
688 */
689 typedef struct _lpadc_calibration_value
690 {
691 /* gain calibration result. */
692 uint16_t gainCalibrationResultA;
693 #if !(defined(FSL_FEATURE_LPADC_HAS_B_SIDE_CHANNELS) && (FSL_FEATURE_LPADC_HAS_B_SIDE_CHANNELS == 0U))
694 uint16_t gainCalibrationResultB;
695 #endif /* !(defined(FSL_FEATURE_LPADC_HAS_B_SIDE_CHANNELS) && (FSL_FEATURE_LPADC_HAS_B_SIDE_CHANNELS == 0U)) */
696 #if (defined(FSL_FEATURE_LPADC_HAS_CTRL_CAL_REQ) && FSL_FEATURE_LPADC_HAS_CTRL_CAL_REQ)
697 /* general calibration value. */
698 uint16_t generalCalibrationValueA[33U];
699 #if !(defined(FSL_FEATURE_LPADC_HAS_B_SIDE_CHANNELS) && (FSL_FEATURE_LPADC_HAS_B_SIDE_CHANNELS == 0U))
700 uint16_t generalCalibrationValueB[33U];
701 #endif /* !(defined(FSL_FEATURE_LPADC_HAS_B_SIDE_CHANNELS) && (FSL_FEATURE_LPADC_HAS_B_SIDE_CHANNELS == 0U)) */
702 #endif /* FSL_FEATURE_LPADC_HAS_CTRL_CAL_REQ */
703 } lpadc_calibration_value_t;
704 #endif /* FSL_FEATURE_LPADC_HAS_CTRL_CALOFS */
705
706 #if defined(__cplusplus)
707 extern "C" {
708 #endif
709
710 /*******************************************************************************
711 * API
712 ******************************************************************************/
713 /*!
714 * @name Initialization & de-initialization.
715 * @{
716 */
717
718 /*!
719 * @brief Initializes the LPADC module.
720 *
721 * @param base LPADC peripheral base address.
722 * @param config Pointer to configuration structure. See "lpadc_config_t".
723 */
724 void LPADC_Init(ADC_Type *base, const lpadc_config_t *config);
725
726 /*!
727 * @brief Gets an available pre-defined settings for initial configuration.
728 *
729 * This function initializes the converter configuration structure with an available settings. The default values are:
730 * @code
731 * config->enableInDozeMode = true;
732 * config->enableAnalogPreliminary = false;
733 * config->powerUpDelay = 0x80;
734 * config->referenceVoltageSource = kLPADC_ReferenceVoltageAlt1;
735 * config->powerLevelMode = kLPADC_PowerLevelAlt1;
736 * config->triggerPriorityPolicy = kLPADC_TriggerPriorityPreemptImmediately;
737 * config->enableConvPause = false;
738 * config->convPauseDelay = 0U;
739 * config->FIFOWatermark = 0U;
740 * @endcode
741 * @param config Pointer to configuration structure.
742 */
743 void LPADC_GetDefaultConfig(lpadc_config_t *config);
744
745 /*!
746 * @brief De-initializes the LPADC module.
747 *
748 * @param base LPADC peripheral base address.
749 */
750 void LPADC_Deinit(ADC_Type *base);
751
752 /*!
753 * @brief Switch on/off the LPADC module.
754 *
755 * @param base LPADC peripheral base address.
756 * @param enable switcher to the module.
757 */
LPADC_Enable(ADC_Type * base,bool enable)758 static inline void LPADC_Enable(ADC_Type *base, bool enable)
759 {
760 if (enable)
761 {
762 base->CTRL |= ADC_CTRL_ADCEN_MASK;
763 }
764 else
765 {
766 base->CTRL &= ~ADC_CTRL_ADCEN_MASK;
767 }
768 }
769
770 #if (defined(FSL_FEATURE_LPADC_FIFO_COUNT) && (FSL_FEATURE_LPADC_FIFO_COUNT == 2))
771 /*!
772 * @brief Do reset the conversion FIFO0.
773 *
774 * @param base LPADC peripheral base address.
775 */
LPADC_DoResetFIFO0(ADC_Type * base)776 static inline void LPADC_DoResetFIFO0(ADC_Type *base)
777 {
778 base->CTRL |= ADC_CTRL_RSTFIFO0_MASK;
779 }
780
781 /*!
782 * @brief Do reset the conversion FIFO1.
783 *
784 * @param base LPADC peripheral base address.
785 */
LPADC_DoResetFIFO1(ADC_Type * base)786 static inline void LPADC_DoResetFIFO1(ADC_Type *base)
787 {
788 base->CTRL |= ADC_CTRL_RSTFIFO1_MASK;
789 }
790 #else
791
792 #if defined(ADC_CTRL_RSTFIFO0_MASK)
793 #define ADC_CTRL_RSTFIFO_MASK ADC_CTRL_RSTFIFO0_MASK
794 #endif /* defined(ADC_CTRL_RSTFIFO0_MASK) */
795 /*!
796 * @brief Do reset the conversion FIFO.
797 *
798 * @param base LPADC peripheral base address.
799 */
LPADC_DoResetFIFO(ADC_Type * base)800 static inline void LPADC_DoResetFIFO(ADC_Type *base)
801 {
802 base->CTRL |= ADC_CTRL_RSTFIFO_MASK;
803 }
804 #endif /* FSL_FEATURE_LPADC_FIFO_COUNT */
805
806 /*!
807 * @brief Do reset the module's configuration.
808 *
809 * Reset all ADC internal logic and registers, except the Control Register (ADCx_CTRL).
810 *
811 * @param base LPADC peripheral base address.
812 */
LPADC_DoResetConfig(ADC_Type * base)813 static inline void LPADC_DoResetConfig(ADC_Type *base)
814 {
815 base->CTRL |= ADC_CTRL_RST_MASK;
816 base->CTRL &= ~ADC_CTRL_RST_MASK;
817 }
818
819 /* @} */
820
821 /*!
822 * @name Status
823 * @{
824 */
825
826 /*!
827 * @brief Get status flags.
828 *
829 * @param base LPADC peripheral base address.
830 * @return status flags' mask. See to #_lpadc_status_flags.
831 */
LPADC_GetStatusFlags(ADC_Type * base)832 static inline uint32_t LPADC_GetStatusFlags(ADC_Type *base)
833 {
834 return base->STAT;
835 }
836
837 /*!
838 * @brief Clear status flags.
839 *
840 * Only the flags can be cleared by writing ADCx_STATUS register would be cleared by this API.
841 *
842 * @param base LPADC peripheral base address.
843 * @param mask Mask value for flags to be cleared. See to #_lpadc_status_flags.
844 */
LPADC_ClearStatusFlags(ADC_Type * base,uint32_t mask)845 static inline void LPADC_ClearStatusFlags(ADC_Type *base, uint32_t mask)
846 {
847 base->STAT = mask;
848 }
849
850 #if (defined(FSL_FEATURE_LPADC_HAS_TSTAT) && FSL_FEATURE_LPADC_HAS_TSTAT)
851 /*!
852 * @brief Get trigger status flags to indicate which trigger sequences have been completed or interrupted by a high
853 * priority trigger exception.
854 *
855 * @param base LPADC peripheral base address.
856 * @return The OR'ed value of @ref _lpadc_trigger_status_flags.
857 */
LPADC_GetTriggerStatusFlags(ADC_Type * base)858 static inline uint32_t LPADC_GetTriggerStatusFlags(ADC_Type *base)
859 {
860 return base->TSTAT;
861 }
862
863 /*!
864 * @brief Clear trigger status flags.
865 *
866 * @param base LPADC peripheral base address.
867 * @param mask The mask of trigger status flags to be cleared, should be the
868 * OR'ed value of @ref _lpadc_trigger_status_flags.
869 */
LPADC_ClearTriggerStatusFlags(ADC_Type * base,uint32_t mask)870 static inline void LPADC_ClearTriggerStatusFlags(ADC_Type *base, uint32_t mask)
871 {
872 /* This assert used to avoid user use doesn't supported trigger sources. */
873 assert(((mask & 0xFFFFU) == (mask & ADC_TSTAT_TEXC_NUM_MASK)) &&
874 ((mask & 0xFFFF0000U) == (mask & ADC_TSTAT_TCOMP_FLAG_MASK)));
875 base->TSTAT = mask;
876 }
877 #endif /* (defined(FSL_FEATURE_LPADC_HAS_TSTAT) && FSL_FEATURE_LPADC_HAS_TSTAT) */
878
879 /* @} */
880
881 /*!
882 * @name Interrupts
883 * @{
884 */
885
886 /*!
887 * @brief Enable interrupts.
888 *
889 * @param base LPADC peripheral base address.
890 * @param mask Mask value for interrupt events. See to #_lpadc_interrupt_enable.
891 */
LPADC_EnableInterrupts(ADC_Type * base,uint32_t mask)892 static inline void LPADC_EnableInterrupts(ADC_Type *base, uint32_t mask)
893 {
894 #if (defined(FSL_FEATURE_LPADC_HAS_IE_TCOMP_IE) && (FSL_FEATURE_LPADC_HAS_IE_TCOMP_IE == 1U))
895 /* This assert used to avoid user use doesn't supported trigger sources. */
896 assert((mask <= 0xFFFFU) || ((mask & 0xFFFF0000U) == (mask & ADC_IE_TCOMP_IE_MASK)));
897 #endif /* #if (defined(FSL_FEATURE_LPADC_HAS_IE_TCOMP_IE) && (FSL_FEATURE_LPADC_HAS_IE_TCOMP_IE == 1U)) */
898 base->IE |= mask;
899 }
900
901 /*!
902 * @brief Disable interrupts.
903 *
904 * @param base LPADC peripheral base address.
905 * @param mask Mask value for interrupt events. See to #_lpadc_interrupt_enable.
906 */
LPADC_DisableInterrupts(ADC_Type * base,uint32_t mask)907 static inline void LPADC_DisableInterrupts(ADC_Type *base, uint32_t mask)
908 {
909 #if (defined(FSL_FEATURE_LPADC_HAS_IE_TCOMP_IE) && (FSL_FEATURE_LPADC_HAS_IE_TCOMP_IE == 1U))
910 /* This assert used to avoid user use doesn't supported trigger sources. */
911 assert((mask <= 0xFFFFU) || ((mask & 0xFFFF0000U) == (mask & ADC_IE_TCOMP_IE_MASK)));
912 #endif /* #if (defined(FSL_FEATURE_LPADC_HAS_IE_TCOMP_IE) && (FSL_FEATURE_LPADC_HAS_IE_TCOMP_IE == 1U)) */
913 base->IE &= ~mask;
914 }
915
916 /*!
917 * @name DMA Control
918 * @{
919 */
920
921 #if (defined(FSL_FEATURE_LPADC_FIFO_COUNT) && (FSL_FEATURE_LPADC_FIFO_COUNT == 2))
922 /*!
923 * @brief Switch on/off the DMA trigger for FIFO0 watermark event.
924 *
925 * @param base LPADC peripheral base address.
926 * @param enable Switcher to the event.
927 */
LPADC_EnableFIFO0WatermarkDMA(ADC_Type * base,bool enable)928 static inline void LPADC_EnableFIFO0WatermarkDMA(ADC_Type *base, bool enable)
929 {
930 if (enable)
931 {
932 base->DE |= ADC_DE_FWMDE0_MASK;
933 }
934 else
935 {
936 base->DE &= ~ADC_DE_FWMDE0_MASK;
937 }
938 }
939
940 /*!
941 * @brief Switch on/off the DMA trigger for FIFO1 watermark event.
942 *
943 * @param base LPADC peripheral base address.
944 * @param enable Switcher to the event.
945 */
LPADC_EnableFIFO1WatermarkDMA(ADC_Type * base,bool enable)946 static inline void LPADC_EnableFIFO1WatermarkDMA(ADC_Type *base, bool enable)
947 {
948 if (enable)
949 {
950 base->DE |= ADC_DE_FWMDE1_MASK;
951 }
952 else
953 {
954 base->DE &= ~ADC_DE_FWMDE1_MASK;
955 }
956 }
957 #else
958 #if defined(ADC_DE_FWMDE0_MASK)
959 #define ADC_DE_FWMDE_MASK ADC_DE_FWMDE0_MASK
960 #endif /* defined(ADC_DE_FWMDE0_MASK) */
961 /*!
962 * @brief Switch on/off the DMA trigger for FIFO watermark event.
963 *
964 * @param base LPADC peripheral base address.
965 * @param enable Switcher to the event.
966 */
LPADC_EnableFIFOWatermarkDMA(ADC_Type * base,bool enable)967 static inline void LPADC_EnableFIFOWatermarkDMA(ADC_Type *base, bool enable)
968 {
969 if (enable)
970 {
971 base->DE |= ADC_DE_FWMDE_MASK;
972 }
973 else
974 {
975 base->DE &= ~ADC_DE_FWMDE_MASK;
976 }
977 }
978 #endif /* (defined(FSL_FEATURE_LPADC_FIFO_COUNT) && (FSL_FEATURE_LPADC_FIFO_COUNT == 2)) */
979 /* @} */
980
981 /*!
982 * @name Trigger and conversion with FIFO.
983 * @{
984 */
985
986 #if (defined(FSL_FEATURE_LPADC_FIFO_COUNT) && (FSL_FEATURE_LPADC_FIFO_COUNT == 2))
987 /*!
988 * @brief Get the count of result kept in conversion FIFOn.
989 *
990 * @param base LPADC peripheral base address.
991 * @param index Result FIFO index.
992 * @return The count of result kept in conversion FIFOn.
993 */
LPADC_GetConvResultCount(ADC_Type * base,uint8_t index)994 static inline uint32_t LPADC_GetConvResultCount(ADC_Type *base, uint8_t index)
995 {
996 return (ADC_FCTRL_FCOUNT_MASK & base->FCTRL[index]) >> ADC_FCTRL_FCOUNT_SHIFT;
997 }
998
999 /*!
1000 * @brief Get the result in conversion FIFOn.
1001 *
1002 * @param base LPADC peripheral base address.
1003 * @param result Pointer to structure variable that keeps the conversion result in conversion FIFOn.
1004 * @param index Result FIFO index.
1005 *
1006 * @return Status whether FIFOn entry is valid.
1007 */
1008 bool LPADC_GetConvResult(ADC_Type *base, lpadc_conv_result_t *result, uint8_t index);
1009
1010 /*!
1011 * @brief Get the result in conversion FIFOn using blocking method.
1012 *
1013 * @param base LPADC peripheral base address.
1014 * @param result Pointer to structure variable that keeps the conversion result in conversion FIFOn.
1015 * @param index Result FIFO index.
1016 */
1017 void LPADC_GetConvResultBlocking(ADC_Type *base, lpadc_conv_result_t *result, uint8_t index);
1018 #else /* (defined(FSL_FEATURE_LPADC_FIFO_COUNT) && (FSL_FEATURE_LPADC_FIFO_COUNT == 1)) */
1019 /*!
1020 * @brief Get the count of result kept in conversion FIFO.
1021 *
1022 * @param base LPADC peripheral base address.
1023 * @return The count of result kept in conversion FIFO.
1024 */
LPADC_GetConvResultCount(ADC_Type * base)1025 static inline uint32_t LPADC_GetConvResultCount(ADC_Type *base)
1026 {
1027 return (ADC_FCTRL_FCOUNT_MASK & base->FCTRL) >> ADC_FCTRL_FCOUNT_SHIFT;
1028 }
1029
1030 /*!
1031 * @brief Get the result in conversion FIFO.
1032 *
1033 * @param base LPADC peripheral base address.
1034 * @param result Pointer to structure variable that keeps the conversion result in conversion FIFO.
1035 *
1036 * @return Status whether FIFO entry is valid.
1037 */
1038 bool LPADC_GetConvResult(ADC_Type *base, lpadc_conv_result_t *result);
1039
1040 /*!
1041 * @brief Get the result in conversion FIFO using blocking method.
1042 *
1043 * @param base LPADC peripheral base address.
1044 * @param result Pointer to structure variable that keeps the conversion result in conversion FIFO.
1045 */
1046 void LPADC_GetConvResultBlocking(ADC_Type *base, lpadc_conv_result_t *result);
1047 #endif /* (defined(FSL_FEATURE_LPADC_FIFO_COUNT) && (FSL_FEATURE_LPADC_FIFO_COUNT == 2)) */
1048
1049 /*!
1050 * @brief Configure the conversion trigger source.
1051 *
1052 * Each programmable trigger can launch the conversion command in command buffer.
1053 *
1054 * @param base LPADC peripheral base address.
1055 * @param triggerId ID for each trigger. Typically, the available value range is from 0.
1056 * @param config Pointer to configuration structure. See to #lpadc_conv_trigger_config_t.
1057 */
1058 void LPADC_SetConvTriggerConfig(ADC_Type *base, uint32_t triggerId, const lpadc_conv_trigger_config_t *config);
1059
1060 /*!
1061 * @brief Gets an available pre-defined settings for trigger's configuration.
1062 *
1063 * This function initializes the trigger's configuration structure with an available settings. The default values are:
1064 * @code
1065 * config->targetCommandId = 0U;
1066 * config->delayPower = 0U;
1067 * config->priority = 0U;
1068 * config->channelAFIFOSelect = 0U;
1069 * config->channelBFIFOSelect = 0U;
1070 * config->enableHardwareTrigger = false;
1071 * @endcode
1072 * @param config Pointer to configuration structure.
1073 */
1074 void LPADC_GetDefaultConvTriggerConfig(lpadc_conv_trigger_config_t *config);
1075
1076 /*!
1077 * @brief Do software trigger to conversion command.
1078 *
1079 * @param base LPADC peripheral base address.
1080 * @param triggerIdMask Mask value for software trigger indexes, which count from zero.
1081 */
LPADC_DoSoftwareTrigger(ADC_Type * base,uint32_t triggerIdMask)1082 static inline void LPADC_DoSoftwareTrigger(ADC_Type *base, uint32_t triggerIdMask)
1083 {
1084 /* Writes to ADCx_SWTRIG register are ignored while ADCx_CTRL[ADCEN] is clear. */
1085 base->SWTRIG = triggerIdMask;
1086 }
1087
1088 #if defined(FSL_FEATURE_LPADC_HAS_TCTRL_CMD_SEL) && FSL_FEATURE_LPADC_HAS_TCTRL_CMD_SEL
1089 /*!
1090 * @brief Enable hardware trigger command selection.
1091 *
1092 * This function will use the hardware trigger command from ADC_ETC.The trigger command is then defined
1093 * by ADC hardware trigger command selection field in ADC_ETC- >TRIGx_CHAINy_z_n[CSEL].
1094 *
1095 * @param base LPADC peripheral base address.
1096 * @param triggerId ID for each trigger. Typically, the available value range is from 0.
1097 * @param enable True to enable or flase to disable.
1098 */
LPADC_EnableHardwareTriggerCommandSelection(ADC_Type * base,uint32_t triggerId,bool enable)1099 static inline void LPADC_EnableHardwareTriggerCommandSelection(ADC_Type *base, uint32_t triggerId, bool enable)
1100 {
1101 if (enable)
1102 {
1103 base->TCTRL[triggerId] |= ADC_TCTRL_CMD_SEL_MASK;
1104 }
1105 else
1106 {
1107 base->TCTRL[triggerId] &= ~ADC_TCTRL_CMD_SEL_MASK;
1108 }
1109 }
1110 #endif /* defined(FSL_FEATURE_LPADC_HAS_TCTRL_CMD_SEL) && FSL_FEATURE_LPADC_HAS_TCTRL_CMD_SEL*/
1111
1112 /*!
1113 * @brief Configure conversion command.
1114
1115 * @note The number of compare value register on different chips is different, that is mean in some chips, some
1116 * command buffers do not have the compare functionality.
1117 *
1118 * @param base LPADC peripheral base address.
1119 * @param commandId ID for command in command buffer. Typically, the available value range is 1 - 15.
1120 * @param config Pointer to configuration structure. See to #lpadc_conv_command_config_t.
1121 */
1122 void LPADC_SetConvCommandConfig(ADC_Type *base, uint32_t commandId, const lpadc_conv_command_config_t *config);
1123
1124 /*!
1125 * @brief Gets an available pre-defined settings for conversion command's configuration.
1126 *
1127 * This function initializes the conversion command's configuration structure with an available settings. The default
1128 * values are:
1129 * @code
1130 * config->sampleScaleMode = kLPADC_SampleFullScale;
1131 * config->channelBScaleMode = kLPADC_SampleFullScale;
1132 * config->sampleChannelMode = kLPADC_SampleChannelSingleEndSideA;
1133 * config->channelNumber = 0U;
1134 * config->channelBNumber = 0U;
1135 * config->chainedNextCommandNumber = 0U;
1136 * config->enableAutoChannelIncrement = false;
1137 * config->loopCount = 0U;
1138 * config->hardwareAverageMode = kLPADC_HardwareAverageCount1;
1139 * config->sampleTimeMode = kLPADC_SampleTimeADCK3;
1140 * config->hardwareCompareMode = kLPADC_HardwareCompareDisabled;
1141 * config->hardwareCompareValueHigh = 0U;
1142 * config->hardwareCompareValueLow = 0U;
1143 * config->conversionResolutionMode = kLPADC_ConversionResolutionStandard;
1144 * config->enableWaitTrigger = false;
1145 * config->enableChannelB = false;
1146 * @endcode
1147 * @param config Pointer to configuration structure.
1148 */
1149 void LPADC_GetDefaultConvCommandConfig(lpadc_conv_command_config_t *config);
1150
1151 #if defined(FSL_FEATURE_LPADC_HAS_CFG_CALOFS) && FSL_FEATURE_LPADC_HAS_CFG_CALOFS
1152 /*!
1153 * @brief Enable the calibration function.
1154 *
1155 * When CALOFS is set, the ADC is configured to perform a calibration function anytime the ADC executes
1156 * a conversion. Any channel selected is ignored and the value returned in the RESFIFO is a signed value
1157 * between -31 and 31. -32 is not a valid and is never a returned value. Software should copy the lower 6-
1158 * bits of the conversion result stored in the RESFIFO after a completed calibration conversion to the
1159 * OFSTRIM field. The OFSTRIM field is used in normal operation for offset correction.
1160 *
1161 * @param base LPADC peripheral base address.
1162 * @param enable switcher to the calibration function.
1163 */
1164 void LPADC_EnableCalibration(ADC_Type *base, bool enable);
1165 #if defined(FSL_FEATURE_LPADC_HAS_OFSTRIM) && FSL_FEATURE_LPADC_HAS_OFSTRIM
1166 /*!
1167 * @brief Set proper offset value to trim ADC.
1168 *
1169 * To minimize the offset during normal operation, software should read the conversion result from
1170 * the RESFIFO calibration operation and write the lower 6 bits to the OFSTRIM register.
1171 *
1172 * @param base LPADC peripheral base address.
1173 * @param value Setting offset value.
1174 */
LPADC_SetOffsetValue(ADC_Type * base,uint32_t value)1175 static inline void LPADC_SetOffsetValue(ADC_Type *base, uint32_t value)
1176 {
1177 base->OFSTRIM = (value & ADC_OFSTRIM_OFSTRIM_MASK) >> ADC_OFSTRIM_OFSTRIM_SHIFT;
1178 }
1179
1180 /*!
1181 * @brief Do auto calibration.
1182 *
1183 * Calibration function should be executed before using converter in application. It used the software trigger and a
1184 * dummy conversion, get the offset and write them into the OFSTRIM register. It called some of functional API
1185 * including: -LPADC_EnableCalibration(...) -LPADC_LPADC_SetOffsetValue(...) -LPADC_SetConvCommandConfig(...)
1186 * -LPADC_SetConvTriggerConfig(...)
1187 *
1188 * @param base LPADC peripheral base address.
1189 */
1190 void LPADC_DoAutoCalibration(ADC_Type *base);
1191 #endif /* defined(FSL_FEATURE_LPADC_HAS_OFSTRIM) && FSL_FEATURE_LPADC_HAS_OFSTRIM */
1192 #endif /* defined(FSL_FEATURE_LPADC_HAS_CFG_CALOFS) && FSL_FEATURE_LPADC_HAS_CFG_CALOFS */
1193
1194 #if defined(FSL_FEATURE_LPADC_HAS_CTRL_CALOFS) && FSL_FEATURE_LPADC_HAS_CTRL_CALOFS
1195 #if defined(FSL_FEATURE_LPADC_HAS_OFSTRIM) && FSL_FEATURE_LPADC_HAS_OFSTRIM
1196 #if defined(FSL_FEATURE_LPADC_OFSTRIM_COUNT) && (FSL_FEATURE_LPADC_OFSTRIM_COUNT == 1U)
1197 /*!
1198 * @brief Set trim value for offset.
1199 *
1200 * @note For 16-bit conversions, each increment is 1/2 LSB resulting in a programmable offset range of -256 LSB to 255.5
1201 * LSB; For 12-bit conversions, each increment is 1/32 LSB resulting in a programmable offset range of -16 LSB to
1202 * 15.96875 LSB.
1203 *
1204 * @param base LPADC peripheral base address.
1205 * @param value Offset trim value, is a 10-bit signed value between -512 and 511.
1206 */
LPADC_SetOffsetValue(ADC_Type * base,int16_t value)1207 static inline void LPADC_SetOffsetValue(ADC_Type *base, int16_t value)
1208 {
1209 base->OFSTRIM = ADC_OFSTRIM_OFSTRIM(value);
1210 }
1211
1212 /*!
1213 * @brief Get trim value of offset.
1214 *
1215 * @param base LPADC peripheral base address.
1216 * @param pValue Pointer to the variable in type of int16_t to store offset value.
1217 */
LPADC_GetOffsetValue(ADC_Type * base,int16_t * pValue)1218 static inline void LPADC_GetOffsetValue(ADC_Type *base, int16_t *pValue)
1219 {
1220 assert(pValue != NULL);
1221
1222 uint16_t ofstrim = (uint16_t)((base->OFSTRIM & (ADC_OFSTRIM_OFSTRIM_MASK)) >> ADC_OFSTRIM_OFSTRIM_SHIFT);
1223
1224 if ((ofstrim & ADC_OFSTRIM_OFSTRIM_SIGN) != 0U)
1225 {
1226 /* If the sign bit is set, then set the other MSB. */
1227 ofstrim |= (uint16_t)(~ADC_OFSTRIM_OFSTRIM_MAX);
1228 }
1229
1230 *pValue = (int16_t)ofstrim;
1231 }
1232 #elif (defined(FSL_FEATURE_LPADC_OFSTRIM_COUNT) && (FSL_FEATURE_LPADC_OFSTRIM_COUNT == 2U))
1233 /*!
1234 * @brief Set proper offset value to trim ADC.
1235 *
1236 * Set the offset trim value for offset calibration manually.
1237 *
1238 * @param base LPADC peripheral base address.
1239 * @param valueA Setting offset value A.
1240 * @param valueB Setting offset value B.
1241 * @note In normal adc sequence, the values are automatically calculated by LPADC_EnableOffsetCalibration.
1242 */
LPADC_SetOffsetValue(ADC_Type * base,int32_t valueA,int32_t valueB)1243 static inline void LPADC_SetOffsetValue(ADC_Type *base, int32_t valueA, int32_t valueB)
1244 {
1245 base->OFSTRIM = ADC_OFSTRIM_OFSTRIM_A(valueA) | ADC_OFSTRIM_OFSTRIM_B(valueB);
1246 }
1247
1248 /*!
1249 * @brief Get trim value of offset.
1250 *
1251 * @param base LPADC peripheral base address.
1252 * @param pValueA Pointer to the variable in type of int32_t to store offset A value.
1253 * @param pValueB Pointer to the variable in type of int32_t to store offset B value.
1254 */
LPADC_GetOffsetValue(ADC_Type * base,int32_t * pValueA,int32_t * pValueB)1255 static inline void LPADC_GetOffsetValue(ADC_Type *base, int32_t *pValueA, int32_t *pValueB)
1256 {
1257 assert(pValueA != NULL);
1258 assert(pValueB != NULL);
1259
1260 uint32_t ofstrimA = (base->OFSTRIM & (ADC_OFSTRIM_OFSTRIM_A_MASK)) >> ADC_OFSTRIM_OFSTRIM_A_SHIFT;
1261 uint32_t ofstrimB = (base->OFSTRIM & (ADC_OFSTRIM_OFSTRIM_B_MASK)) >> ADC_OFSTRIM_OFSTRIM_B_SHIFT;
1262
1263 if ((ofstrimA & ADC_OFSTRIM_OFSTRIM_A_SIGN) != 0U)
1264 {
1265 /* If the sign bit is set, then set the other MSB. */
1266 ofstrimA |= (~ADC_OFSTRIM_OFSTRIM_A_MAX);
1267 }
1268 if ((ofstrimB & ADC_OFSTRIM_OFSTRIM_B_SIGN) != 0U)
1269 {
1270 /* If the sign bit is set, then set the other MSB. */
1271 ofstrimB |= (~ADC_OFSTRIM_OFSTRIM_B_MAX);
1272 }
1273
1274 *pValueA = (int32_t)ofstrimA;
1275 *pValueB = (int32_t)ofstrimB;
1276 }
1277 #endif /* defined(FSL_FEATURE_LPADC_OFSTRIM_COUNT) */
1278 #else /* !(defined(FSL_FEATURE_LPADC_HAS_OFSTRIM) && FSL_FEATURE_LPADC_HAS_OFSTRIM) */
1279 /*!
1280 * @brief Set proper offset value to trim 12 bit ADC conversion.
1281 *
1282 * Set the offset trim value for offset calibration manually.
1283 *
1284 * @param base LPADC peripheral base address.
1285 * @param valueA Setting offset value A.
1286 * @param valueB Setting offset value B.
1287 * @note In normal adc sequence, the values are automatically calculated by LPADC_EnableOffsetCalibration.
1288 */
LPADC_SetOffset12BitValue(ADC_Type * base,uint32_t valueA,uint32_t valueB)1289 static inline void LPADC_SetOffset12BitValue(ADC_Type *base, uint32_t valueA, uint32_t valueB)
1290 {
1291 base->OFSTRIM12 = ADC_OFSTRIM12_OFSTRIM_A(valueA) | ADC_OFSTRIM12_OFSTRIM_A(valueB);
1292 }
1293
1294 /*!
1295 * @brief Set proper offset value to trim 16 bit ADC conversion.
1296 *
1297 * Set the offset trim value for offset calibration manually.
1298 *
1299 * @param base LPADC peripheral base address.
1300 * @param valueA Setting offset value A.
1301 * @param valueB Setting offset value B.
1302 * @note In normal adc sequence, the values are automatically calculated by LPADC_EnableOffsetCalibration.
1303 */
LPADC_SetOffset16BitValue(ADC_Type * base,uint32_t valueA,uint32_t valueB)1304 static inline void LPADC_SetOffset16BitValue(ADC_Type *base, uint32_t valueA, uint32_t valueB)
1305 {
1306 base->OFSTRIM16 = ADC_OFSTRIM16_OFSTRIM_A(valueA) | ADC_OFSTRIM16_OFSTRIM_B(valueB);
1307 }
1308 #endif /* FSL_FEATURE_LPADC_HAS_OFSTRIM */
1309
1310 /*!
1311 * @brief Enable the offset calibration function.
1312 *
1313 * @param base LPADC peripheral base address.
1314 * @param enable switcher to the calibration function.
1315 */
LPADC_EnableOffsetCalibration(ADC_Type * base,bool enable)1316 static inline void LPADC_EnableOffsetCalibration(ADC_Type *base, bool enable)
1317 {
1318 if (enable)
1319 {
1320 base->CTRL |= ADC_CTRL_CALOFS_MASK;
1321 }
1322 else
1323 {
1324 base->CTRL &= ~ADC_CTRL_CALOFS_MASK;
1325 }
1326 }
1327 #if defined(FSL_FEATURE_LPADC_HAS_CTRL_CALOFSMODE) && FSL_FEATURE_LPADC_HAS_CTRL_CALOFSMODE
1328 /*!
1329 * @brief Set offset calibration mode.
1330 *
1331 * @param base LPADC peripheral base address.
1332 * @param mode set offset calibration mode.see to #lpadc_offset_calibration_mode_t .
1333 */
LPADC_SetOffsetCalibrationMode(ADC_Type * base,lpadc_offset_calibration_mode_t mode)1334 static inline void LPADC_SetOffsetCalibrationMode(ADC_Type *base, lpadc_offset_calibration_mode_t mode)
1335 {
1336 base->CTRL = (base->CTRL & ~ADC_CTRL_CALOFSMODE_MASK) | ADC_CTRL_CALOFSMODE(mode);
1337 }
1338
1339 #endif /* defined(FSL_FEATURE_LPADC_HAS_CTRL_CALOFSMODE) && FSL_FEATURE_LPADC_HAS_CTRL_CALOFSMODE */
1340
1341 /*!
1342 * @brief Do offset calibration.
1343 *
1344 * @param base LPADC peripheral base address.
1345 */
1346 void LPADC_DoOffsetCalibration(ADC_Type *base);
1347
1348 #if defined(FSL_FEATURE_LPADC_HAS_CTRL_CAL_REQ) && FSL_FEATURE_LPADC_HAS_CTRL_CAL_REQ
1349 /*!
1350 * @brief Do auto calibration.
1351 *
1352 * @param base LPADC peripheral base address.
1353 */
1354 void LPADC_DoAutoCalibration(ADC_Type *base);
1355
1356 /*!
1357 * @brief Prepare auto calibration, LPADC_FinishAutoCalibration has to be called before using the LPADC.
1358 * LPADC_DoAutoCalibration has been split in two API to avoid to be stuck too long in the function.
1359 *
1360 * @param base LPADC peripheral base address.
1361 */
1362 void LPADC_PrepareAutoCalibration(ADC_Type *base);
1363
1364 /*!
1365 * @brief Finish auto calibration start with LPADC_PrepareAutoCalibration.
1366 *
1367 * @param base LPADC peripheral base address.
1368 */
1369 void LPADC_FinishAutoCalibration(ADC_Type *base);
1370
1371 #endif /* defined(FSL_FEATURE_LPADC_HAS_CTRL_CAL_REQ) && FSL_FEATURE_LPADC_HAS_CTRL_CAL_REQ */
1372
1373 /*!
1374 * @brief Get calibration value into the memory which is defined by invoker.
1375 *
1376 * @note Please note the ADC will be disabled temporary.
1377 * @note This function should be used after finish calibration.
1378 *
1379 * @param base LPADC peripheral base address.
1380 * @param ptrCalibrationValue Pointer to @ref lpadc_calibration_value_t structure, this memory block should be always
1381 * powered on even in low power modes.
1382 */
1383 void LPADC_GetCalibrationValue(ADC_Type *base, lpadc_calibration_value_t *ptrCalibrationValue);
1384
1385 /*!
1386 * @brief Set calibration value into ADC calibration registers.
1387 *
1388 * @note Please note the ADC will be disabled temporary.
1389 *
1390 * @param base LPADC peripheral base address.
1391 * @param ptrCalibrationValue Pointer to @ref lpadc_calibration_value_t structure which contains ADC's calibration
1392 * value.
1393 */
1394 void LPADC_SetCalibrationValue(ADC_Type *base, const lpadc_calibration_value_t *ptrCalibrationValue);
1395
1396 #endif /* defined(FSL_FEATURE_LPADC_HAS_CTRL_CALOFS) && FSL_FEATURE_LPADC_HAS_CTRL_CALOFS */
1397
1398 #if ((defined(FSL_FEATURE_LPADC_HAS_CTRL_CALHS)) && FSL_FEATURE_LPADC_HAS_CTRL_CALHS)
1399 /*!
1400 * @brief Request high speed mode trim calculation.
1401 *
1402 * @param base LPADC peripheral base address.
1403 */
LPADC_RequestHighSpeedModeTrim(ADC_Type * base)1404 static inline void LPADC_RequestHighSpeedModeTrim(ADC_Type *base)
1405 {
1406 base->CTRL |= ADC_CTRL_CALHS_MASK;
1407 }
1408
1409 /*!
1410 * @brief Get high speed mode trim value, the result is a 5-bit signed value between -16 and 15.
1411 *
1412 * @note The high speed mode trim value is used to minimize offset for high speed conversion.
1413 *
1414 * @param base LPADC peripheral base address.
1415 * @return The calculated high speed mode trim value.
1416 */
LPADC_GetHighSpeedTrimValue(ADC_Type * base)1417 static inline int8_t LPADC_GetHighSpeedTrimValue(ADC_Type *base)
1418 {
1419 return (int8_t)(base->HSTRIM);
1420 }
1421
1422 /*!
1423 * @brief Set high speed mode trim value.
1424 *
1425 * @note If is possible to set the trim value manually, but it is recommended to use the LPADC_RequestHighSpeedModeTrim.
1426 *
1427 * @param base LPADC peripheral base address.
1428 * @param trimValue The trim value to be set.
1429 */
LPADC_SetHighSpeedTrimValue(ADC_Type * base,int8_t trimValue)1430 static inline void LPADC_SetHighSpeedTrimValue(ADC_Type *base, int8_t trimValue)
1431 {
1432 base->HSTRIM = ADC_HSTRIM_HSTRIM(trimValue);
1433 }
1434
1435 /*!
1436 * @brief Enable/disable high speed conversion mode, if enabled conversions complete 2 or 3 ADCK cycles sooner compared
1437 * to conversion cycle counts when high speed mode is disabled.
1438 *
1439 * @param base LPADC peripheral base address.
1440 * @param enable Used to enable/disable high speed conversion mode:
1441 * - \b true Enable high speed conversion mode;
1442 * - \b false Disable high speed conversion mode.
1443 */
LPADC_EnableHighSpeedConversionMode(ADC_Type * base,bool enable)1444 static inline void LPADC_EnableHighSpeedConversionMode(ADC_Type *base, bool enable)
1445 {
1446 if (enable)
1447 {
1448 base->CFG2 |= ADC_CFG2_HS_MASK;
1449 }
1450 else
1451 {
1452 base->CFG2 &= ~ADC_CFG2_HS_MASK;
1453 }
1454 }
1455
1456 /*!
1457 * @brief Enable/disable an additional ADCK cycle to conversion.
1458 *
1459 * @param base LPADC peripheral base address.
1460 * @param enable Used to enable/disable an additional ADCK cycle to conversion:
1461 * - \b true Enable an additional ADCK cycle to conversion;
1462 * - \b false Disable an additional ADCK cycle to conversion.
1463 */
LPADC_EnableExtraCycle(ADC_Type * base,bool enable)1464 static inline void LPADC_EnableExtraCycle(ADC_Type *base, bool enable)
1465 {
1466 if (enable)
1467 {
1468 base->CFG2 |= ADC_CFG2_HSEXTRA_MASK;
1469 }
1470 else
1471 {
1472 base->CFG2 &= ~ADC_CFG2_HSEXTRA_MASK;
1473 }
1474 }
1475
1476 /*!
1477 * @brief Set tune value which provides some variability in how many cycles are needed to complete a conversion.
1478 *
1479 * @param base LPADC peripheral base address.
1480 * @param tuneValue The tune value to be set, please refer to @ref lpadc_tune_value_t.
1481 */
LPADC_SetTuneValue(ADC_Type * base,lpadc_tune_value_t tuneValue)1482 static inline void LPADC_SetTuneValue(ADC_Type *base, lpadc_tune_value_t tuneValue)
1483 {
1484 base->CFG2 = (base->CFG2 & ~ADC_CFG2_TUNE_MASK) | ADC_CFG2_TUNE(tuneValue);
1485 }
1486
1487 /*!
1488 * @brief Get tune value which provides some variability in how many cycles are needed to complete a conversion.
1489 *
1490 * @param base LPADC peripheral base address.
1491 * @return The tune value, please refer to @ref lpadc_tune_value_t.
1492 */
LPADC_GetTuneValue(ADC_Type * base)1493 static inline lpadc_tune_value_t LPADC_GetTuneValue(ADC_Type *base)
1494 {
1495 return (lpadc_tune_value_t)((base->CFG2 & ADC_CFG2_TUNE_MASK) >> ADC_CFG2_TUNE_SHIFT);
1496 }
1497 #endif /* ((defined(FSL_FEATURE_LPADC_HAS_CTRL_CALHS)) && FSL_FEATURE_LPADC_HAS_CTRL_CALHS) */
1498
1499 #if (defined(FSL_FEATURE_LPADC_HAS_CFG2_JLEFT) && FSL_FEATURE_LPADC_HAS_CFG2_JLEFT)
1500 /*!
1501 * @brief Enable/disable left-justify format in 12-bit single-end mode.
1502 *
1503 * @param base LPADC peripheral base address.
1504 * @param enable Used to enable/disable left-justify format in 12-bit single-end mode:
1505 * - \b true Enable left-justify format in 12-bit single-end mode;
1506 * - \b false Disable left-justify format in 12-bit single-end mode.
1507 */
LPADC_EnableJustifiedLeft(ADC_Type * base,bool enable)1508 static inline void LPADC_EnableJustifiedLeft(ADC_Type *base, bool enable)
1509 {
1510 if (enable)
1511 {
1512 base->CFG2 |= ADC_CFG2_JLEFT_MASK;
1513 }
1514 else
1515 {
1516 base->CFG2 &= ~ADC_CFG2_JLEFT_MASK;
1517 }
1518 }
1519 #endif /* (defined(FSL_FEATURE_LPADC_HAS_CFG2_JLEFT) && FSL_FEATURE_LPADC_HAS_CFG2_JLEFT) */
1520
1521 /* @} */
1522
1523 #if defined(__cplusplus)
1524 }
1525 #endif
1526 /*!
1527 * @}
1528 */
1529 #endif /* FSL_LPADC_H_ */
1530
