1 /* 2 * Copyright 2022 NXP 3 * All rights reserved. 4 * 5 * SPDX-License-Identifier: BSD-3-Clause 6 */ 7 #ifndef FSL_ITRC_H_ 8 #define FSL_ITRC_H_ 9 10 #include "fsl_common.h" 11 12 /*! 13 * @addtogroup ITRC 14 * @{ 15 */ 16 17 /*! @file */ 18 19 /******************************************************************************* 20 * Definitions 21 *******************************************************************************/ 22 23 /*! @name Driver version */ 24 /*! @{ */ 25 /*! @brief Defines ITRC driver version 2.3.0. 26 * 27 * Change log: 28 * - Version 2.3.0 29 * - Update names of kITRC_SwEvent1/2 to kITRC_SwEvent0/1 to align with RM 30 * - Version 2.2.0 31 * - Update driver to new version and input events 32 * - Version 2.1.0 33 * - Make SYSCON glitch platform dependent 34 * - Version 2.0.0 35 * - initial version 36 */ 37 #define FSL_ITRC_DRIVER_VERSION (MAKE_VERSION(2, 3, 0)) 38 /*! @} */ 39 40 typedef enum _itrc_input_signals 41 { 42 kITRC_Glitch = 0U, 43 kITRC_Tamper = 1U, 44 kITRC_Cdog = 2U, 45 kITRC_BodVbat = 3u, 46 kITRC_BodVdd = 4u, 47 kITRC_Watchdog = 5u, 48 kITRC_FlashEcc = 6u, 49 kITRC_Ahb = 7u, 50 kITRC_ElsErr = 8u, 51 #if defined(FSL_FEATURE_ITRC_HAS_SYSCON_GLITCH) && (FSL_FEATURE_ITRC_HAS_SYSCON_GLITCH > 0) 52 kITRC_SysconGlitch = 9u, 53 #endif 54 kITRC_Pkc = 10u, 55 #if defined(ITRC_OUTX_SEL_OUTX_SELY_OUT_SEL_IN11_SELn_MASK) 56 kITRC_Cdog1 = 11u, 57 #endif /* ITRC_OUTX_SEL_OUTX_SELY_OUT_SEL_IN11_SELn_MASK */ 58 #if defined(ITRC_OUTX_SEL_OUTX_SELY_OUT_SEL_IN12_SELn_MASK) 59 kITRC_Watchdog1 = 12u, 60 #endif /* ITRC_OUTX_SEL_OUTX_SELY_OUT_SEL_IN12_SELn_MASK*/ 61 #if defined(ITRC_OUTX_SEL_OUTX_SELY_OUT_SEL_IN13_SELn_MASK) 62 kITRC_Freqme = 13u, 63 #endif /* ITRC_OUTX_SEL_OUTX_SELY_OUT_SEL_IN13_SELn_MASK */ 64 kITRC_SwEvent0 = 14u, 65 kITRC_SwEvent1 = 15u, 66 #if defined(ITRC_OUTX_SEL_1_OUTX_SELY_OUT_SEL_1_IN16_SELn_MASK) 67 kITRC_VddSysLow = 16u, 68 #endif /* ITRC_OUTX_SEL_1_OUTX_SELY_OUT_SEL_1_IN16_SELn_MASK */ 69 #if defined(ITRC_OUTX_SEL_1_OUTX_SELY_OUT_SEL_1_IN17_SELn_MASK) 70 kITRC_VddIoLow = 17u, 71 #endif /* ITRC_OUTX_SEL_1_OUTX_SELY_OUT_SEL_1_IN17_SELn_MASK */ 72 #if defined(ITRC_OUTX_SEL_1_OUTX_SELY_OUT_SEL_1_IN19_SELn_MASK) 73 kITRC_VddTemp = 19u, 74 #endif /* ITRC_OUTX_SEL_1_OUTX_SELY_OUT_SEL_1_IN19_SELn_MASK */ 75 #if defined(ITRC_OUTX_SEL_1_OUTX_SELY_OUT_SEL_1_IN20_SELn_MASK) 76 kITRC_VddClock = 20u, 77 #endif /* ITRC_OUTX_SEL_1_OUTX_SELY_OUT_SEL_1_IN20_SELn_MASK */ 78 #if defined(ITRC_OUTX_SEL_1_OUTX_SELY_OUT_SEL_1_IN21_SELn_MASK) 79 kITRC_INTM0 = 21u, 80 #endif /* ITRC_OUTX_SEL_1_OUTX_SELY_OUT_SEL_1_IN21_SELn_MASK */ 81 #if defined(ITRC_OUTX_SEL_1_OUTX_SELY_OUT_SEL_1_IN22_SELn_MASK) 82 kITRC_INTM1 = 22u, 83 #endif /* ITRC_OUTX_SEL_1_OUTX_SELY_OUT_SEL_1_IN22_SELn_MASK */ 84 #if defined(ITRC_OUTX_SEL_1_OUTX_SELY_OUT_SEL_1_IN23_SELn_MASK) 85 kITRC_INTM2 = 23u, 86 #endif /* ITRC_OUTX_SEL_1_OUTX_SELY_OUT_SEL_1_IN23_SELn_MASK */ 87 #if defined(ITRC_OUTX_SEL_1_OUTX_SELY_OUT_SEL_1_IN24_SELn_MASK) 88 kITRC_INTM3 = 24u, 89 #endif /* ITRC_OUTX_SEL_1_OUTX_SELY_OUT_SEL_1_IN24_SELn_MASK */ 90 #if defined(ITRC_OUTX_SEL_1_OUTX_SELY_OUT_SEL_1_IN25_SELn_MASK) && \ 91 defined(ITRC_OUTX_SEL_2_OUTX_SELY_OUT_SEL_2_IN32_SELn_MASK) 92 kITRC_SoCTrim0 = 25u, 93 kITRC_SoCTrim1 = 26u, 94 kITRC_SoCTrim2 = 27u, 95 kITRC_SoCTrim3 = 28u, 96 kITRC_SoCTrim4 = 29u, 97 kITRC_SoCTrim5 = 30u, 98 kITRC_SoCTrim6 = 31u, 99 kITRC_SoCTrim7 = 32u, 100 #endif /* ITRC_OUTX_SEL_x_OUTX_SELY_OUT_SEL_INxx_SELn_MASK */ 101 #if defined(ITRC_OUTX_SEL_2_OUTX_SELY_OUT_SEL_2_IN33_SELn_MASK) 102 kITRC_GdetSfr = 33u, 103 #endif /* ITRC_OUTX_SEL_x_OUTX_SELY_OUT_SEL_INxx_SELn_MASK */ 104 #if defined(ITRC_OUTX_SEL_2_OUTX_SELY_OUT_SEL_2_IN34_SELn_MASK) 105 kITRC_VddCore = 34u, 106 #endif /* ITRC_OUTX_SEL_2_OUTX_SELY_OUT_SEL_2_IN34_SELn_MASK */ 107 #if defined(ITRC_OUTX_SEL_2_OUTX_SELY_OUT_SEL_2_IN35_SELn_MASK) 108 kITRC_VddSys = 35u, 109 #endif /* ITRC_OUTX_SEL_2_OUTX_SELY_OUT_SEL_2_IN35_SELn_MASK */ 110 #if defined(ITRC_OUTX_SEL_2_OUTX_SELY_OUT_SEL_2_IN36_SELn_MASK) 111 kITRC_VddIo = 36u, 112 #endif /* ITRC_OUTX_SEL_2_OUTX_SELY_OUT_SEL_2_IN36_SELn_MASK */ 113 #if defined(ITRC_OUTX_SEL_2_OUTX_SELY_OUT_SEL_2_IN37_SELn_MASK) 114 kITRC_FlexspiGcm = 37u, 115 #endif /* ITRC_OUTX_SEL_2_OUTX_SELY_OUT_SEL_2_IN37_SELn_MASK */ 116 #if defined(ITRC_OUTX_SEL_2_OUTX_SELY_OUT_SEL_2_IN46_SELn_MASK) 117 kITRC_Sm3Err = 46u, 118 #endif /* ITRC_OUTX_SEL_2_OUTX_SELY_OUT_SEL_2_IN46_SELn_MASK */ 119 #if defined(ITRC_OUTX_SEL_2_OUTX_SELY_OUT_SEL_2_IN47_SELn_MASK) 120 kITRC_TrngErr = 47u, 121 #endif /* */ 122 } itrc_input_signals_t; 123 124 typedef enum _itrc_lock 125 { 126 kITRC_Unlock = 0U, 127 kITRC_Lock = 1U, 128 } itrc_lock_t; 129 130 typedef enum _itrc_enable 131 { 132 kITRC_Enable = 0U, 133 kITRC_Disable = 1U, 134 } itrc_enable_t; 135 136 typedef enum _itrc_out_signals 137 { 138 kITRC_Irq = 0U, 139 kITRC_ElsReset = 1U, 140 kITRC_PufZeroize = 2U, 141 kITRC_RamZeroize = 3u, 142 kITRC_ChipReset = 4u, 143 kITRC_TamperOut = 5u, 144 kITRC_TamperOut1 = 6u, 145 } itrc_out_signals_t; 146 147 /* Inputs 0 to 15 events mask */ 148 #if defined(FSL_FEATURE_ITRC_HAS_SYSCON_GLITCH) && (FSL_FEATURE_ITRC_HAS_SYSCON_GLITCH > 0) 149 #define IN_0_15_EVENTS_MASK \ 150 (ITRC_STATUS_IN0_STATUS_MASK | ITRC_STATUS_IN1_STATUS_MASK | ITRC_STATUS_IN2_STATUS_MASK | \ 151 ITRC_STATUS_IN3_STATUS_MASK | ITRC_STATUS_IN4_STATUS_MASK | ITRC_STATUS_IN5_STATUS_MASK | \ 152 ITRC_STATUS_IN6_STATUS_MASK | ITRC_STATUS_IN7_STATUS_MASK | ITRC_STATUS_IN8_STATUS_MASK | \ 153 ITRC_STATUS_IN9_STATUS_MASK | ITRC_STATUS_IN10_STATUS_MASK | ITRC_STATUS_IN14_STATUS_MASK | \ 154 ITRC_STATUS_IN15_STATUS_MASK) 155 #else 156 #define IN_0_15_EVENTS_MASK \ 157 (ITRC_STATUS_IN0_STATUS_MASK | ITRC_STATUS_IN1_STATUS_MASK | ITRC_STATUS_IN2_STATUS_MASK | \ 158 ITRC_STATUS_IN3_STATUS_MASK | ITRC_STATUS_IN4_STATUS_MASK | ITRC_STATUS_IN5_STATUS_MASK | \ 159 ITRC_STATUS_IN6_STATUS_MASK | ITRC_STATUS_IN7_STATUS_MASK | ITRC_STATUS_IN8_STATUS_MASK | \ 160 ITRC_STATUS_IN10_STATUS_MASK | ITRC_STATUS_IN14_STATUS_MASK | ITRC_STATUS_IN15_STATUS_MASK) 161 #endif /* FSL_FEATURE_ITRC_HAS_SYSCON_GLITCH */ 162 163 /* Inputs 15 to 47 events mask */ 164 #if defined(ITRC_STATUS1_IN16_STATUS_MASK) && defined(ITRC_STATUS1_IN47_STATUS) 165 #define IN_16_47_EVENTS_MASK \ 166 (ITRC_STATUS1_IN16_STATUS_MASK | ITRC_STATUS1_IN17_STATUS_MASK | ITRC_STATUS1_IN18_STATUS_MASK | \ 167 ITRC_STATUS1_IN19_STATUS_MASK | ITRC_STATUS1_IN20_STATUS_MASK | ITRC_STATUS1_IN24_21_STATUS_MASK | \ 168 ITRC_STATUS1_IN24_21_STATUS_MASK | ITRC_STATUS1_IN32_25_STATUS_MASK | ITRC_STATUS1_IN33_STATUS_MASK | \ 169 ITRC_STATUS1_IN34_STATUS_MASK | ITRC_STATUS1_IN35_STATUS_MASK | ITRC_STATUS1_IN36_STATUS_MASK | \ 170 ITRC_STATUS1_IN37_STATUS_MASK | ITRC_STATUS1_IN46_STATUS_MASK | ITRC_STATUS1_IN47_STATUS_MASK) 171 #endif /* ITRC_STATUS1_IN16_STATUS_MASK && ITRC_STATUS1_IN47_STATUS */ 172 173 /* Output actions mask */ 174 #if defined(ITRC_STATUS_OUT6_STATUS) 175 #define OUT_ACTIONS_MASK \ 176 (ITRC_STATUS_OUT0_STATUS_MASK | ITRC_STATUS_OUT1_STATUS_MASK | ITRC_STATUS_OUT2_STATUS_MASK | \ 177 ITRC_STATUS_OUT3_STATUS_MASK | ITRC_STATUS_OUT4_STATUS_MASK | ITRC_STATUS_OUT5_STATUS_MASK | \ 178 ITRC_STATUS_OUT6_STATUS_MASK) 179 #else 180 #define OUT_ACTIONS_MASK \ 181 (ITRC_STATUS_OUT0_STATUS_MASK | ITRC_STATUS_OUT1_STATUS_MASK | ITRC_STATUS_OUT2_STATUS_MASK | \ 182 ITRC_STATUS_OUT3_STATUS_MASK | ITRC_STATUS_OUT4_STATUS_MASK | ITRC_STATUS_OUT5_STATUS_MASK) 183 #endif /* ITRC_STATUS_OUT6_STATUS */ 184 185 #define ITRC_OUT_COUNT (7u) 186 #ifndef ITRC 187 #define ITRC ITRC0 188 #endif 189 190 /******************************************************************************* 191 * API 192 *******************************************************************************/ 193 194 extern void ITRC0_DriverIRQHandler(void); 195 196 #if defined(__cplusplus) 197 extern "C" { 198 #endif /* __cplusplus */ 199 200 /*! 201 * @name ITRC Functional Operation 202 * @{ 203 */ 204 205 /*! 206 * @brief Set ITRC Action to Event 207 * 208 * This function sets input Event signal to corresponding output Action response signal. 209 * 210 * @param base ITRC peripheral base address 211 * @param out ITRC OUT signal action 212 * @param in ITRC IN signal event 213 * @param lock if set locks INx_SEL configuration. This can be cleared only by PMC Core reset. 214 * @param enable if set input Event will be selected for output Action, otherwise disable (if not already locked). 215 * @return kStatus_Success if success, kStatus_InvalidArgument otherwise 216 */ 217 status_t ITRC_SetActionToEvent( 218 ITRC_Type *base, itrc_out_signals_t out, itrc_input_signals_t in, itrc_lock_t lock, itrc_enable_t enable); 219 220 /*! 221 * @brief Trigger ITRC SW Event 0 222 * 223 * This funciton set SW_EVENT0 register with value !=0 which triggers ITRC SW Event 0. 224 * 225 * @param base ITRC peripheral base address 226 */ 227 void ITRC_SetSWEvent0(ITRC_Type *base); 228 229 /*! 230 * @brief Trigger ITRC SW Event 1 231 * 232 * This funciton set SW_EVENT1 register with value !=0 which triggers ITRC SW Event 1. 233 * 234 * @param base ITRC peripheral base address 235 */ 236 void ITRC_SetSWEvent1(ITRC_Type *base); 237 238 /*! 239 * @brief Get ITRC Status 240 * 241 * This function returns ITRC register status. 242 * 243 * @param base ITRC peripheral base address 244 * @return Value of ITRC STATUS register 245 */ 246 uint32_t ITRC_GetStatus(ITRC_Type *base); 247 248 /*! 249 * @brief Clear ITRC status 250 * 251 * This function clears corresponding ITRC event or action in STATUS register. 252 * 253 * @param base ITRC peripheral base address 254 * @param word 32bit word represent corresponding event/action in STATUS register to be cleared (see 255 * ITRC_STATUS_INx/OUTx_STATUS) 256 * @return kStatus_Success if success, kStatus_InvalidArgument otherwise 257 */ 258 status_t ITRC_ClearStatus(ITRC_Type *base, uint32_t word); 259 260 #if defined(ITRC_STATUS1_IN16_STATUS_MASK) 261 /*! 262 * @brief Get ITRC Status 1 263 * 264 * This function returns ITRC STATUS1 register value. 265 * 266 * @param base ITRC peripheral base address 267 * @return Value of ITRC STATUS1 register 268 */ 269 uint32_t ITRC_GetStatus1(ITRC_Type *base); 270 271 /*! 272 * brief Clear ITRC status 1 273 * 274 * This function clears corresponding ITRC event or action in STATUS1 register. 275 * 276 * param base ITRC peripheral base address 277 * param word 32bit word represent corresponding event/action in STATUS1 register to be cleared (see 278 * ITRC_STATUS_INx/OUTx_STATUS) 279 * return kStatus_Success if success, kStatus_InvalidArgument otherwise 280 */ 281 status_t ITRC_ClearStatus1(ITRC_Type *base, uint32_t word); 282 #endif /* defined(ITRC_STATUS1_IN16_STATUS_MASK) */ 283 284 /*! 285 * @brief Clear All ITRC status 286 * 287 * This function clears all event and action status. 288 * 289 * @param base ITRC peripheral base address 290 * @return kStatus_Success if success 291 */ 292 status_t ITRC_ClearAllStatus(ITRC_Type *base); 293 294 /*! 295 * @brief Initialize ITRC 296 * 297 * This function initializes ITRC by enabling IRQ. 298 * 299 * @param base ITRC peripheral base address 300 * @param conf ITRC configuration structure 301 * @return Status of the init operation 302 */ 303 status_t ITRC_Init(ITRC_Type *base); 304 305 /*! 306 * @brief Deinitialize ITRC 307 * 308 * This function deinitializes ITRC by disabling IRQ. 309 * 310 * @param base ITRC peripheral base address 311 */ 312 void ITRC_Deinit(ITRC_Type *base); 313 314 /*! @}*/ 315 316 #if defined(__cplusplus) 317 } 318 #endif /* __cplusplus */ 319 320 /*! @}*/ /* end of group itrc */ 321 322 #endif /* FSL_ITRC_H_ */ 323
