1 /*
2 * Copyright 2022 NXP
3 * All rights reserved.
4 *
5 *
6 * SPDX-License-Identifier: BSD-3-Clause
7 */
8
9 #ifndef FSL_ERM_H_
10 #define FSL_ERM_H_
11
12 #include "fsl_common.h"
13
14 /*!
15 * @addtogroup erm
16 * @{
17 */
18
19 /******************************************************************************
20 * Definitions.
21 *****************************************************************************/
22
23 /*! @name Driver version */
24 /*! @{ */
25 /*! @brief Driver version. */
26 #define FSL_ERM_DRIVER_VERSION (MAKE_VERSION(2U, 0U, 1U))
27 /*! @} */
28
29 /*!
30 * @brief ERM interrupt configuration structure, default settings all disabled, _erm_interrupt_enable.
31 *
32 * This structure contains the settings for all of the ERM interrupt configurations.
33 */
34 enum
35 {
36 kERM_SingleCorrectionIntEnable = 0x08U, /*!< Single Correction Interrupt Notification enable.*/
37 kERM_NonCorrectableIntEnable = 0x04U, /*!< Non-Correction Interrupt Notification enable.*/
38
39 kERM_AllInterruptsEnable = 0xFFFFFFFFUL, /*!< All Interrupts enable */
40 };
41
42 /*!
43 * @brief ERM interrupt status, _erm_interrupt_flag.
44 *
45 * This provides constants for the ERM event status for use in the ERM functions.
46 */
47 enum
48 {
49 kERM_SingleBitCorrectionIntFlag = 0x08U, /*!< Single-Bit Correction Event.*/
50 kERM_NonCorrectableErrorIntFlag = 0x04U, /*!< Non-Correctable Error Event.*/
51
52 kERM_AllIntsFlag = 0xFFFFFFFFUL, /*!< All Events. */
53 };
54
55 /*******************************************************************************
56 * APIs
57 ******************************************************************************/
58
59 #if defined(__cplusplus)
60 extern "C" {
61 #endif
62
63 /*!
64 * @name Initialization and de-initialization
65 * @{
66 */
67
68 /*!
69 * @brief ERM module initialization function.
70 *
71 * @param base ERM base address.
72 */
73 void ERM_Init(ERM_Type *base);
74
75 /*!
76 * @brief De-initializes the ERM.
77 *
78 */
79 void ERM_Deinit(ERM_Type *base);
80
81 /*! @} */
82
83 /*!
84 * @name Interrupt
85 * @{
86 */
87 /*!
88 * @brief ERM enable interrupts.
89 *
90 * @param base ERM peripheral base address.
91 * @param channel memory channel.
92 * @param mask single correction interrupt or non-correction interrupt enable to disable for one specific memory region.
93 * Refer to "_erm_interrupt_enable" enumeration.
94 */
ERM_EnableInterrupts(ERM_Type * base,erm_memory_channel_t channel,uint32_t mask)95 static inline void ERM_EnableInterrupts(ERM_Type *base, erm_memory_channel_t channel, uint32_t mask)
96 {
97 uint32_t temp = 0x00U;
98 if ((uint32_t)channel <= 0x07U)
99 {
100 temp = base->CR0;
101 base->CR0 =
102 (temp & ~(0x0CUL << ((0x07U - (uint32_t)channel) * 4U))) | (mask << ((0x07U - (uint32_t)channel) * 4U));
103 }
104 #ifdef ERM_CR1_ESCIE8_MASK
105 else
106 {
107 temp = base->CR1;
108 base->CR1 = (temp & ~(0x0CUL << ((0x07U + 0x08U - (uint32_t)channel) * 4U))) |
109 (mask << ((0x07U + 0x08U - (uint32_t)channel) * 4U));
110 }
111 #endif
112 }
113
114 /*!
115 * @brief ERM module disable interrupts.
116 *
117 * @param base ERM base address.
118 * @param channel memory channel.
119 * @param mask single correction interrupt or non-correction interrupt enable to disable for one specific memory region.
120 * Refer to "_erm_interrupt_enable" enumeration.
121 */
ERM_DisableInterrupts(ERM_Type * base,erm_memory_channel_t channel,uint32_t mask)122 static inline void ERM_DisableInterrupts(ERM_Type *base, erm_memory_channel_t channel, uint32_t mask)
123 {
124 if ((uint32_t)channel <= 0x07U)
125 {
126 base->CR0 &= ~(mask << ((0x07U - (uint32_t)channel) * 4U));
127 }
128 #ifdef ERM_CR1_ESCIE8_MASK
129 else
130 {
131 base->CR1 &= ~(mask << ((0x07U + 0x08U - (uint32_t)channel) * 4U));
132 }
133 #endif
134 }
135
136 /*!
137 * @brief Gets ERM interrupt flags.
138 *
139 * @param base ERM peripheral base address.
140 * @return ERM event flags.
141 */
ERM_GetInterruptStatus(ERM_Type * base,erm_memory_channel_t channel)142 static inline uint32_t ERM_GetInterruptStatus(ERM_Type *base, erm_memory_channel_t channel)
143 {
144 if ((uint32_t)channel <= 0x07U)
145 {
146 return ((base->SR0 & (uint32_t)kERM_AllIntsFlag) >> (0x07U - (uint32_t)channel) * 4U);
147 }
148 #ifdef ERM_SR1_SBC8_MASK
149 else
150 {
151 return ((base->SR1 & (uint32_t)kERM_AllIntsFlag) >> ((0x07U + 0x08U - (uint32_t)channel) * 4U));
152 }
153 #else
154 {
155 return 0;
156 }
157 #endif
158 }
159
160 /*!
161 * @brief ERM module clear interrupt status flag.
162 *
163 * @param base ERM base address.
164 * @param mask event flag to clear. Refer to "_erm_interrupt_flag" enumeration.
165 */
ERM_ClearInterruptStatus(ERM_Type * base,erm_memory_channel_t channel,uint32_t mask)166 static inline void ERM_ClearInterruptStatus(ERM_Type *base, erm_memory_channel_t channel, uint32_t mask)
167 {
168 if ((uint32_t)channel <= 0x07U)
169 {
170 base->SR0 = mask << ((0x07U - (uint32_t)channel) * 4U);
171 }
172 #ifdef ERM_SR1_SBC8_MASK
173 else
174 {
175 base->SR1 = mask << ((0x07U + 0x08U - (uint32_t)channel) * 4U);
176 }
177 #endif
178 }
179
180 /*! @} */
181
182 /*!
183 * @name functional
184 * @{
185 */
186
187 /*!
188 * @brief ERM get memory error absolute address, which capturing the address of the last ECC event in Memory n.
189 *
190 * @param base ERM base address.
191 * @param channel memory channel.
192 * @retval memory error absolute address.
193 */
194
195 uint32_t ERM_GetMemoryErrorAddr(ERM_Type *base, erm_memory_channel_t channel);
196
197 /*!
198 * @brief ERM get syndrome, which identifies the pertinent bit position on a correctable, single-bit data inversion or a
199 * non-correctable, single-bit address inversion. The syndrome value does not provide any additional diagnostic
200 * information on non-correctable, multi-bit inversions.
201 *
202 * @param base ERM base address.
203 * @param channel memory channel.
204 * @retval syndrome value.
205 */
206 uint32_t ERM_GetSyndrome(ERM_Type *base, erm_memory_channel_t channel);
207
208 /*!
209 * @brief ERM get error count, which records the count value of the number of correctable ECC error events for Memory
210 * n. Non-correctable errors are considered a serious fault, so the ERM does not provide any mechanism to count
211 * non-correctable errors. Only correctable errors are counted.
212 *
213 * @param base ERM base address.
214 * @param channel memory channel.
215 * @retval error count.
216 */
217 uint32_t ERM_GetErrorCount(ERM_Type *base, erm_memory_channel_t channel);
218
219 /*!
220 * @brief ERM reset error count.
221 *
222 * @param base ERM base address.
223 * @param channel memory channel.
224 */
225 void ERM_ResetErrorCount(ERM_Type *base, erm_memory_channel_t channel);
226
227 /*! @}*/
228
229 #if defined(__cplusplus)
230 }
231 #endif
232
233 /*! @}*/
234
235 #endif
236
