Home
last modified time | relevance | path

Searched refs:kCLOCK_DivUsb1Clk (Results 1 – 25 of 30) sorted by relevance

12

/hal_nxp-latest/mcux/mcux-sdk/devices/LPC54628/drivers/
Dfsl_clock.c2740 … CLOCK_SetClkDiv(kCLOCK_DivUsb1Clk, 2, false); /*!< Div by 2 to get 48MHz, no divider reset */ in CLOCK_EnableUsbhs0DeviceClock()
2744 … CLOCK_SetClkDiv(kCLOCK_DivUsb1Clk, 1, false); /*!< Div by 1 to get 48MHz, no divider reset */ in CLOCK_EnableUsbhs0DeviceClock()
2765 CLOCK_SetClkDiv(kCLOCK_DivUsb1Clk, 1U, false); in CLOCK_EnableUsbhs0DeviceClock()
2794 … CLOCK_SetClkDiv(kCLOCK_DivUsb1Clk, 2, false); /*!< Div by 2 to get 48MHz, no divider reset */ in CLOCK_EnableUsbhs0HostClock()
2798 … CLOCK_SetClkDiv(kCLOCK_DivUsb1Clk, 1, false); /*!< Div by 1 to get 48MHz, no divider reset */ in CLOCK_EnableUsbhs0HostClock()
2819 CLOCK_SetClkDiv(kCLOCK_DivUsb1Clk, 1U, false); in CLOCK_EnableUsbhs0HostClock()
Dfsl_clock.h906 kCLOCK_DivUsb1Clk = 39, /*!< Usb1 Clock Divider. */ enumerator
/hal_nxp-latest/mcux/mcux-sdk/devices/LPC54S005/drivers/
Dfsl_clock.c2728 … CLOCK_SetClkDiv(kCLOCK_DivUsb1Clk, 2U, false); /*!< Div by 2 to get 48MHz, no divider reset */ in CLOCK_EnableUsbhs0DeviceClock()
2732 … CLOCK_SetClkDiv(kCLOCK_DivUsb1Clk, 1U, false); /*!< Div by 1 to get 48MHz, no divider reset */ in CLOCK_EnableUsbhs0DeviceClock()
2753 CLOCK_SetClkDiv(kCLOCK_DivUsb1Clk, 1U, false); in CLOCK_EnableUsbhs0DeviceClock()
2782 … CLOCK_SetClkDiv(kCLOCK_DivUsb1Clk, 2U, false); /*!< Div by 2 to get 48MHz, no divider reset */ in CLOCK_EnableUsbhs0HostClock()
2786 … CLOCK_SetClkDiv(kCLOCK_DivUsb1Clk, 1U, false); /*!< Div by 1 to get 48MHz, no divider reset */ in CLOCK_EnableUsbhs0HostClock()
2807 CLOCK_SetClkDiv(kCLOCK_DivUsb1Clk, 1U, false); in CLOCK_EnableUsbhs0HostClock()
Dfsl_clock.h919 kCLOCK_DivUsb1Clk = 39, /*!< Usb1 Clock Divider. */ enumerator
/hal_nxp-latest/mcux/mcux-sdk/devices/LPC54S018/drivers/
Dfsl_clock.c2738 … CLOCK_SetClkDiv(kCLOCK_DivUsb1Clk, 2U, false); /*!< Div by 2 to get 48MHz, no divider reset */ in CLOCK_EnableUsbhs0DeviceClock()
2742 … CLOCK_SetClkDiv(kCLOCK_DivUsb1Clk, 1U, false); /*!< Div by 1 to get 48MHz, no divider reset */ in CLOCK_EnableUsbhs0DeviceClock()
2763 CLOCK_SetClkDiv(kCLOCK_DivUsb1Clk, 1U, false); in CLOCK_EnableUsbhs0DeviceClock()
2792 … CLOCK_SetClkDiv(kCLOCK_DivUsb1Clk, 2U, false); /*!< Div by 2 to get 48MHz, no divider reset */ in CLOCK_EnableUsbhs0HostClock()
2796 … CLOCK_SetClkDiv(kCLOCK_DivUsb1Clk, 1U, false); /*!< Div by 1 to get 48MHz, no divider reset */ in CLOCK_EnableUsbhs0HostClock()
2817 CLOCK_SetClkDiv(kCLOCK_DivUsb1Clk, 1U, false); in CLOCK_EnableUsbhs0HostClock()
Dfsl_clock.h921 kCLOCK_DivUsb1Clk = 39, /*!< Usb1 Clock Divider. */ enumerator
/hal_nxp-latest/mcux/mcux-sdk/devices/LPC54S016/drivers/
Dfsl_clock.c2729 … CLOCK_SetClkDiv(kCLOCK_DivUsb1Clk, 2U, false); /*!< Div by 2 to get 48MHz, no divider reset */ in CLOCK_EnableUsbhs0DeviceClock()
2733 … CLOCK_SetClkDiv(kCLOCK_DivUsb1Clk, 1U, false); /*!< Div by 1 to get 48MHz, no divider reset */ in CLOCK_EnableUsbhs0DeviceClock()
2754 CLOCK_SetClkDiv(kCLOCK_DivUsb1Clk, 1U, false); in CLOCK_EnableUsbhs0DeviceClock()
2783 … CLOCK_SetClkDiv(kCLOCK_DivUsb1Clk, 2U, false); /*!< Div by 2 to get 48MHz, no divider reset */ in CLOCK_EnableUsbhs0HostClock()
2787 … CLOCK_SetClkDiv(kCLOCK_DivUsb1Clk, 1U, false); /*!< Div by 1 to get 48MHz, no divider reset */ in CLOCK_EnableUsbhs0HostClock()
2808 CLOCK_SetClkDiv(kCLOCK_DivUsb1Clk, 1U, false); in CLOCK_EnableUsbhs0HostClock()
Dfsl_clock.h919 kCLOCK_DivUsb1Clk = 39, /*!< Usb1 Clock Divider. */ enumerator
/hal_nxp-latest/mcux/mcux-sdk/devices/LPC54618/drivers/
Dfsl_clock.c2739 … CLOCK_SetClkDiv(kCLOCK_DivUsb1Clk, 2, false); /*!< Div by 2 to get 48MHz, no divider reset */ in CLOCK_EnableUsbhs0DeviceClock()
2743 … CLOCK_SetClkDiv(kCLOCK_DivUsb1Clk, 1, false); /*!< Div by 1 to get 48MHz, no divider reset */ in CLOCK_EnableUsbhs0DeviceClock()
2764 CLOCK_SetClkDiv(kCLOCK_DivUsb1Clk, 1U, false); in CLOCK_EnableUsbhs0DeviceClock()
2793 … CLOCK_SetClkDiv(kCLOCK_DivUsb1Clk, 2, false); /*!< Div by 2 to get 48MHz, no divider reset */ in CLOCK_EnableUsbhs0HostClock()
2797 … CLOCK_SetClkDiv(kCLOCK_DivUsb1Clk, 1, false); /*!< Div by 1 to get 48MHz, no divider reset */ in CLOCK_EnableUsbhs0HostClock()
2818 CLOCK_SetClkDiv(kCLOCK_DivUsb1Clk, 1U, false); in CLOCK_EnableUsbhs0HostClock()
Dfsl_clock.h907 kCLOCK_DivUsb1Clk = 39, /*!< Usb1 Clock Divider. */ enumerator
/hal_nxp-latest/mcux/mcux-sdk/devices/LPC54606/drivers/
Dfsl_clock.c2740 … CLOCK_SetClkDiv(kCLOCK_DivUsb1Clk, 2, false); /*!< Div by 2 to get 48MHz, no divider reset */ in CLOCK_EnableUsbhs0DeviceClock()
2744 … CLOCK_SetClkDiv(kCLOCK_DivUsb1Clk, 1, false); /*!< Div by 1 to get 48MHz, no divider reset */ in CLOCK_EnableUsbhs0DeviceClock()
2765 CLOCK_SetClkDiv(kCLOCK_DivUsb1Clk, 1U, false); in CLOCK_EnableUsbhs0DeviceClock()
2794 … CLOCK_SetClkDiv(kCLOCK_DivUsb1Clk, 2, false); /*!< Div by 2 to get 48MHz, no divider reset */ in CLOCK_EnableUsbhs0HostClock()
2798 … CLOCK_SetClkDiv(kCLOCK_DivUsb1Clk, 1, false); /*!< Div by 1 to get 48MHz, no divider reset */ in CLOCK_EnableUsbhs0HostClock()
2819 CLOCK_SetClkDiv(kCLOCK_DivUsb1Clk, 1U, false); in CLOCK_EnableUsbhs0HostClock()
/hal_nxp-latest/mcux/mcux-sdk/devices/LPC54605/drivers/
Dfsl_clock.c2740 … CLOCK_SetClkDiv(kCLOCK_DivUsb1Clk, 2, false); /*!< Div by 2 to get 48MHz, no divider reset */ in CLOCK_EnableUsbhs0DeviceClock()
2744 … CLOCK_SetClkDiv(kCLOCK_DivUsb1Clk, 1, false); /*!< Div by 1 to get 48MHz, no divider reset */ in CLOCK_EnableUsbhs0DeviceClock()
2765 CLOCK_SetClkDiv(kCLOCK_DivUsb1Clk, 1U, false); in CLOCK_EnableUsbhs0DeviceClock()
2794 … CLOCK_SetClkDiv(kCLOCK_DivUsb1Clk, 2, false); /*!< Div by 2 to get 48MHz, no divider reset */ in CLOCK_EnableUsbhs0HostClock()
2798 … CLOCK_SetClkDiv(kCLOCK_DivUsb1Clk, 1, false); /*!< Div by 1 to get 48MHz, no divider reset */ in CLOCK_EnableUsbhs0HostClock()
2819 CLOCK_SetClkDiv(kCLOCK_DivUsb1Clk, 1U, false); in CLOCK_EnableUsbhs0HostClock()
Dfsl_clock.h907 kCLOCK_DivUsb1Clk = 39, /*!< Usb1 Clock Divider. */ enumerator
/hal_nxp-latest/mcux/mcux-sdk/devices/LPC54607/drivers/
Dfsl_clock.c2740 … CLOCK_SetClkDiv(kCLOCK_DivUsb1Clk, 2, false); /*!< Div by 2 to get 48MHz, no divider reset */ in CLOCK_EnableUsbhs0DeviceClock()
2744 … CLOCK_SetClkDiv(kCLOCK_DivUsb1Clk, 1, false); /*!< Div by 1 to get 48MHz, no divider reset */ in CLOCK_EnableUsbhs0DeviceClock()
2765 CLOCK_SetClkDiv(kCLOCK_DivUsb1Clk, 1U, false); in CLOCK_EnableUsbhs0DeviceClock()
2794 … CLOCK_SetClkDiv(kCLOCK_DivUsb1Clk, 2, false); /*!< Div by 2 to get 48MHz, no divider reset */ in CLOCK_EnableUsbhs0HostClock()
2798 … CLOCK_SetClkDiv(kCLOCK_DivUsb1Clk, 1, false); /*!< Div by 1 to get 48MHz, no divider reset */ in CLOCK_EnableUsbhs0HostClock()
2819 CLOCK_SetClkDiv(kCLOCK_DivUsb1Clk, 1U, false); in CLOCK_EnableUsbhs0HostClock()
Dfsl_clock.h907 kCLOCK_DivUsb1Clk = 39, /*!< Usb1 Clock Divider. */ enumerator
/hal_nxp-latest/mcux/mcux-sdk/devices/LPC54608/drivers/
Dfsl_clock.c2740 … CLOCK_SetClkDiv(kCLOCK_DivUsb1Clk, 2, false); /*!< Div by 2 to get 48MHz, no divider reset */ in CLOCK_EnableUsbhs0DeviceClock()
2744 … CLOCK_SetClkDiv(kCLOCK_DivUsb1Clk, 1, false); /*!< Div by 1 to get 48MHz, no divider reset */ in CLOCK_EnableUsbhs0DeviceClock()
2765 CLOCK_SetClkDiv(kCLOCK_DivUsb1Clk, 1U, false); in CLOCK_EnableUsbhs0DeviceClock()
2794 … CLOCK_SetClkDiv(kCLOCK_DivUsb1Clk, 2, false); /*!< Div by 2 to get 48MHz, no divider reset */ in CLOCK_EnableUsbhs0HostClock()
2798 … CLOCK_SetClkDiv(kCLOCK_DivUsb1Clk, 1, false); /*!< Div by 1 to get 48MHz, no divider reset */ in CLOCK_EnableUsbhs0HostClock()
2819 CLOCK_SetClkDiv(kCLOCK_DivUsb1Clk, 1U, false); in CLOCK_EnableUsbhs0HostClock()
Dfsl_clock.h907 kCLOCK_DivUsb1Clk = 39, /*!< Usb1 Clock Divider. */ enumerator
/hal_nxp-latest/mcux/mcux-sdk/devices/LPC54016/drivers/
Dfsl_clock.c2730 … CLOCK_SetClkDiv(kCLOCK_DivUsb1Clk, 2U, false); /*!< Div by 2 to get 48MHz, no divider reset */ in CLOCK_EnableUsbhs0DeviceClock()
2734 … CLOCK_SetClkDiv(kCLOCK_DivUsb1Clk, 1U, false); /*!< Div by 1 to get 48MHz, no divider reset */ in CLOCK_EnableUsbhs0DeviceClock()
2755 CLOCK_SetClkDiv(kCLOCK_DivUsb1Clk, 1U, false); in CLOCK_EnableUsbhs0DeviceClock()
2784 … CLOCK_SetClkDiv(kCLOCK_DivUsb1Clk, 2U, false); /*!< Div by 2 to get 48MHz, no divider reset */ in CLOCK_EnableUsbhs0HostClock()
2788 … CLOCK_SetClkDiv(kCLOCK_DivUsb1Clk, 1U, false); /*!< Div by 1 to get 48MHz, no divider reset */ in CLOCK_EnableUsbhs0HostClock()
2809 CLOCK_SetClkDiv(kCLOCK_DivUsb1Clk, 1U, false); in CLOCK_EnableUsbhs0HostClock()
/hal_nxp-latest/mcux/mcux-sdk/devices/LPC54018/drivers/
Dfsl_clock.c2738 … CLOCK_SetClkDiv(kCLOCK_DivUsb1Clk, 2U, false); /*!< Div by 2 to get 48MHz, no divider reset */ in CLOCK_EnableUsbhs0DeviceClock()
2742 … CLOCK_SetClkDiv(kCLOCK_DivUsb1Clk, 1U, false); /*!< Div by 1 to get 48MHz, no divider reset */ in CLOCK_EnableUsbhs0DeviceClock()
2763 CLOCK_SetClkDiv(kCLOCK_DivUsb1Clk, 1U, false); in CLOCK_EnableUsbhs0DeviceClock()
2792 … CLOCK_SetClkDiv(kCLOCK_DivUsb1Clk, 2U, false); /*!< Div by 2 to get 48MHz, no divider reset */ in CLOCK_EnableUsbhs0HostClock()
2796 … CLOCK_SetClkDiv(kCLOCK_DivUsb1Clk, 1U, false); /*!< Div by 1 to get 48MHz, no divider reset */ in CLOCK_EnableUsbhs0HostClock()
2817 CLOCK_SetClkDiv(kCLOCK_DivUsb1Clk, 1U, false); in CLOCK_EnableUsbhs0HostClock()
/hal_nxp-latest/mcux/mcux-sdk/devices/LPC54018M/drivers/
Dfsl_clock.c2730 … CLOCK_SetClkDiv(kCLOCK_DivUsb1Clk, 2U, false); /*!< Div by 2 to get 48MHz, no divider reset */ in CLOCK_EnableUsbhs0DeviceClock()
2734 … CLOCK_SetClkDiv(kCLOCK_DivUsb1Clk, 1U, false); /*!< Div by 1 to get 48MHz, no divider reset */ in CLOCK_EnableUsbhs0DeviceClock()
2755 CLOCK_SetClkDiv(kCLOCK_DivUsb1Clk, 1U, false); in CLOCK_EnableUsbhs0DeviceClock()
2784 … CLOCK_SetClkDiv(kCLOCK_DivUsb1Clk, 2U, false); /*!< Div by 2 to get 48MHz, no divider reset */ in CLOCK_EnableUsbhs0HostClock()
2788 … CLOCK_SetClkDiv(kCLOCK_DivUsb1Clk, 1U, false); /*!< Div by 1 to get 48MHz, no divider reset */ in CLOCK_EnableUsbhs0HostClock()
2809 CLOCK_SetClkDiv(kCLOCK_DivUsb1Clk, 1U, false); in CLOCK_EnableUsbhs0HostClock()
Dfsl_clock.h917 kCLOCK_DivUsb1Clk = 39, /*!< Usb1 Clock Divider. */ enumerator
/hal_nxp-latest/mcux/mcux-sdk/devices/LPC54005/drivers/
Dfsl_clock.c2728 … CLOCK_SetClkDiv(kCLOCK_DivUsb1Clk, 2U, false); /*!< Div by 2 to get 48MHz, no divider reset */ in CLOCK_EnableUsbhs0DeviceClock()
2732 … CLOCK_SetClkDiv(kCLOCK_DivUsb1Clk, 1U, false); /*!< Div by 1 to get 48MHz, no divider reset */ in CLOCK_EnableUsbhs0DeviceClock()
2753 CLOCK_SetClkDiv(kCLOCK_DivUsb1Clk, 1U, false); in CLOCK_EnableUsbhs0DeviceClock()
2782 … CLOCK_SetClkDiv(kCLOCK_DivUsb1Clk, 2U, false); /*!< Div by 2 to get 48MHz, no divider reset */ in CLOCK_EnableUsbhs0HostClock()
2786 … CLOCK_SetClkDiv(kCLOCK_DivUsb1Clk, 1U, false); /*!< Div by 1 to get 48MHz, no divider reset */ in CLOCK_EnableUsbhs0HostClock()
2807 CLOCK_SetClkDiv(kCLOCK_DivUsb1Clk, 1U, false); in CLOCK_EnableUsbhs0HostClock()
Dfsl_clock.h917 kCLOCK_DivUsb1Clk = 39, /*!< Usb1 Clock Divider. */ enumerator
/hal_nxp-latest/mcux/mcux-sdk/devices/LPC54616/drivers/
Dfsl_clock.c2719 … CLOCK_SetClkDiv(kCLOCK_DivUsb1Clk, 2, false); /*!< Div by 2 to get 48MHz, no divider reset */ in CLOCK_EnableUsbhs0DeviceClock()
2723 … CLOCK_SetClkDiv(kCLOCK_DivUsb1Clk, 1, false); /*!< Div by 1 to get 48MHz, no divider reset */ in CLOCK_EnableUsbhs0DeviceClock()
2744 CLOCK_SetClkDiv(kCLOCK_DivUsb1Clk, 1U, false); in CLOCK_EnableUsbhs0DeviceClock()
2773 … CLOCK_SetClkDiv(kCLOCK_DivUsb1Clk, 2, false); /*!< Div by 2 to get 48MHz, no divider reset */ in CLOCK_EnableUsbhs0HostClock()
2777 … CLOCK_SetClkDiv(kCLOCK_DivUsb1Clk, 1, false); /*!< Div by 1 to get 48MHz, no divider reset */ in CLOCK_EnableUsbhs0HostClock()
2798 CLOCK_SetClkDiv(kCLOCK_DivUsb1Clk, 1U, false); in CLOCK_EnableUsbhs0HostClock()
/hal_nxp-latest/mcux/mcux-sdk/devices/LPC54S018M/drivers/
Dfsl_clock.c2738 … CLOCK_SetClkDiv(kCLOCK_DivUsb1Clk, 2U, false); /*!< Div by 2 to get 48MHz, no divider reset */ in CLOCK_EnableUsbhs0DeviceClock()
2742 … CLOCK_SetClkDiv(kCLOCK_DivUsb1Clk, 1U, false); /*!< Div by 1 to get 48MHz, no divider reset */ in CLOCK_EnableUsbhs0DeviceClock()
2763 CLOCK_SetClkDiv(kCLOCK_DivUsb1Clk, 1U, false); in CLOCK_EnableUsbhs0DeviceClock()
2792 … CLOCK_SetClkDiv(kCLOCK_DivUsb1Clk, 2U, false); /*!< Div by 2 to get 48MHz, no divider reset */ in CLOCK_EnableUsbhs0HostClock()
2796 … CLOCK_SetClkDiv(kCLOCK_DivUsb1Clk, 1U, false); /*!< Div by 1 to get 48MHz, no divider reset */ in CLOCK_EnableUsbhs0HostClock()
2817 CLOCK_SetClkDiv(kCLOCK_DivUsb1Clk, 1U, false); in CLOCK_EnableUsbhs0HostClock()

12