| /hal_nxp-latest/mcux/mcux-sdk/boards/lpcxpresso54s018/ |
| D | clock_config.c | 257 …CLOCK_SetClkDiv(kCLOCK_DivUsb0Clk, 0U, true); /*!< Reset USB0CLKDIV divider count… in BOARD_BootClockPLL180M()
258 …CLOCK_SetClkDiv(kCLOCK_DivUsb0Clk, 2U, false); /*!< Set USB0CLKDIV divider to val… in BOARD_BootClockPLL180M()
|
| /hal_nxp-latest/mcux/mcux-sdk/boards/lpcxpresso54628/ |
| D | clock_config.c | 326 …CLOCK_SetClkDiv(kCLOCK_DivUsb0Clk, 0U, true); /*!< Reset USB0CLKDIV divider count… in BOARD_BootClockPLL220M()
327 …CLOCK_SetClkDiv(kCLOCK_DivUsb0Clk, 2U, false); /*!< Set USB0CLKDIV divider to val… in BOARD_BootClockPLL220M()
|
| /hal_nxp-latest/mcux/mcux-sdk/devices/LPC54628/drivers/ |
| D | fsl_clock.c | 2634 … CLOCK_SetClkDiv(kCLOCK_DivUsb0Clk, 2, false); /*!< Div by 2 to get 48MHz, no divider reset */ in CLOCK_EnableUsbfs0DeviceClock()
2638 … CLOCK_SetClkDiv(kCLOCK_DivUsb0Clk, 1, false); /*!< Div by 1 to get 48MHz, no divider reset */ in CLOCK_EnableUsbfs0DeviceClock()
2659 CLOCK_SetClkDiv(kCLOCK_DivUsb0Clk, 1U, false); in CLOCK_EnableUsbfs0DeviceClock()
2687 … CLOCK_SetClkDiv(kCLOCK_DivUsb0Clk, 2, false); /*!< Div by 2 to get 48MHz, no divider reset */ in CLOCK_EnableUsbfs0HostClock()
2691 … CLOCK_SetClkDiv(kCLOCK_DivUsb0Clk, 1, false); /*!< Div by 1 to get 48MHz, no divider reset */ in CLOCK_EnableUsbfs0HostClock()
2712 CLOCK_SetClkDiv(kCLOCK_DivUsb0Clk, 1U, false); in CLOCK_EnableUsbfs0HostClock()
|
| /hal_nxp-latest/mcux/mcux-sdk/devices/LPC54S005/drivers/ |
| D | fsl_clock.c | 2622 … CLOCK_SetClkDiv(kCLOCK_DivUsb0Clk, 2U, false); /*!< Div by 2 to get 48MHz, no divider reset */ in CLOCK_EnableUsbfs0DeviceClock()
2626 … CLOCK_SetClkDiv(kCLOCK_DivUsb0Clk, 1U, false); /*!< Div by 1 to get 48MHz, no divider reset */ in CLOCK_EnableUsbfs0DeviceClock()
2647 CLOCK_SetClkDiv(kCLOCK_DivUsb0Clk, 1U, false); in CLOCK_EnableUsbfs0DeviceClock()
2675 … CLOCK_SetClkDiv(kCLOCK_DivUsb0Clk, 2U, false); /*!< Div by 2 to get 48MHz, no divider reset */ in CLOCK_EnableUsbfs0HostClock()
2679 … CLOCK_SetClkDiv(kCLOCK_DivUsb0Clk, 1U, false); /*!< Div by 1 to get 48MHz, no divider reset */ in CLOCK_EnableUsbfs0HostClock()
2700 CLOCK_SetClkDiv(kCLOCK_DivUsb0Clk, 1U, false); in CLOCK_EnableUsbfs0HostClock()
|
| /hal_nxp-latest/mcux/mcux-sdk/devices/LPC54S018/drivers/ |
| D | fsl_clock.c | 2632 … CLOCK_SetClkDiv(kCLOCK_DivUsb0Clk, 2U, false); /*!< Div by 2 to get 48MHz, no divider reset */ in CLOCK_EnableUsbfs0DeviceClock()
2636 … CLOCK_SetClkDiv(kCLOCK_DivUsb0Clk, 1U, false); /*!< Div by 1 to get 48MHz, no divider reset */ in CLOCK_EnableUsbfs0DeviceClock()
2657 CLOCK_SetClkDiv(kCLOCK_DivUsb0Clk, 1U, false); in CLOCK_EnableUsbfs0DeviceClock()
2685 … CLOCK_SetClkDiv(kCLOCK_DivUsb0Clk, 2U, false); /*!< Div by 2 to get 48MHz, no divider reset */ in CLOCK_EnableUsbfs0HostClock()
2689 … CLOCK_SetClkDiv(kCLOCK_DivUsb0Clk, 1U, false); /*!< Div by 1 to get 48MHz, no divider reset */ in CLOCK_EnableUsbfs0HostClock()
2710 CLOCK_SetClkDiv(kCLOCK_DivUsb0Clk, 1U, false); in CLOCK_EnableUsbfs0HostClock()
|
| /hal_nxp-latest/mcux/mcux-sdk/devices/LPC54S016/drivers/ |
| D | fsl_clock.c | 2623 … CLOCK_SetClkDiv(kCLOCK_DivUsb0Clk, 2U, false); /*!< Div by 2 to get 48MHz, no divider reset */ in CLOCK_EnableUsbfs0DeviceClock()
2627 … CLOCK_SetClkDiv(kCLOCK_DivUsb0Clk, 1U, false); /*!< Div by 1 to get 48MHz, no divider reset */ in CLOCK_EnableUsbfs0DeviceClock()
2648 CLOCK_SetClkDiv(kCLOCK_DivUsb0Clk, 1U, false); in CLOCK_EnableUsbfs0DeviceClock()
2676 … CLOCK_SetClkDiv(kCLOCK_DivUsb0Clk, 2U, false); /*!< Div by 2 to get 48MHz, no divider reset */ in CLOCK_EnableUsbfs0HostClock()
2680 … CLOCK_SetClkDiv(kCLOCK_DivUsb0Clk, 1U, false); /*!< Div by 1 to get 48MHz, no divider reset */ in CLOCK_EnableUsbfs0HostClock()
2701 CLOCK_SetClkDiv(kCLOCK_DivUsb0Clk, 1U, false); in CLOCK_EnableUsbfs0HostClock()
|
| /hal_nxp-latest/mcux/mcux-sdk/devices/LPC54618/drivers/ |
| D | fsl_clock.c | 2633 … CLOCK_SetClkDiv(kCLOCK_DivUsb0Clk, 2, false); /*!< Div by 2 to get 48MHz, no divider reset */ in CLOCK_EnableUsbfs0DeviceClock()
2637 … CLOCK_SetClkDiv(kCLOCK_DivUsb0Clk, 1, false); /*!< Div by 1 to get 48MHz, no divider reset */ in CLOCK_EnableUsbfs0DeviceClock()
2658 CLOCK_SetClkDiv(kCLOCK_DivUsb0Clk, 1U, false); in CLOCK_EnableUsbfs0DeviceClock()
2686 … CLOCK_SetClkDiv(kCLOCK_DivUsb0Clk, 2, false); /*!< Div by 2 to get 48MHz, no divider reset */ in CLOCK_EnableUsbfs0HostClock()
2690 … CLOCK_SetClkDiv(kCLOCK_DivUsb0Clk, 1, false); /*!< Div by 1 to get 48MHz, no divider reset */ in CLOCK_EnableUsbfs0HostClock()
2711 CLOCK_SetClkDiv(kCLOCK_DivUsb0Clk, 1U, false); in CLOCK_EnableUsbfs0HostClock()
|
| /hal_nxp-latest/mcux/mcux-sdk/devices/LPC54606/drivers/ |
| D | fsl_clock.c | 2634 … CLOCK_SetClkDiv(kCLOCK_DivUsb0Clk, 2, false); /*!< Div by 2 to get 48MHz, no divider reset */ in CLOCK_EnableUsbfs0DeviceClock()
2638 … CLOCK_SetClkDiv(kCLOCK_DivUsb0Clk, 1, false); /*!< Div by 1 to get 48MHz, no divider reset */ in CLOCK_EnableUsbfs0DeviceClock()
2659 CLOCK_SetClkDiv(kCLOCK_DivUsb0Clk, 1U, false); in CLOCK_EnableUsbfs0DeviceClock()
2687 … CLOCK_SetClkDiv(kCLOCK_DivUsb0Clk, 2, false); /*!< Div by 2 to get 48MHz, no divider reset */ in CLOCK_EnableUsbfs0HostClock()
2691 … CLOCK_SetClkDiv(kCLOCK_DivUsb0Clk, 1, false); /*!< Div by 1 to get 48MHz, no divider reset */ in CLOCK_EnableUsbfs0HostClock()
2712 CLOCK_SetClkDiv(kCLOCK_DivUsb0Clk, 1U, false); in CLOCK_EnableUsbfs0HostClock()
|
| /hal_nxp-latest/mcux/mcux-sdk/devices/LPC54605/drivers/ |
| D | fsl_clock.c | 2634 … CLOCK_SetClkDiv(kCLOCK_DivUsb0Clk, 2, false); /*!< Div by 2 to get 48MHz, no divider reset */ in CLOCK_EnableUsbfs0DeviceClock()
2638 … CLOCK_SetClkDiv(kCLOCK_DivUsb0Clk, 1, false); /*!< Div by 1 to get 48MHz, no divider reset */ in CLOCK_EnableUsbfs0DeviceClock()
2659 CLOCK_SetClkDiv(kCLOCK_DivUsb0Clk, 1U, false); in CLOCK_EnableUsbfs0DeviceClock()
2687 … CLOCK_SetClkDiv(kCLOCK_DivUsb0Clk, 2, false); /*!< Div by 2 to get 48MHz, no divider reset */ in CLOCK_EnableUsbfs0HostClock()
2691 … CLOCK_SetClkDiv(kCLOCK_DivUsb0Clk, 1, false); /*!< Div by 1 to get 48MHz, no divider reset */ in CLOCK_EnableUsbfs0HostClock()
2712 CLOCK_SetClkDiv(kCLOCK_DivUsb0Clk, 1U, false); in CLOCK_EnableUsbfs0HostClock()
|
| /hal_nxp-latest/mcux/mcux-sdk/devices/LPC54607/drivers/ |
| D | fsl_clock.c | 2634 … CLOCK_SetClkDiv(kCLOCK_DivUsb0Clk, 2, false); /*!< Div by 2 to get 48MHz, no divider reset */ in CLOCK_EnableUsbfs0DeviceClock()
2638 … CLOCK_SetClkDiv(kCLOCK_DivUsb0Clk, 1, false); /*!< Div by 1 to get 48MHz, no divider reset */ in CLOCK_EnableUsbfs0DeviceClock()
2659 CLOCK_SetClkDiv(kCLOCK_DivUsb0Clk, 1U, false); in CLOCK_EnableUsbfs0DeviceClock()
2687 … CLOCK_SetClkDiv(kCLOCK_DivUsb0Clk, 2, false); /*!< Div by 2 to get 48MHz, no divider reset */ in CLOCK_EnableUsbfs0HostClock()
2691 … CLOCK_SetClkDiv(kCLOCK_DivUsb0Clk, 1, false); /*!< Div by 1 to get 48MHz, no divider reset */ in CLOCK_EnableUsbfs0HostClock()
2712 CLOCK_SetClkDiv(kCLOCK_DivUsb0Clk, 1U, false); in CLOCK_EnableUsbfs0HostClock()
|
| /hal_nxp-latest/mcux/mcux-sdk/devices/LPC54608/drivers/ |
| D | fsl_clock.c | 2634 … CLOCK_SetClkDiv(kCLOCK_DivUsb0Clk, 2, false); /*!< Div by 2 to get 48MHz, no divider reset */ in CLOCK_EnableUsbfs0DeviceClock()
2638 … CLOCK_SetClkDiv(kCLOCK_DivUsb0Clk, 1, false); /*!< Div by 1 to get 48MHz, no divider reset */ in CLOCK_EnableUsbfs0DeviceClock()
2659 CLOCK_SetClkDiv(kCLOCK_DivUsb0Clk, 1U, false); in CLOCK_EnableUsbfs0DeviceClock()
2687 … CLOCK_SetClkDiv(kCLOCK_DivUsb0Clk, 2, false); /*!< Div by 2 to get 48MHz, no divider reset */ in CLOCK_EnableUsbfs0HostClock()
2691 … CLOCK_SetClkDiv(kCLOCK_DivUsb0Clk, 1, false); /*!< Div by 1 to get 48MHz, no divider reset */ in CLOCK_EnableUsbfs0HostClock()
2712 CLOCK_SetClkDiv(kCLOCK_DivUsb0Clk, 1U, false); in CLOCK_EnableUsbfs0HostClock()
|
| /hal_nxp-latest/mcux/mcux-sdk/devices/LPC54016/drivers/ |
| D | fsl_clock.c | 2624 … CLOCK_SetClkDiv(kCLOCK_DivUsb0Clk, 2U, false); /*!< Div by 2 to get 48MHz, no divider reset */ in CLOCK_EnableUsbfs0DeviceClock()
2628 … CLOCK_SetClkDiv(kCLOCK_DivUsb0Clk, 1U, false); /*!< Div by 1 to get 48MHz, no divider reset */ in CLOCK_EnableUsbfs0DeviceClock()
2649 CLOCK_SetClkDiv(kCLOCK_DivUsb0Clk, 1U, false); in CLOCK_EnableUsbfs0DeviceClock()
2677 … CLOCK_SetClkDiv(kCLOCK_DivUsb0Clk, 2U, false); /*!< Div by 2 to get 48MHz, no divider reset */ in CLOCK_EnableUsbfs0HostClock()
2681 … CLOCK_SetClkDiv(kCLOCK_DivUsb0Clk, 1U, false); /*!< Div by 1 to get 48MHz, no divider reset */ in CLOCK_EnableUsbfs0HostClock()
2702 CLOCK_SetClkDiv(kCLOCK_DivUsb0Clk, 1U, false); in CLOCK_EnableUsbfs0HostClock()
|
| /hal_nxp-latest/mcux/mcux-sdk/devices/LPC54018/drivers/ |
| D | fsl_clock.c | 2632 … CLOCK_SetClkDiv(kCLOCK_DivUsb0Clk, 2U, false); /*!< Div by 2 to get 48MHz, no divider reset */ in CLOCK_EnableUsbfs0DeviceClock()
2636 … CLOCK_SetClkDiv(kCLOCK_DivUsb0Clk, 1U, false); /*!< Div by 1 to get 48MHz, no divider reset */ in CLOCK_EnableUsbfs0DeviceClock()
2657 CLOCK_SetClkDiv(kCLOCK_DivUsb0Clk, 1U, false); in CLOCK_EnableUsbfs0DeviceClock()
2685 … CLOCK_SetClkDiv(kCLOCK_DivUsb0Clk, 2U, false); /*!< Div by 2 to get 48MHz, no divider reset */ in CLOCK_EnableUsbfs0HostClock()
2689 … CLOCK_SetClkDiv(kCLOCK_DivUsb0Clk, 1U, false); /*!< Div by 1 to get 48MHz, no divider reset */ in CLOCK_EnableUsbfs0HostClock()
2710 CLOCK_SetClkDiv(kCLOCK_DivUsb0Clk, 1U, false); in CLOCK_EnableUsbfs0HostClock()
|
| /hal_nxp-latest/mcux/mcux-sdk/devices/LPC54018M/drivers/ |
| D | fsl_clock.c | 2624 … CLOCK_SetClkDiv(kCLOCK_DivUsb0Clk, 2U, false); /*!< Div by 2 to get 48MHz, no divider reset */ in CLOCK_EnableUsbfs0DeviceClock()
2628 … CLOCK_SetClkDiv(kCLOCK_DivUsb0Clk, 1U, false); /*!< Div by 1 to get 48MHz, no divider reset */ in CLOCK_EnableUsbfs0DeviceClock()
2649 CLOCK_SetClkDiv(kCLOCK_DivUsb0Clk, 1U, false); in CLOCK_EnableUsbfs0DeviceClock()
2677 … CLOCK_SetClkDiv(kCLOCK_DivUsb0Clk, 2U, false); /*!< Div by 2 to get 48MHz, no divider reset */ in CLOCK_EnableUsbfs0HostClock()
2681 … CLOCK_SetClkDiv(kCLOCK_DivUsb0Clk, 1U, false); /*!< Div by 1 to get 48MHz, no divider reset */ in CLOCK_EnableUsbfs0HostClock()
2702 CLOCK_SetClkDiv(kCLOCK_DivUsb0Clk, 1U, false); in CLOCK_EnableUsbfs0HostClock()
|
| /hal_nxp-latest/mcux/mcux-sdk/devices/LPC54005/drivers/ |
| D | fsl_clock.c | 2622 … CLOCK_SetClkDiv(kCLOCK_DivUsb0Clk, 2U, false); /*!< Div by 2 to get 48MHz, no divider reset */ in CLOCK_EnableUsbfs0DeviceClock()
2626 … CLOCK_SetClkDiv(kCLOCK_DivUsb0Clk, 1U, false); /*!< Div by 1 to get 48MHz, no divider reset */ in CLOCK_EnableUsbfs0DeviceClock()
2647 CLOCK_SetClkDiv(kCLOCK_DivUsb0Clk, 1U, false); in CLOCK_EnableUsbfs0DeviceClock()
2675 … CLOCK_SetClkDiv(kCLOCK_DivUsb0Clk, 2U, false); /*!< Div by 2 to get 48MHz, no divider reset */ in CLOCK_EnableUsbfs0HostClock()
2679 … CLOCK_SetClkDiv(kCLOCK_DivUsb0Clk, 1U, false); /*!< Div by 1 to get 48MHz, no divider reset */ in CLOCK_EnableUsbfs0HostClock()
2700 CLOCK_SetClkDiv(kCLOCK_DivUsb0Clk, 1U, false); in CLOCK_EnableUsbfs0HostClock()
|
| /hal_nxp-latest/mcux/mcux-sdk/devices/LPC54616/drivers/ |
| D | fsl_clock.c | 2613 … CLOCK_SetClkDiv(kCLOCK_DivUsb0Clk, 2, false); /*!< Div by 2 to get 48MHz, no divider reset */ in CLOCK_EnableUsbfs0DeviceClock()
2617 … CLOCK_SetClkDiv(kCLOCK_DivUsb0Clk, 1, false); /*!< Div by 1 to get 48MHz, no divider reset */ in CLOCK_EnableUsbfs0DeviceClock()
2638 CLOCK_SetClkDiv(kCLOCK_DivUsb0Clk, 1U, false); in CLOCK_EnableUsbfs0DeviceClock()
2666 … CLOCK_SetClkDiv(kCLOCK_DivUsb0Clk, 2, false); /*!< Div by 2 to get 48MHz, no divider reset */ in CLOCK_EnableUsbfs0HostClock()
2670 … CLOCK_SetClkDiv(kCLOCK_DivUsb0Clk, 1, false); /*!< Div by 1 to get 48MHz, no divider reset */ in CLOCK_EnableUsbfs0HostClock()
2691 CLOCK_SetClkDiv(kCLOCK_DivUsb0Clk, 1U, false); in CLOCK_EnableUsbfs0HostClock()
|
| /hal_nxp-latest/mcux/mcux-sdk/devices/LPC54S018M/drivers/ |
| D | fsl_clock.c | 2632 … CLOCK_SetClkDiv(kCLOCK_DivUsb0Clk, 2U, false); /*!< Div by 2 to get 48MHz, no divider reset */ in CLOCK_EnableUsbfs0DeviceClock()
2636 … CLOCK_SetClkDiv(kCLOCK_DivUsb0Clk, 1U, false); /*!< Div by 1 to get 48MHz, no divider reset */ in CLOCK_EnableUsbfs0DeviceClock()
2657 CLOCK_SetClkDiv(kCLOCK_DivUsb0Clk, 1U, false); in CLOCK_EnableUsbfs0DeviceClock()
2685 … CLOCK_SetClkDiv(kCLOCK_DivUsb0Clk, 2U, false); /*!< Div by 2 to get 48MHz, no divider reset */ in CLOCK_EnableUsbfs0HostClock()
2689 … CLOCK_SetClkDiv(kCLOCK_DivUsb0Clk, 1U, false); /*!< Div by 1 to get 48MHz, no divider reset */ in CLOCK_EnableUsbfs0HostClock()
2710 CLOCK_SetClkDiv(kCLOCK_DivUsb0Clk, 1U, false); in CLOCK_EnableUsbfs0HostClock()
|
| /hal_nxp-latest/mcux/mcux-sdk/devices/LPC55S66/drivers/ |
| D | fsl_clock.c | 1909 … CLOCK_SetClkDiv(kCLOCK_DivUsb0Clk, 2, false); /*!< Div by 2 to get 48MHz, no divider reset */ in CLOCK_EnableUsbfs0DeviceClock()
1945 CLOCK_SetClkDiv(kCLOCK_DivUsb0Clk, 1U, false); in CLOCK_EnableUsbfs0DeviceClock()
1973 … CLOCK_SetClkDiv(kCLOCK_DivUsb0Clk, 2, false); /*!< Div by 2 to get 48MHz, no divider reset */ in CLOCK_EnableUsbfs0HostClock()
2008 CLOCK_SetClkDiv(kCLOCK_DivUsb0Clk, 1U, false); in CLOCK_EnableUsbfs0HostClock()
|
| /hal_nxp-latest/mcux/mcux-sdk/devices/LPC5514/drivers/ |
| D | fsl_clock.c | 1993 … CLOCK_SetClkDiv(kCLOCK_DivUsb0Clk, 2, false); /*!< Div by 2 to get 48MHz, no divider reset */ in CLOCK_EnableUsbfs0DeviceClock()
2029 CLOCK_SetClkDiv(kCLOCK_DivUsb0Clk, 1U, false); in CLOCK_EnableUsbfs0DeviceClock()
2057 … CLOCK_SetClkDiv(kCLOCK_DivUsb0Clk, 2, false); /*!< Div by 2 to get 48MHz, no divider reset */ in CLOCK_EnableUsbfs0HostClock()
2092 CLOCK_SetClkDiv(kCLOCK_DivUsb0Clk, 1U, false); in CLOCK_EnableUsbfs0HostClock()
|
| /hal_nxp-latest/mcux/mcux-sdk/devices/LPC5516/drivers/ |
| D | fsl_clock.c | 1993 … CLOCK_SetClkDiv(kCLOCK_DivUsb0Clk, 2, false); /*!< Div by 2 to get 48MHz, no divider reset */ in CLOCK_EnableUsbfs0DeviceClock()
2029 CLOCK_SetClkDiv(kCLOCK_DivUsb0Clk, 1U, false); in CLOCK_EnableUsbfs0DeviceClock()
2057 … CLOCK_SetClkDiv(kCLOCK_DivUsb0Clk, 2, false); /*!< Div by 2 to get 48MHz, no divider reset */ in CLOCK_EnableUsbfs0HostClock()
2092 CLOCK_SetClkDiv(kCLOCK_DivUsb0Clk, 1U, false); in CLOCK_EnableUsbfs0HostClock()
|
| /hal_nxp-latest/mcux/mcux-sdk/devices/LPC5512/drivers/ |
| D | fsl_clock.c | 1993 … CLOCK_SetClkDiv(kCLOCK_DivUsb0Clk, 2, false); /*!< Div by 2 to get 48MHz, no divider reset */ in CLOCK_EnableUsbfs0DeviceClock()
2029 CLOCK_SetClkDiv(kCLOCK_DivUsb0Clk, 1U, false); in CLOCK_EnableUsbfs0DeviceClock()
2056 … CLOCK_SetClkDiv(kCLOCK_DivUsb0Clk, 2, false); /*!< Div by 2 to get 48MHz, no divider reset */ in CLOCK_EnableUsbfs0HostClock()
2091 CLOCK_SetClkDiv(kCLOCK_DivUsb0Clk, 1U, false); in CLOCK_EnableUsbfs0HostClock()
|
| /hal_nxp-latest/mcux/mcux-sdk/devices/LPC55S28/drivers/ |
| D | fsl_clock.c | 1909 … CLOCK_SetClkDiv(kCLOCK_DivUsb0Clk, 2, false); /*!< Div by 2 to get 48MHz, no divider reset */ in CLOCK_EnableUsbfs0DeviceClock()
1945 CLOCK_SetClkDiv(kCLOCK_DivUsb0Clk, 1U, false); in CLOCK_EnableUsbfs0DeviceClock()
1973 … CLOCK_SetClkDiv(kCLOCK_DivUsb0Clk, 2, false); /*!< Div by 2 to get 48MHz, no divider reset */ in CLOCK_EnableUsbfs0HostClock()
2008 CLOCK_SetClkDiv(kCLOCK_DivUsb0Clk, 1U, false); in CLOCK_EnableUsbfs0HostClock()
|
| /hal_nxp-latest/mcux/mcux-sdk/devices/LPC55S16/drivers/ |
| D | fsl_clock.c | 1993 … CLOCK_SetClkDiv(kCLOCK_DivUsb0Clk, 2, false); /*!< Div by 2 to get 48MHz, no divider reset */ in CLOCK_EnableUsbfs0DeviceClock()
2029 CLOCK_SetClkDiv(kCLOCK_DivUsb0Clk, 1U, false); in CLOCK_EnableUsbfs0DeviceClock()
2057 … CLOCK_SetClkDiv(kCLOCK_DivUsb0Clk, 2, false); /*!< Div by 2 to get 48MHz, no divider reset */ in CLOCK_EnableUsbfs0HostClock()
2092 CLOCK_SetClkDiv(kCLOCK_DivUsb0Clk, 1U, false); in CLOCK_EnableUsbfs0HostClock()
|
| /hal_nxp-latest/mcux/mcux-sdk/devices/LPC5526/drivers/ |
| D | fsl_clock.c | 1909 … CLOCK_SetClkDiv(kCLOCK_DivUsb0Clk, 2, false); /*!< Div by 2 to get 48MHz, no divider reset */ in CLOCK_EnableUsbfs0DeviceClock()
1945 CLOCK_SetClkDiv(kCLOCK_DivUsb0Clk, 1U, false); in CLOCK_EnableUsbfs0DeviceClock()
1973 … CLOCK_SetClkDiv(kCLOCK_DivUsb0Clk, 2, false); /*!< Div by 2 to get 48MHz, no divider reset */ in CLOCK_EnableUsbfs0HostClock()
2008 CLOCK_SetClkDiv(kCLOCK_DivUsb0Clk, 1U, false); in CLOCK_EnableUsbfs0HostClock()
|
| /hal_nxp-latest/mcux/mcux-sdk/devices/LPC5528/drivers/ |
| D | fsl_clock.c | 1909 … CLOCK_SetClkDiv(kCLOCK_DivUsb0Clk, 2, false); /*!< Div by 2 to get 48MHz, no divider reset */ in CLOCK_EnableUsbfs0DeviceClock()
1945 CLOCK_SetClkDiv(kCLOCK_DivUsb0Clk, 1U, false); in CLOCK_EnableUsbfs0DeviceClock()
1973 … CLOCK_SetClkDiv(kCLOCK_DivUsb0Clk, 2, false); /*!< Div by 2 to get 48MHz, no divider reset */ in CLOCK_EnableUsbfs0HostClock()
2008 CLOCK_SetClkDiv(kCLOCK_DivUsb0Clk, 1U, false); in CLOCK_EnableUsbfs0HostClock()
|
