Home
last modified time | relevance | path

Searched refs:kAI_PLL1G_CTRL1 (Results 1 – 14 of 14) sorted by relevance

/hal_nxp-latest/mcux/mcux-sdk/devices/MIMXRT1172/drivers/
Dfsl_anatop_ai.h86 kAI_PLL1G_CTRL1 = 0x10, /*!< 1G PLL CTRL1 Register. */ enumerator
Dfsl_clock.c60 #define PLL_AI_CTRL1_REG kAI_PLL1G_CTRL1
/hal_nxp-latest/mcux/mcux-sdk/devices/MIMXRT1165/drivers/
Dfsl_anatop_ai.h86 kAI_PLL1G_CTRL1 = 0x10, /*!< 1G PLL CTRL1 Register. */ enumerator
Dfsl_clock.c60 #define PLL_AI_CTRL1_REG kAI_PLL1G_CTRL1
/hal_nxp-latest/mcux/mcux-sdk/devices/MIMXRT1176/drivers/
Dfsl_anatop_ai.h86 kAI_PLL1G_CTRL1 = 0x10, /*!< 1G PLL CTRL1 Register. */ enumerator
Dfsl_clock.c60 #define PLL_AI_CTRL1_REG kAI_PLL1G_CTRL1
/hal_nxp-latest/mcux/mcux-sdk/devices/MIMXRT1173/drivers/
Dfsl_anatop_ai.h86 kAI_PLL1G_CTRL1 = 0x10, /*!< 1G PLL CTRL1 Register. */ enumerator
Dfsl_clock.c60 #define PLL_AI_CTRL1_REG kAI_PLL1G_CTRL1
/hal_nxp-latest/mcux/mcux-sdk/devices/MIMXRT1171/drivers/
Dfsl_anatop_ai.h86 kAI_PLL1G_CTRL1 = 0x10, /*!< 1G PLL CTRL1 Register. */ enumerator
Dfsl_clock.c60 #define PLL_AI_CTRL1_REG kAI_PLL1G_CTRL1
/hal_nxp-latest/mcux/mcux-sdk/devices/MIMXRT1166/drivers/
Dfsl_anatop_ai.h86 kAI_PLL1G_CTRL1 = 0x10, /*!< 1G PLL CTRL1 Register. */ enumerator
Dfsl_clock.c60 #define PLL_AI_CTRL1_REG kAI_PLL1G_CTRL1
/hal_nxp-latest/mcux/mcux-sdk/devices/MIMXRT1175/drivers/
Dfsl_anatop_ai.h86 kAI_PLL1G_CTRL1 = 0x10, /*!< 1G PLL CTRL1 Register. */ enumerator
Dfsl_clock.c60 #define PLL_AI_CTRL1_REG kAI_PLL1G_CTRL1