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Searched refs:kAI_PLL1G_CTRL0_SET (Results 1 – 14 of 14) sorted by relevance

/hal_nxp-latest/mcux/mcux-sdk/devices/MIMXRT1172/drivers/
Dfsl_anatop_ai.h84 kAI_PLL1G_CTRL0_SET = 0x4, /*!< 1G PLL CTRL0 SET Register. */ enumerator
Dfsl_clock.c58 #define PLL_AI_CTRL0_SET_REG kAI_PLL1G_CTRL0_SET
/hal_nxp-latest/mcux/mcux-sdk/devices/MIMXRT1165/drivers/
Dfsl_anatop_ai.h84 kAI_PLL1G_CTRL0_SET = 0x4, /*!< 1G PLL CTRL0 SET Register. */ enumerator
Dfsl_clock.c58 #define PLL_AI_CTRL0_SET_REG kAI_PLL1G_CTRL0_SET
/hal_nxp-latest/mcux/mcux-sdk/devices/MIMXRT1176/drivers/
Dfsl_anatop_ai.h84 kAI_PLL1G_CTRL0_SET = 0x4, /*!< 1G PLL CTRL0 SET Register. */ enumerator
Dfsl_clock.c58 #define PLL_AI_CTRL0_SET_REG kAI_PLL1G_CTRL0_SET
/hal_nxp-latest/mcux/mcux-sdk/devices/MIMXRT1173/drivers/
Dfsl_anatop_ai.h84 kAI_PLL1G_CTRL0_SET = 0x4, /*!< 1G PLL CTRL0 SET Register. */ enumerator
Dfsl_clock.c58 #define PLL_AI_CTRL0_SET_REG kAI_PLL1G_CTRL0_SET
/hal_nxp-latest/mcux/mcux-sdk/devices/MIMXRT1171/drivers/
Dfsl_anatop_ai.h84 kAI_PLL1G_CTRL0_SET = 0x4, /*!< 1G PLL CTRL0 SET Register. */ enumerator
Dfsl_clock.c58 #define PLL_AI_CTRL0_SET_REG kAI_PLL1G_CTRL0_SET
/hal_nxp-latest/mcux/mcux-sdk/devices/MIMXRT1166/drivers/
Dfsl_anatop_ai.h84 kAI_PLL1G_CTRL0_SET = 0x4, /*!< 1G PLL CTRL0 SET Register. */ enumerator
Dfsl_clock.c58 #define PLL_AI_CTRL0_SET_REG kAI_PLL1G_CTRL0_SET
/hal_nxp-latest/mcux/mcux-sdk/devices/MIMXRT1175/drivers/
Dfsl_anatop_ai.h84 kAI_PLL1G_CTRL0_SET = 0x4, /*!< 1G PLL CTRL0 SET Register. */ enumerator
Dfsl_clock.c58 #define PLL_AI_CTRL0_SET_REG kAI_PLL1G_CTRL0_SET