1 /* 2 * Copyright 1997-2016 Freescale Semiconductor, Inc. 3 * Copyright 2016-2024 NXP 4 * 5 * SPDX-License-Identifier: BSD-3-Clause 6 */ 7 8 /*! 9 * @file S32Z2_ierc_ierb.h 10 * @version 2.3 11 * @date 2024-05-03 12 * @brief Peripheral Access Layer for S32Z2_ierc_ierb 13 * 14 * This file contains register definitions and macros for easy access to their 15 * bit fields. 16 * 17 * This file assumes LITTLE endian system. 18 */ 19 20 /** 21 * @page misra_violations MISRA-C:2012 violations 22 * 23 * @section [global] 24 * Violates MISRA 2012 Advisory Rule 2.3, local typedef not referenced 25 * The SoC header defines typedef for all modules. 26 * 27 * @section [global] 28 * Violates MISRA 2012 Advisory Rule 2.5, local macro not referenced 29 * The SoC header defines macros for all modules and registers. 30 * 31 * @section [global] 32 * Violates MISRA 2012 Advisory Directive 4.9, Function-like macro 33 * These are generated macros used for accessing the bit-fields from registers. 34 * 35 * @section [global] 36 * Violates MISRA 2012 Required Rule 5.1, identifier clash 37 * The supported compilers use more than 31 significant characters for identifiers. 38 * 39 * @section [global] 40 * Violates MISRA 2012 Required Rule 5.2, identifier clash 41 * The supported compilers use more than 31 significant characters for identifiers. 42 * 43 * @section [global] 44 * Violates MISRA 2012 Required Rule 5.4, identifier clash 45 * The supported compilers use more than 31 significant characters for identifiers. 46 * 47 * @section [global] 48 * Violates MISRA 2012 Required Rule 5.5, identifier clash 49 * The supported compilers use more than 31 significant characters for identifiers. 50 * 51 * @section [global] 52 * Violates MISRA 2012 Required Rule 21.1, defined macro '__I' is reserved to the compiler 53 * This type qualifier is needed to ensure correct I/O access and addressing. 54 */ 55 56 /* Prevention from multiple including the same memory map */ 57 #if !defined(S32Z2_ierc_ierb_H_) /* Check if memory map has not been already included */ 58 #define S32Z2_ierc_ierb_H_ 59 60 #include "S32Z2_COMMON.h" 61 62 /* ---------------------------------------------------------------------------- 63 -- ierc_ierb Peripheral Access Layer 64 ---------------------------------------------------------------------------- */ 65 66 /*! 67 * @addtogroup ierc_ierb_Peripheral_Access_Layer ierc_ierb Peripheral Access Layer 68 * @{ 69 */ 70 71 /** ierc_ierb - Register Layout Typedef */ 72 typedef struct { 73 __IO uint32_t F0_EC_CFH_DIDVID; /**< Function 0 EC config header device ID and vendor ID register, offset: 0x0 */ 74 __IO uint32_t F0_EC_CFH_SIDSVID; /**< Function 0 EC config header subsystem ID and subsystem vendor ID register, offset: 0x4 */ 75 } ierc_ierb_Type, *ierc_ierb_MemMapPtr; 76 77 /** Number of instances of the ierc_ierb module. */ 78 #define ierc_ierb_INSTANCE_COUNT (1u) 79 80 /* ierc_ierb - Peripheral instance base addresses */ 81 /** Peripheral NETC__IERC_IERB base address */ 82 #define IP_NETC__IERC_IERB_BASE (0x74810000u) 83 /** Peripheral NETC__IERC_IERB base pointer */ 84 #define IP_NETC__IERC_IERB ((ierc_ierb_Type *)IP_NETC__IERC_IERB_BASE) 85 /** Array initializer of ierc_ierb peripheral base addresses */ 86 #define IP_ierc_ierb_BASE_ADDRS { IP_NETC__IERC_IERB_BASE } 87 /** Array initializer of ierc_ierb peripheral base pointers */ 88 #define IP_ierc_ierb_BASE_PTRS { IP_NETC__IERC_IERB } 89 90 /* ---------------------------------------------------------------------------- 91 -- ierc_ierb Register Masks 92 ---------------------------------------------------------------------------- */ 93 94 /*! 95 * @addtogroup ierc_ierb_Register_Masks ierc_ierb Register Masks 96 * @{ 97 */ 98 99 /*! @name F0_EC_CFH_DIDVID - Function 0 EC config header device ID and vendor ID register */ 100 /*! @{ */ 101 102 #define ierc_ierb_F0_EC_CFH_DIDVID_VENDOR_ID_MASK (0xFFFFU) 103 #define ierc_ierb_F0_EC_CFH_DIDVID_VENDOR_ID_SHIFT (0U) 104 #define ierc_ierb_F0_EC_CFH_DIDVID_VENDOR_ID_WIDTH (16U) 105 #define ierc_ierb_F0_EC_CFH_DIDVID_VENDOR_ID(x) (((uint32_t)(((uint32_t)(x)) << ierc_ierb_F0_EC_CFH_DIDVID_VENDOR_ID_SHIFT)) & ierc_ierb_F0_EC_CFH_DIDVID_VENDOR_ID_MASK) 106 107 #define ierc_ierb_F0_EC_CFH_DIDVID_DEVICE_ID_MASK (0xFFFF0000U) 108 #define ierc_ierb_F0_EC_CFH_DIDVID_DEVICE_ID_SHIFT (16U) 109 #define ierc_ierb_F0_EC_CFH_DIDVID_DEVICE_ID_WIDTH (16U) 110 #define ierc_ierb_F0_EC_CFH_DIDVID_DEVICE_ID(x) (((uint32_t)(((uint32_t)(x)) << ierc_ierb_F0_EC_CFH_DIDVID_DEVICE_ID_SHIFT)) & ierc_ierb_F0_EC_CFH_DIDVID_DEVICE_ID_MASK) 111 /*! @} */ 112 113 /*! @name F0_EC_CFH_SIDSVID - Function 0 EC config header subsystem ID and subsystem vendor ID register */ 114 /*! @{ */ 115 116 #define ierc_ierb_F0_EC_CFH_SIDSVID_SUBSYSTEM_VENDOR_ID_MASK (0xFFFFU) 117 #define ierc_ierb_F0_EC_CFH_SIDSVID_SUBSYSTEM_VENDOR_ID_SHIFT (0U) 118 #define ierc_ierb_F0_EC_CFH_SIDSVID_SUBSYSTEM_VENDOR_ID_WIDTH (16U) 119 #define ierc_ierb_F0_EC_CFH_SIDSVID_SUBSYSTEM_VENDOR_ID(x) (((uint32_t)(((uint32_t)(x)) << ierc_ierb_F0_EC_CFH_SIDSVID_SUBSYSTEM_VENDOR_ID_SHIFT)) & ierc_ierb_F0_EC_CFH_SIDSVID_SUBSYSTEM_VENDOR_ID_MASK) 120 121 #define ierc_ierb_F0_EC_CFH_SIDSVID_SUBSYSTEM_DEVICE_ID_MASK (0xFFFF0000U) 122 #define ierc_ierb_F0_EC_CFH_SIDSVID_SUBSYSTEM_DEVICE_ID_SHIFT (16U) 123 #define ierc_ierb_F0_EC_CFH_SIDSVID_SUBSYSTEM_DEVICE_ID_WIDTH (16U) 124 #define ierc_ierb_F0_EC_CFH_SIDSVID_SUBSYSTEM_DEVICE_ID(x) (((uint32_t)(((uint32_t)(x)) << ierc_ierb_F0_EC_CFH_SIDSVID_SUBSYSTEM_DEVICE_ID_SHIFT)) & ierc_ierb_F0_EC_CFH_SIDSVID_SUBSYSTEM_DEVICE_ID_MASK) 125 /*! @} */ 126 127 /*! 128 * @} 129 */ /* end of group ierc_ierb_Register_Masks */ 130 131 /*! 132 * @} 133 */ /* end of group ierc_ierb_Peripheral_Access_Layer */ 134 135 #endif /* #if !defined(S32Z2_ierc_ierb_H_) */ 136
