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/hal_nxp-latest/s32/drivers/s32ze/Can_CANEXCEL/src/
DCanEXCEL_Ip_HwAccess.c704 void CanXL_ConfigAccAddr(CANXL_RXFIFO_Type * base,const Canexcel_Ip_RxFifoFilterID_ADDR * filter, u… in CanXL_ConfigAccAddr() argument
707 if (CANEXCEL_IP_RX_FIFO_RANGE_FILTER == filter->filterType) in CanXL_ConfigAccAddr()
716 base->ADDRACPTFLTAR[filtIdx].AAFLTH = filter->idAddrFilterH; in CanXL_ConfigAccAddr()
717 base->ADDRACPTFLTAR[filtIdx].AAFLTL = filter->idAddrFilterL; in CanXL_ConfigAccAddr()
724 void CanXL_ConfigIDFilter(CANXL_RXFIFO_Type * base,const Canexcel_Ip_RxFifoFilterID_ADDR * filter, … in CanXL_ConfigIDFilter() argument
727 if (CANEXCEL_IP_RX_FIFO_RANGE_FILTER == filter->filterType) in CanXL_ConfigIDFilter()
736 base->IDACPTFLTAR[filtIdx].IDAFLTH = filter->idAddrFilterH; in CanXL_ConfigIDFilter()
737 base->IDACPTFLTAR[filtIdx].IDAFLTL = filter->idAddrFilterL; in CanXL_ConfigIDFilter()
744 void CanXL_ConfigSDUFilter(CANXL_RXFIFO_Type * base,const Canexcel_Ip_RxFifoFilterSDU_CAN * filter,… in CanXL_ConfigSDUFilter() argument
747 if (CANEXCEL_IP_RX_FIFO_RANGE_FILTER == filter->filterType) in CanXL_ConfigSDUFilter()
[all …]
/hal_nxp-latest/mcux/mcux-sdk/drivers/snvs_lp/
Dfsl_snvs_lp.c545 config->filter = 0U; in SNVS_LP_PassiveTamperPin_GetDefaultConfig()
592 config->filter = 0U; in SNVS_LP_TamperPinRx_GetDefaultConfig()
625 SNVS->LPTGFCR |= SNVS_LPTGFCR_ETGF1(config.filter); in SNVS_LP_EnablePassiveTamper()
644 SNVS->LPTGFCR |= SNVS_LPTGFCR_ETGF2(config.filter); in SNVS_LP_EnablePassiveTamper()
663 SNVS->LPTGF1CR |= SNVS_LPTGF1CR_ETGF3(config.filter); in SNVS_LP_EnablePassiveTamper()
678 SNVS->LPTGF1CR |= SNVS_LPTGF1CR_ETGF4(config.filter); in SNVS_LP_EnablePassiveTamper()
693 SNVS->LPTGF1CR |= SNVS_LPTGF1CR_ETGF5(config.filter); in SNVS_LP_EnablePassiveTamper()
708 SNVS->LPTGF1CR |= SNVS_LPTGF1CR_ETGF6(config.filter); in SNVS_LP_EnablePassiveTamper()
723 SNVS->LPTGF2CR |= SNVS_LPTGF2CR_ETGF7(config.filter); in SNVS_LP_EnablePassiveTamper()
738 SNVS->LPTGF2CR |= SNVS_LPTGF2CR_ETGF8(config.filter); in SNVS_LP_EnablePassiveTamper()
[all …]
Dfsl_snvs_lp.h96 uint8_t filter; member
108 uint8_t filter; member
/hal_nxp-latest/s32/drivers/s32ze/Can_CANEXCEL/include/
DCanEXCEL_Ip_HwAccess.h674 void CanXL_ConfigAccAddr(CANXL_RXFIFO_Type * base,const Canexcel_Ip_RxFifoFilterID_ADDR * filter, u…
682 void CanXL_ConfigIDFilter(CANXL_RXFIFO_Type * base,const Canexcel_Ip_RxFifoFilterID_ADDR * filter, …
690 void CanXL_ConfigSDUFilter(CANXL_RXFIFO_Type * base,const Canexcel_Ip_RxFifoFilterSDU_CAN * filter,…
698 void CanXL_ConfigVCANFilter(CANXL_RXFIFO_Type * base,const Canexcel_Ip_RxFifoFilterSDU_CAN * filter…
707 …FILTER_BANK_Type * base, uint8 bank,const Canexcel_Ip_RxFifoFilterID_ADDR * filter, uint8 filtIdx);
716 …FILTER_BANK_Type * base, uint8 bank,const Canexcel_Ip_RxFifoFilterSDU_CAN * filter, uint8 filtIdx);
725 …FILTER_BANK_Type * base, uint8 bank,const Canexcel_Ip_RxFifoFilterSDU_CAN * filter, uint8 filtIdx);
734 …FILTER_BANK_Type * base, uint8 bank,const Canexcel_Ip_RxFifoFilterID_ADDR * filter, uint8 filtIdx);
743 …FILTER_BANK_Type * base, uint8 bank,const Canexcel_Ip_RxFifoFilterSDU_CAN * filter, uint8 filtIdx);
752 …FILTER_BANK_Type * base, uint8 bank,const Canexcel_Ip_RxFifoFilterSDU_CAN * filter, uint8 filtIdx);
/hal_nxp-latest/mcux/mcux-sdk/CMSIS/NN/Source/ConvolutionFunctions/
Darm_depthwise_conv_wrapper_s8.c55 const q7_t *filter, in arm_depthwise_conv_wrapper_s8() argument
73 filter, in arm_depthwise_conv_wrapper_s8()
88 filter, in arm_depthwise_conv_wrapper_s8()
103 filter, in arm_depthwise_conv_wrapper_s8()
/hal_nxp-latest/mcux/mcux-sdk/devices/MKE06Z4/drivers/
Dfsl_port.c97 void PORT_SetFilterSelect(PORT_Type *base, port_filter_pin_t port, port_filter_select_t filter) in PORT_SetFilterSelect() argument
107 base->IOFLT0 = ((uint32_t)filter << (uint32_t)port) | fltReg; in PORT_SetFilterSelect()
115 base->IOFLT1 = ((uint32_t)filter << temp) | fltReg; in PORT_SetFilterSelect()
Dfsl_port.h263 void PORT_SetFilterSelect(PORT_Type *base, port_filter_pin_t port, port_filter_select_t filter);
/hal_nxp-latest/mcux/mcux-sdk/devices/MKE04Z1284/drivers/
Dfsl_port.c97 void PORT_SetFilterSelect(PORT_Type *base, port_filter_pin_t port, port_filter_select_t filter) in PORT_SetFilterSelect() argument
106 base->IOFLT0 = ((uint32_t)filter << (uint32_t)port) | fltReg; in PORT_SetFilterSelect()
116 base->IOFLT1 = ((uint32_t)filter << port_unsigned) | fltReg; in PORT_SetFilterSelect()
Dfsl_port.h263 void PORT_SetFilterSelect(PORT_Type *base, port_filter_pin_t port, port_filter_select_t filter);
/hal_nxp-latest/mcux/mcux-sdk/components/video/display/it6161/
Dhdmi_tx.c1487 uint8_t filter = 0; /* filter is for Video CTRL DN_FREE_GO,EN_DITHER,and ENUDFILT */ in HDMITX_SetupCsc() local
1514 filter |= HDMI_TX_INPUT_DATA_FORMAT_REG72_Reg_EN_UDFILTER_MASK; in HDMITX_SetupCsc()
1523 filter |= HDMI_TX_INPUT_DATA_FORMAT_REG72_Reg_EN_DITHER_MASK | in HDMITX_SetupCsc()
1537 filter |= HDMI_TX_INPUT_DATA_FORMAT_REG72_Reg_EN_UDFILTER_MASK; in HDMITX_SetupCsc()
1541 filter |= HDMI_TX_INPUT_DATA_FORMAT_REG72_Reg_EN_DITHER_MASK | in HDMITX_SetupCsc()
1552 filter |= HDMI_TX_INPUT_DATA_FORMAT_REG72_Reg_EN_UDFILTER_MASK; in HDMITX_SetupCsc()
1556 filter |= HDMI_TX_INPUT_DATA_FORMAT_REG72_Reg_EN_DITHER_MASK | in HDMITX_SetupCsc()
1570 filter |= HDMI_TX_INPUT_DATA_FORMAT_REG72_Reg_EN_DITHER_MASK | in HDMITX_SetupCsc()
1577 filter |= HDMI_TX_INPUT_DATA_FORMAT_REG72_Reg_EN_UDFILTER_MASK; in HDMITX_SetupCsc()
1581 filter |= HDMI_TX_INPUT_DATA_FORMAT_REG72_Reg_EN_DITHER_MASK | in HDMITX_SetupCsc()
[all …]
/hal_nxp-latest/mcux/mcux-sdk/drivers/tsi/
Dfsl_tsi_v4.h228 tsi_filter_bits_t filter; /*!< Noise mode filter bits */ member
676 static inline void TSI_SetFilterBits(TSI_Type *base, tsi_filter_bits_t filter) in TSI_SetFilterBits() argument
679 …((base->GENCS & TSI_V4_EXTCHRG_FILTER_BITS_CLEAR) | (((uint32_t)filter) << TSI_V4_EXTCHRG_FILTER_B… in TSI_SetFilterBits()
Dfsl_tsi_v4.c67 TSI_SetFilterBits(base, config->filter); in TSI_Init()
/hal_nxp-latest/mcux/mcux-sdk/drivers/tsi/tsi_v4/
Dfsl_tsi_v4.h228 tsi_filter_bits_t filter; /*!< Noise mode filter bits */ member
676 static inline void TSI_SetFilterBits(TSI_Type *base, tsi_filter_bits_t filter) in TSI_SetFilterBits() argument
679 …((base->GENCS & TSI_V4_EXTCHRG_FILTER_BITS_CLEAR) | (((uint32_t)filter) << TSI_V4_EXTCHRG_FILTER_B… in TSI_SetFilterBits()
Dfsl_tsi_v4.c67 TSI_SetFilterBits(base, config->filter); in TSI_Init()
/hal_nxp-latest/mcux/mcux-sdk/devices/MKE04Z4/drivers/
Dfsl_port.h186 …ine void PORT_SetFilterSelect(PORT_Type *base, port_filter_pin_t port, port_filter_select_t filter) in PORT_SetFilterSelect() argument
193 base->IOFLT = ((uint32_t)filter << (uint32_t)port) | fltReg; in PORT_SetFilterSelect()
/hal_nxp-latest/mcux/mcux-sdk/devices/MKE02Z4/drivers/
Dfsl_port.h195 …ine void PORT_SetFilterSelect(PORT_Type *base, port_filter_pin_t port, port_filter_select_t filter) in PORT_SetFilterSelect() argument
202 base->IOFLT = ((uint32_t)filter << (uint32_t)port) | fltReg; in PORT_SetFilterSelect()
/hal_nxp-latest/mcux/mcux-sdk/components/codec/tfa9xxx/vas_tfa_drv/
Dtfa9xxx_parameters.h269 nxpTfaFilter_t filter[TFA98XX_MAX_EQ]; member
299 nxpTfaFilter_t filter[TFA98XX_MAX_EQ]; // note: API index counts from 1..10 member
Dtfa2_container.h223 int tfa2_cont_write_filterbank(struct tfa2_device *tfa, nxpTfaFilter_t *filter);
/hal_nxp-latest/mcux/mcux-sdk/CMSIS/NN/
DREADME.md16 Core loop | No input or filter offset | Input and/or filter offset |
/hal_nxp-latest/mcux/mcux-sdk/components/codec/tfa9896/
Dfsl_hal_registers.c489 status_t TFA9896_Write_FilterBank(tfa9896_handle_t *handle, tfa9896FilterM_t *filter) in TFA9896_Write_FilterBank() argument
495 if (filter[biquad_index].enabled) in TFA9896_Write_FilterBank()
498 …error = TFA9896_DspSetParam(handle, 2, biquad_index + 1, sizeof(filter[biquad_index].biquad.bytes), in TFA9896_Write_FilterBank()
499 filter[biquad_index].biquad.bytes); in TFA9896_Write_FilterBank()
Dfsl_tfa9896.h470 status_t TFA9896_Write_FilterBank(tfa9896_handle_t *handle, tfa9896FilterM_t *filter);
/hal_nxp-latest/mcux/mcux-sdk/drivers/mcan/
Dfsl_mcan.h794 const mcan_std_filter_element_config_t *filter,
807 const mcan_ext_filter_element_config_t *filter,
Dfsl_mcan.c1491 const mcan_std_filter_element_config_t *filter, in MCAN_SetSTDFilterElement() argument
1496 …(void)memcpy((void *)elementAddress, (const void *)filter, sizeof(mcan_std_filter_element_config_t… in MCAN_SetSTDFilterElement()
1509 const mcan_ext_filter_element_config_t *filter, in MCAN_SetEXTFilterElement() argument
1514 …(void)memcpy((void *)elementAddress, (const void *)filter, sizeof(mcan_ext_filter_element_config_t… in MCAN_SetEXTFilterElement()
/hal_nxp-latest/mcux/scripts/pinctrl/kinetis/
Dkinetis_cfg_utils.py505 port_pins = list(filter(lambda p: (p.get_port().lower() == which_port), pins))
553 pcr_pins = list(filter(lambda p: (p.get_periph() not in ["FB", "EZPORT"]), pinmux_opts))
/hal_nxp-latest/mcux/middleware/wifi_nxp/wifidriver/
Dwifi-uap.c4291 sys_config->filter.mac_count = params->num_mac_acl; in wifi_nxp_set_acl()
4293 sys_config->filter.mac_count = MAX_MAC_FILTER_NUM; in wifi_nxp_set_acl()
4296 sys_config->filter.filter_mode = MAC_FILTER_MODE_ALLOW_MAC; in wifi_nxp_set_acl()
4298 sys_config->filter.filter_mode = MAC_FILTER_MODE_BLOCK_MAC; in wifi_nxp_set_acl()
4299 …memcpy(sys_config->filter.mac_list, params->mac_acl, sys_config->filter.mac_count * sizeof(mlan_80… in wifi_nxp_set_acl()

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