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/hal_nxp-latest/mcux/mcux-sdk/boards/evkmcimx7ulp/
Dclock_config.c116 .divBus = kSCG_SysClkDivBy1, /* Bus clock divider. */
133 .divBus = kSCG_SysClkDivBy2, /* Bus clock divider. */
151 .divBus = kSCG_SysClkDivBy4, /* Bus clock divider. */
167 .divBus = kSCG_SysClkDivBy2, /* Bus clock divider. */
183 .divBus = kSCG_SysClkDivBy1, /* Bus clock divider. */
/hal_nxp-latest/mcux/mcux-sdk/boards/evkmimx8ulp/
Dclock_config.c93 .divBus = 1, /* Bus clock divider. */
145 .divBus = 1, /* Bus clock divider. */
150 .divBus = 1, /* Bus clock divider. */
155 .divBus = 1, /* Bus clock divider. */
372 tmp_sys_clk_cfg.divBus = *bus_clk_divider - 1; in BOARD_CalculateCoreClkDivider()
411 g_sysClkConfigFroSource.divBus = bus_clk_divider - 1; in BOARD_SwitchToFROClk()
902 g_sysClkConfigRun.divBus = bus_clk_divider - 1; in BOARD_SwitchDriveMode()
/hal_nxp-latest/mcux/mcux-sdk/boards/twrke18f/
Dclock_config.c77 .divBus = kSCG_SysClkDivBy1, /* Bus clock divider */ in CLOCK_CONFIG_FircSafeConfig()
160 .divBus = kSCG_SysClkDivBy2, /* Bus Clock Divider: divided by 2 */
272 .divBus = kSCG_SysClkDivBy2, /* Bus Clock Divider: divided by 2 */
392 .divBus = kSCG_SysClkDivBy2, /* Bus Clock Divider: divided by 2 */
/hal_nxp-latest/mcux/mcux-sdk/boards/frdmk32l3a6/
Dclock_config.c141 .divBus = kSCG_SysClkDivBy1, /* Bus Clock Divider: divided by 1 */
241 .divBus = kSCG_SysClkDivBy1, /* Bus Clock Divider: divided by 1 */
349 .divBus = kSCG_SysClkDivBy2, /* Bus Clock Divider: divided by 2 */
/hal_nxp-latest/mcux/mcux-sdk/devices/MIMX8UD7/drivers/
Dfsl_clock.h1180 …uint32_t divBus : 6; /*!< Bus clock divider, selected division is the value of the field + 1. */ member
1208 …uint32_t divBus : 6; /*!< Platform clock divider, selected division is the value of the field +… member
1738 assert(config->divSlow > config->divBus); in CLOCK_SetCm33SysClkConfig()
1739 assert((config->divSlow + 1U) % (config->divBus + 1U) == 0U); in CLOCK_SetCm33SysClkConfig()
1766 assert(config->divSlow > config->divBus); in CLOCK_SetFusionSysClkConfig()
1767 assert((config->divSlow + 1U) % (config->divBus + 1U) == 0U); in CLOCK_SetFusionSysClkConfig()
1900 assert((config->divBus + 1U) % (config->divAhb + 1U) == 0U); in CLOCK_SetLpavSysClkConfig()
/hal_nxp-latest/mcux/mcux-sdk/devices/MIMX8US5/drivers/
Dfsl_clock.h1180 …uint32_t divBus : 6; /*!< Bus clock divider, selected division is the value of the field + 1. */ member
1208 …uint32_t divBus : 6; /*!< Platform clock divider, selected division is the value of the field +… member
1738 assert(config->divSlow > config->divBus); in CLOCK_SetCm33SysClkConfig()
1739 assert((config->divSlow + 1U) % (config->divBus + 1U) == 0U); in CLOCK_SetCm33SysClkConfig()
1766 assert(config->divSlow > config->divBus); in CLOCK_SetFusionSysClkConfig()
1767 assert((config->divSlow + 1U) % (config->divBus + 1U) == 0U); in CLOCK_SetFusionSysClkConfig()
1900 assert((config->divBus + 1U) % (config->divAhb + 1U) == 0U); in CLOCK_SetLpavSysClkConfig()
/hal_nxp-latest/mcux/mcux-sdk/devices/MIMX8UD5/drivers/
Dfsl_clock.h1180 …uint32_t divBus : 6; /*!< Bus clock divider, selected division is the value of the field + 1. */ member
1208 …uint32_t divBus : 6; /*!< Platform clock divider, selected division is the value of the field +… member
1738 assert(config->divSlow > config->divBus); in CLOCK_SetCm33SysClkConfig()
1739 assert((config->divSlow + 1U) % (config->divBus + 1U) == 0U); in CLOCK_SetCm33SysClkConfig()
1766 assert(config->divSlow > config->divBus); in CLOCK_SetFusionSysClkConfig()
1767 assert((config->divSlow + 1U) % (config->divBus + 1U) == 0U); in CLOCK_SetFusionSysClkConfig()
1900 assert((config->divBus + 1U) % (config->divAhb + 1U) == 0U); in CLOCK_SetLpavSysClkConfig()
/hal_nxp-latest/mcux/mcux-sdk/devices/MIMX8US3/drivers/
Dfsl_clock.h1180 …uint32_t divBus : 6; /*!< Bus clock divider, selected division is the value of the field + 1. */ member
1208 …uint32_t divBus : 6; /*!< Platform clock divider, selected division is the value of the field +… member
1738 assert(config->divSlow > config->divBus); in CLOCK_SetCm33SysClkConfig()
1739 assert((config->divSlow + 1U) % (config->divBus + 1U) == 0U); in CLOCK_SetCm33SysClkConfig()
1766 assert(config->divSlow > config->divBus); in CLOCK_SetFusionSysClkConfig()
1767 assert((config->divSlow + 1U) % (config->divBus + 1U) == 0U); in CLOCK_SetFusionSysClkConfig()
1900 assert((config->divBus + 1U) % (config->divAhb + 1U) == 0U); in CLOCK_SetLpavSysClkConfig()
/hal_nxp-latest/mcux/mcux-sdk/devices/MIMX8UD3/drivers/
Dfsl_clock.h1180 …uint32_t divBus : 6; /*!< Bus clock divider, selected division is the value of the field + 1. */ member
1208 …uint32_t divBus : 6; /*!< Platform clock divider, selected division is the value of the field +… member
1738 assert(config->divSlow > config->divBus); in CLOCK_SetCm33SysClkConfig()
1739 assert((config->divSlow + 1U) % (config->divBus + 1U) == 0U); in CLOCK_SetCm33SysClkConfig()
1766 assert(config->divSlow > config->divBus); in CLOCK_SetFusionSysClkConfig()
1767 assert((config->divSlow + 1U) % (config->divBus + 1U) == 0U); in CLOCK_SetFusionSysClkConfig()
1900 assert((config->divBus + 1U) % (config->divAhb + 1U) == 0U); in CLOCK_SetLpavSysClkConfig()
/hal_nxp-latest/mcux/mcux-sdk/boards/k32w148evk/
Dclock_config.c161 .divBus = (uint32_t)kSCG_SysClkDivBy1, /* Bus Clock Divider: divided by 1 */
/hal_nxp-latest/mcux/mcux-sdk/boards/kw45b41zevk/
Dclock_config.c161 .divBus = (uint32_t)kSCG_SysClkDivBy1, /* Bus Clock Divider: divided by 1 */
/hal_nxp-latest/mcux/mcux-sdk/boards/kw45b41zloc/
Dclock_config.c161 .divBus = (uint32_t)kSCG_SysClkDivBy1, /* Bus Clock Divider: divided by 1 */
/hal_nxp-latest/mcux/mcux-sdk/boards/frdmmcxw71/
Dclock_config.c161 .divBus = (uint32_t)kSCG_SysClkDivBy1, /* Bus Clock Divider: divided by 1 */
/hal_nxp-latest/mcux/mcux-sdk/devices/MCXW727C/drivers/
Dfsl_clock.c296 freq /= (sysClkConfig.divBus + 1U); in CLOCK_GetSysClkFreq()
Dfsl_clock.h410 uint32_t divBus : 4; /*!< Bus clock divider, see @ref scg_sys_clk_div_t. */ member
/hal_nxp-latest/mcux/mcux-sdk/devices/MCXW716C/drivers/
Dfsl_clock.c295 freq /= (sysClkConfig.divBus + 1U); in CLOCK_GetSysClkFreq()
Dfsl_clock.h380 uint32_t divBus : 4; /*!< Bus clock divider, see @ref scg_sys_clk_div_t. */ member
/hal_nxp-latest/mcux/mcux-sdk/devices/MCXW716A/drivers/
Dfsl_clock.c295 freq /= (sysClkConfig.divBus + 1U); in CLOCK_GetSysClkFreq()
Dfsl_clock.h380 uint32_t divBus : 4; /*!< Bus clock divider, see @ref scg_sys_clk_div_t. */ member
/hal_nxp-latest/mcux/mcux-sdk/devices/K32L3A60/drivers/
Dfsl_clock.c355 freq /= (sysClkConfig.divBus + 1U); in CLOCK_GetSysClkFreq()
Dfsl_clock.h446 uint32_t divBus : 4; /*!< Bus clock divider, see @ref scg_sys_clk_div_t. */ member
/hal_nxp-latest/mcux/mcux-sdk/devices/MKE18F16/drivers/
Dfsl_clock.h386 uint32_t divBus : 4; /*!< Bus clock divider, see @ref scg_sys_clk_div_t. */ member
Dfsl_clock.c377 freq /= (sysClkConfig.divBus + 1U); in CLOCK_GetSysClkFreq()
/hal_nxp-latest/mcux/mcux-sdk/devices/MKE16F16/drivers/
Dfsl_clock.h386 uint32_t divBus : 4; /*!< Bus clock divider, see @ref scg_sys_clk_div_t. */ member
/hal_nxp-latest/mcux/mcux-sdk/devices/MKE14F16/drivers/
Dfsl_clock.h380 uint32_t divBus : 4; /*!< Bus clock divider, see @ref scg_sys_clk_div_t. */ member

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