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Searched refs:div3 (Results 1 – 13 of 13) sorted by relevance

/hal_nxp-latest/mcux/mcux-sdk/boards/frdmk32l2a4s/
Dclock_config.c89 .div3 = kSCG_AsyncClkDivBy2, in CLOCK_CONFIG_FircSafeConfig()
197 .div3 = kSCG_AsyncClkDivBy1, /* System OSC Clock Divider 3: divided by 1 */
205 .div3 = kSCG_AsyncClkDivBy2, /* Slow IRC Clock Divider 3: divided by 2 */
212 .div3 = kSCG_AsyncClkDivBy1, /* Fast IRC Clock Divider 3: divided by 1 */
221 ….div3 = kSCG_AsyncClkDisable, /* System PLL Clock Divider 3: Clock output is disabled …
328 .div3 = kSCG_AsyncClkDivBy1, /* System OSC Clock Divider 3: divided by 1 */
336 .div3 = kSCG_AsyncClkDivBy1, /* Slow IRC Clock Divider 3: divided by 1 */
343 .div3 = kSCG_AsyncClkDivBy1, /* Fast IRC Clock Divider 3: divided by 1 */
352 .div3 = kSCG_AsyncClkDivBy1, /* System PLL Clock Divider 3: divided by 1 */
444 ….div3 = kSCG_AsyncClkDisable, /* System OSC Clock Divider 3: Clock output is disabled …
[all …]
/hal_nxp-latest/mcux/mcux-sdk/boards/frdmk32l3a6/
Dclock_config.c151 .div3 = kSCG_AsyncClkDivBy1, /* Slow IRC Clock Divider 3: divided by 1 */
159 .div3 = kSCG_AsyncClkDivBy1, /* Fast IRC Clock Divider 3: divided by 1 */
168 ….div3 = kSCG_AsyncClkDisable, /* Low Power FLL Clock Divider 3: Clock output is disabl…
251 .div3 = kSCG_AsyncClkDivBy1, /* Slow IRC Clock Divider 3: divided by 1 */
259 .div3 = kSCG_AsyncClkDivBy1, /* Fast IRC Clock Divider 3: divided by 1 */
268 ….div3 = kSCG_AsyncClkDisable, /* Low Power FLL Clock Divider 3: Clock output is disabl…
359 .div3 = kSCG_AsyncClkDivBy1, /* Slow IRC Clock Divider 3: divided by 1 */
367 … .div3 = kSCG_AsyncClkDisable, /* Fast IRC Clock Divider 3: Clock output is disabled */
376 ….div3 = kSCG_AsyncClkDisable, /* Low Power FLL Clock Divider 3: Clock output is disabl…
/hal_nxp-latest/mcux/mcux-sdk/boards/evkmcimx7ulp/
Dclock_config.c36 .div3 = kSCG_AsyncClkDisable,
49 .div3 = kSCG_AsyncClkDisable,
62 .div3 = kSCG_AsyncClkDisable,
77 .div3 = kSCG_AsyncClkDisable,
94 .div3 = kSCG_AsyncClkDisable,
/hal_nxp-latest/mcux/mcux-sdk/devices/MCIMX7U3/drivers/
Dfsl_clock.h631 scg_async_clk_div_t div3; /*!< SOSCDIV3 value. */ member
661 scg_async_clk_div_t div3; /*!< SIRCDIV3 value. */ member
746 scg_async_clk_div_t div3; /*!< FIRCDIV3 value. */ member
789 scg_async_clk_div_t div3; /*!< SPLLDIV3 value. */ member
853 scg_async_clk_div_t div3; /*!< APLLDIV3 value. */ member
Dfsl_clock.c603 …V_SOSCDIV1(config->div1) | SCG_SOSCDIV_SOSCDIV2(config->div2) | SCG_SOSCDIV_SOSCDIV3(config->div3); in CLOCK_InitSysOsc()
754 …V_SIRCDIV1(config->div1) | SCG_SIRCDIV_SIRCDIV2(config->div2) | SCG_SIRCDIV_SIRCDIV3(config->div3); in CLOCK_InitSirc()
900 …V_FIRCDIV1(config->div1) | SCG_FIRCDIV_FIRCDIV2(config->div2) | SCG_FIRCDIV_FIRCDIV3(config->div3); in CLOCK_InitFirc()
1120 …V_APLLDIV1(config->div1) | SCG_APLLDIV_APLLDIV2(config->div2) | SCG_APLLDIV_APLLDIV3(config->div3); in CLOCK_InitAuxPll()
1426 …V_SPLLDIV1(config->div1) | SCG_SPLLDIV_SPLLDIV2(config->div2) | SCG_SPLLDIV_SPLLDIV3(config->div3); in CLOCK_InitSysPll()
/hal_nxp-latest/mcux/mcux-sdk/devices/MCIMX7U5/drivers/
Dfsl_clock.h631 scg_async_clk_div_t div3; /*!< SOSCDIV3 value. */ member
661 scg_async_clk_div_t div3; /*!< SIRCDIV3 value. */ member
746 scg_async_clk_div_t div3; /*!< FIRCDIV3 value. */ member
789 scg_async_clk_div_t div3; /*!< SPLLDIV3 value. */ member
853 scg_async_clk_div_t div3; /*!< APLLDIV3 value. */ member
Dfsl_clock.c603 …V_SOSCDIV1(config->div1) | SCG_SOSCDIV_SOSCDIV2(config->div2) | SCG_SOSCDIV_SOSCDIV3(config->div3); in CLOCK_InitSysOsc()
754 …V_SIRCDIV1(config->div1) | SCG_SIRCDIV_SIRCDIV2(config->div2) | SCG_SIRCDIV_SIRCDIV3(config->div3); in CLOCK_InitSirc()
900 …V_FIRCDIV1(config->div1) | SCG_FIRCDIV_FIRCDIV2(config->div2) | SCG_FIRCDIV_FIRCDIV3(config->div3); in CLOCK_InitFirc()
1120 …V_APLLDIV1(config->div1) | SCG_APLLDIV_APLLDIV2(config->div2) | SCG_APLLDIV_APLLDIV3(config->div3); in CLOCK_InitAuxPll()
1426 …V_SPLLDIV1(config->div1) | SCG_SPLLDIV_SPLLDIV2(config->div2) | SCG_SPLLDIV_SPLLDIV3(config->div3); in CLOCK_InitSysPll()
/hal_nxp-latest/mcux/mcux-sdk/devices/K32L2A41A/drivers/
Dfsl_clock.h463 scg_async_clk_div_t div3; /*!< SOSCDIV3 value. */ member
494 scg_async_clk_div_t div3; /*!< SIRCDIV3 value. */ member
579 scg_async_clk_div_t div3; /*!< FIRCDIV3 value. */ member
623 scg_async_clk_div_t div3; /*!< SPLLDIV3 value. */ member
Dfsl_clock.c469 …V_SOSCDIV1(config->div1) | SCG_SOSCDIV_SOSCDIV2(config->div2) | SCG_SOSCDIV_SOSCDIV3(config->div3); in CLOCK_InitSysOsc()
621 SCG_SIRCDIV_SIRCDIV3(config->div3); in CLOCK_InitSirc()
768 …V_FIRCDIV1(config->div1) | SCG_FIRCDIV_FIRCDIV2(config->div2) | SCG_FIRCDIV_FIRCDIV3(config->div3); in CLOCK_InitFirc()
1074 …V_SPLLDIV1(config->div1) | SCG_SPLLDIV_SPLLDIV2(config->div2) | SCG_SPLLDIV_SPLLDIV3(config->div3); in CLOCK_InitSysPll()
/hal_nxp-latest/mcux/mcux-sdk/devices/K32L2A31A/drivers/
Dfsl_clock.h463 scg_async_clk_div_t div3; /*!< SOSCDIV3 value. */ member
494 scg_async_clk_div_t div3; /*!< SIRCDIV3 value. */ member
579 scg_async_clk_div_t div3; /*!< FIRCDIV3 value. */ member
623 scg_async_clk_div_t div3; /*!< SPLLDIV3 value. */ member
Dfsl_clock.c469 …V_SOSCDIV1(config->div1) | SCG_SOSCDIV_SOSCDIV2(config->div2) | SCG_SOSCDIV_SOSCDIV3(config->div3); in CLOCK_InitSysOsc()
621 SCG_SIRCDIV_SIRCDIV3(config->div3); in CLOCK_InitSirc()
768 …V_FIRCDIV1(config->div1) | SCG_FIRCDIV_FIRCDIV2(config->div2) | SCG_FIRCDIV_FIRCDIV3(config->div3); in CLOCK_InitFirc()
1074 …V_SPLLDIV1(config->div1) | SCG_SPLLDIV_SPLLDIV2(config->div2) | SCG_SPLLDIV_SPLLDIV3(config->div3); in CLOCK_InitSysPll()
/hal_nxp-latest/mcux/mcux-sdk/devices/K32L3A60/drivers/
Dfsl_clock.c400 …V_SIRCDIV1(config->div1) | SCG_SIRCDIV_SIRCDIV2(config->div2) | SCG_SIRCDIV_SIRCDIV3(config->div3); in CLOCK_InitSirc()
537 …V_FIRCDIV1(config->div1) | SCG_FIRCDIV_FIRCDIV2(config->div2) | SCG_FIRCDIV_FIRCDIV3(config->div3); in CLOCK_InitFirc()
719 SCG_LPFLLDIV_LPFLLDIV3(config->div3); in CLOCK_InitLpFll()
Dfsl_clock.h517 scg_async_clk_div_t div3; /*!< SIRCDIV3 value. */ member
601 scg_async_clk_div_t div3; /*!< FIRCDIV3 value. */ member
684 scg_async_clk_div_t div3; /*!< LPFLLDIV3 value. */ member