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/hal_nxp-latest/mcux/mcux-sdk/boards/twrke18f/
Dclock_config.c72 .div1 = kSCG_AsyncClkDisable, in CLOCK_CONFIG_FircSafeConfig()
169 .div1 = kSCG_AsyncClkDivBy1, /* System OSC Clock Divider 1: divided by 1 */
175 .div1 = kSCG_AsyncClkDivBy1, /* Slow IRC Clock Divider 1: divided by 1 */
181 .div1 = kSCG_AsyncClkDivBy1, /* Fast IRC Clock Divider 1: divided by 1 */
189 .div1 = kSCG_AsyncClkDivBy1, /* System PLL Clock Divider 1: divided by 1 */
281 .div1 = kSCG_AsyncClkDivBy1, /* System OSC Clock Divider 1: divided by 1 */
287 .div1 = kSCG_AsyncClkDivBy1, /* Slow IRC Clock Divider 1: divided by 1 */
293 .div1 = kSCG_AsyncClkDivBy1, /* Fast IRC Clock Divider 1: divided by 1 */
301 .div1 = kSCG_AsyncClkDivBy1, /* System PLL Clock Divider 1: divided by 1 */
401 .div1 = kSCG_AsyncClkDivBy1, /* System OSC Clock Divider 1: divided by 1 */
[all …]
/hal_nxp-latest/mcux/mcux-sdk/boards/frdmk32l2a4s/
Dclock_config.c88 .div1 = kSCG_AsyncClkDisable, in CLOCK_CONFIG_FircSafeConfig()
196 ….div1 = kSCG_AsyncClkDisable, /* System OSC Clock Divider 1: Clock output is disabled …
204 … .div1 = kSCG_AsyncClkDisable, /* Slow IRC Clock Divider 1: Clock output is disabled */
211 .div1 = kSCG_AsyncClkDivBy1, /* Fast IRC Clock Divider 1: divided by 1 */
220 ….div1 = kSCG_AsyncClkDisable, /* System PLL Clock Divider 1: Clock output is disabled …
327 .div1 = kSCG_AsyncClkDivBy1, /* System OSC Clock Divider 1: divided by 1 */
335 .div1 = kSCG_AsyncClkDivBy1, /* Slow IRC Clock Divider 1: divided by 1 */
342 .div1 = kSCG_AsyncClkDivBy1, /* Fast IRC Clock Divider 1: divided by 1 */
351 .div1 = kSCG_AsyncClkDivBy1, /* System PLL Clock Divider 1: divided by 1 */
443 ….div1 = kSCG_AsyncClkDisable, /* System OSC Clock Divider 1: Clock output is disabled …
[all …]
/hal_nxp-latest/mcux/mcux-sdk/boards/frdmk32l3a6/
Dclock_config.c74 .div1 = kSCG_AsyncClkDisable, in CLOCK_CONFIG_FircSafeConfig()
149 … .div1 = kSCG_AsyncClkDisable, /* Slow IRC Clock Divider 1: Clock output is disabled */
157 .div1 = kSCG_AsyncClkDivBy1, /* Fast IRC Clock Divider 1: divided by 1 */
166 .div1 = kSCG_AsyncClkDivBy1, /* Low Power FLL Clock Divider 1: divided by 1 */
249 … .div1 = kSCG_AsyncClkDisable, /* Slow IRC Clock Divider 1: Clock output is disabled */
257 .div1 = kSCG_AsyncClkDivBy1, /* Fast IRC Clock Divider 1: divided by 1 */
266 .div1 = kSCG_AsyncClkDivBy1, /* Low Power FLL Clock Divider 1: divided by 1 */
357 .div1 = kSCG_AsyncClkDivBy1, /* Slow IRC Clock Divider 1: divided by 1 */
365 .div1 = kSCG_AsyncClkDivBy1, /* Fast IRC Clock Divider 1: divided by 1 */
374 ….div1 = kSCG_AsyncClkDisable, /* Low Power FLL Clock Divider 1: Clock output is disabl…
/hal_nxp-latest/mcux/mcux-sdk/boards/evkmcimx7ulp/
Dclock_config.c34 .div1 = kSCG_AsyncClkDisable,
47 .div1 = kSCG_AsyncClkDisable,
60 .div1 = kSCG_AsyncClkDisable,
75 .div1 = kSCG_AsyncClkDisable,
92 .div1 = kSCG_AsyncClkDivBy1,
/hal_nxp-latest/mcux/mcux-sdk/devices/MKE18F16/drivers/
Dfsl_clock.h468 scg_async_clk_div_t div1; /*!< SOSCDIV1 value. */ member
497 scg_async_clk_div_t div1; /*!< SIRCDIV1 value. */ member
580 scg_async_clk_div_t div1; /*!< FIRCDIV1 value. */ member
623 scg_async_clk_div_t div1; /*!< SPLLDIV1 value. */ member
Dfsl_clock.c439 SCG->SOSCDIV = SCG_SOSCDIV_SOSCDIV1(config->div1) | SCG_SOSCDIV_SOSCDIV2(config->div2); in CLOCK_InitSysOsc()
587 SCG->SIRCDIV = SCG_SIRCDIV_SIRCDIV1(config->div1) | SCG_SIRCDIV_SIRCDIV2(config->div2); in CLOCK_InitSirc()
730 SCG->FIRCDIV = SCG_FIRCDIV_FIRCDIV1(config->div1) | SCG_FIRCDIV_FIRCDIV2(config->div2); in CLOCK_InitFirc()
1034 SCG->SPLLDIV = SCG_SPLLDIV_SPLLDIV1(config->div1) | SCG_SPLLDIV_SPLLDIV2(config->div2); in CLOCK_InitSysPll()
/hal_nxp-latest/mcux/mcux-sdk/devices/MKE16F16/drivers/
Dfsl_clock.h468 scg_async_clk_div_t div1; /*!< SOSCDIV1 value. */ member
497 scg_async_clk_div_t div1; /*!< SIRCDIV1 value. */ member
580 scg_async_clk_div_t div1; /*!< FIRCDIV1 value. */ member
623 scg_async_clk_div_t div1; /*!< SPLLDIV1 value. */ member
Dfsl_clock.c439 SCG->SOSCDIV = SCG_SOSCDIV_SOSCDIV1(config->div1) | SCG_SOSCDIV_SOSCDIV2(config->div2); in CLOCK_InitSysOsc()
587 SCG->SIRCDIV = SCG_SIRCDIV_SIRCDIV1(config->div1) | SCG_SIRCDIV_SIRCDIV2(config->div2); in CLOCK_InitSirc()
730 SCG->FIRCDIV = SCG_FIRCDIV_FIRCDIV1(config->div1) | SCG_FIRCDIV_FIRCDIV2(config->div2); in CLOCK_InitFirc()
1034 SCG->SPLLDIV = SCG_SPLLDIV_SPLLDIV1(config->div1) | SCG_SPLLDIV_SPLLDIV2(config->div2); in CLOCK_InitSysPll()
/hal_nxp-latest/mcux/mcux-sdk/devices/MKE14F16/drivers/
Dfsl_clock.h462 scg_async_clk_div_t div1; /*!< SOSCDIV1 value. */ member
491 scg_async_clk_div_t div1; /*!< SIRCDIV1 value. */ member
574 scg_async_clk_div_t div1; /*!< FIRCDIV1 value. */ member
617 scg_async_clk_div_t div1; /*!< SPLLDIV1 value. */ member
Dfsl_clock.c439 SCG->SOSCDIV = SCG_SOSCDIV_SOSCDIV1(config->div1) | SCG_SOSCDIV_SOSCDIV2(config->div2); in CLOCK_InitSysOsc()
587 SCG->SIRCDIV = SCG_SIRCDIV_SIRCDIV1(config->div1) | SCG_SIRCDIV_SIRCDIV2(config->div2); in CLOCK_InitSirc()
730 SCG->FIRCDIV = SCG_FIRCDIV_FIRCDIV1(config->div1) | SCG_FIRCDIV_FIRCDIV2(config->div2); in CLOCK_InitFirc()
1034 SCG->SPLLDIV = SCG_SPLLDIV_SPLLDIV1(config->div1) | SCG_SPLLDIV_SPLLDIV2(config->div2); in CLOCK_InitSysPll()
/hal_nxp-latest/mcux/mcux-sdk/devices/MCIMX7U3/drivers/
Dfsl_clock.h629 scg_async_clk_div_t div1; /*!< SOSCDIV1 value. */ member
659 scg_async_clk_div_t div1; /*!< SIRCDIV1 value. */ member
744 scg_async_clk_div_t div1; /*!< FIRCDIV1 value. */ member
787 scg_async_clk_div_t div1; /*!< SPLLDIV1 value. */ member
851 scg_async_clk_div_t div1; /*!< APLLDIV1 value. */ member
Dfsl_clock.c603 …SCG_SOSCDIV_SOSCDIV1(config->div1) | SCG_SOSCDIV_SOSCDIV2(config->div2) | SCG_SOSCDIV_SOSCDIV3(con… in CLOCK_InitSysOsc()
754 …SCG_SIRCDIV_SIRCDIV1(config->div1) | SCG_SIRCDIV_SIRCDIV2(config->div2) | SCG_SIRCDIV_SIRCDIV3(con… in CLOCK_InitSirc()
900 …SCG_FIRCDIV_FIRCDIV1(config->div1) | SCG_FIRCDIV_FIRCDIV2(config->div2) | SCG_FIRCDIV_FIRCDIV3(con… in CLOCK_InitFirc()
1120 …SCG_APLLDIV_APLLDIV1(config->div1) | SCG_APLLDIV_APLLDIV2(config->div2) | SCG_APLLDIV_APLLDIV3(con… in CLOCK_InitAuxPll()
1426 …SCG_SPLLDIV_SPLLDIV1(config->div1) | SCG_SPLLDIV_SPLLDIV2(config->div2) | SCG_SPLLDIV_SPLLDIV3(con… in CLOCK_InitSysPll()
/hal_nxp-latest/mcux/mcux-sdk/devices/MCIMX7U5/drivers/
Dfsl_clock.h629 scg_async_clk_div_t div1; /*!< SOSCDIV1 value. */ member
659 scg_async_clk_div_t div1; /*!< SIRCDIV1 value. */ member
744 scg_async_clk_div_t div1; /*!< FIRCDIV1 value. */ member
787 scg_async_clk_div_t div1; /*!< SPLLDIV1 value. */ member
851 scg_async_clk_div_t div1; /*!< APLLDIV1 value. */ member
Dfsl_clock.c603 …SCG_SOSCDIV_SOSCDIV1(config->div1) | SCG_SOSCDIV_SOSCDIV2(config->div2) | SCG_SOSCDIV_SOSCDIV3(con… in CLOCK_InitSysOsc()
754 …SCG_SIRCDIV_SIRCDIV1(config->div1) | SCG_SIRCDIV_SIRCDIV2(config->div2) | SCG_SIRCDIV_SIRCDIV3(con… in CLOCK_InitSirc()
900 …SCG_FIRCDIV_FIRCDIV1(config->div1) | SCG_FIRCDIV_FIRCDIV2(config->div2) | SCG_FIRCDIV_FIRCDIV3(con… in CLOCK_InitFirc()
1120 …SCG_APLLDIV_APLLDIV1(config->div1) | SCG_APLLDIV_APLLDIV2(config->div2) | SCG_APLLDIV_APLLDIV3(con… in CLOCK_InitAuxPll()
1426 …SCG_SPLLDIV_SPLLDIV1(config->div1) | SCG_SPLLDIV_SPLLDIV2(config->div2) | SCG_SPLLDIV_SPLLDIV3(con… in CLOCK_InitSysPll()
/hal_nxp-latest/mcux/mcux-sdk/devices/K32L2A41A/drivers/
Dfsl_clock.h461 scg_async_clk_div_t div1; /*!< SOSCDIV1 value. */ member
492 scg_async_clk_div_t div1; /*!< SIRCDIV1 value. */ member
577 scg_async_clk_div_t div1; /*!< FIRCDIV1 value. */ member
621 scg_async_clk_div_t div1; /*!< SPLLDIV1 value. */ member
Dfsl_clock.c469 …SCG_SOSCDIV_SOSCDIV1(config->div1) | SCG_SOSCDIV_SOSCDIV2(config->div2) | SCG_SOSCDIV_SOSCDIV3(con… in CLOCK_InitSysOsc()
620 SCG->SIRCDIV = SCG_SIRCDIV_SIRCDIV1(config->div1) | SCG_SIRCDIV_SIRCDIV2(config->div2) | in CLOCK_InitSirc()
768 …SCG_FIRCDIV_FIRCDIV1(config->div1) | SCG_FIRCDIV_FIRCDIV2(config->div2) | SCG_FIRCDIV_FIRCDIV3(con… in CLOCK_InitFirc()
1074 …SCG_SPLLDIV_SPLLDIV1(config->div1) | SCG_SPLLDIV_SPLLDIV2(config->div2) | SCG_SPLLDIV_SPLLDIV3(con… in CLOCK_InitSysPll()
/hal_nxp-latest/mcux/mcux-sdk/devices/K32L2A31A/drivers/
Dfsl_clock.h461 scg_async_clk_div_t div1; /*!< SOSCDIV1 value. */ member
492 scg_async_clk_div_t div1; /*!< SIRCDIV1 value. */ member
577 scg_async_clk_div_t div1; /*!< FIRCDIV1 value. */ member
621 scg_async_clk_div_t div1; /*!< SPLLDIV1 value. */ member
Dfsl_clock.c469 …SCG_SOSCDIV_SOSCDIV1(config->div1) | SCG_SOSCDIV_SOSCDIV2(config->div2) | SCG_SOSCDIV_SOSCDIV3(con… in CLOCK_InitSysOsc()
620 SCG->SIRCDIV = SCG_SIRCDIV_SIRCDIV1(config->div1) | SCG_SIRCDIV_SIRCDIV2(config->div2) | in CLOCK_InitSirc()
768 …SCG_FIRCDIV_FIRCDIV1(config->div1) | SCG_FIRCDIV_FIRCDIV2(config->div2) | SCG_FIRCDIV_FIRCDIV3(con… in CLOCK_InitFirc()
1074 …SCG_SPLLDIV_SPLLDIV1(config->div1) | SCG_SPLLDIV_SPLLDIV2(config->div2) | SCG_SPLLDIV_SPLLDIV3(con… in CLOCK_InitSysPll()
/hal_nxp-latest/mcux/mcux-sdk/devices/K32L3A60/drivers/
Dfsl_clock.c400 …SCG_SIRCDIV_SIRCDIV1(config->div1) | SCG_SIRCDIV_SIRCDIV2(config->div2) | SCG_SIRCDIV_SIRCDIV3(con… in CLOCK_InitSirc()
537 …SCG_FIRCDIV_FIRCDIV1(config->div1) | SCG_FIRCDIV_FIRCDIV2(config->div2) | SCG_FIRCDIV_FIRCDIV3(con… in CLOCK_InitFirc()
718 SCG->LPFLLDIV = SCG_LPFLLDIV_LPFLLDIV1(config->div1) | SCG_LPFLLDIV_LPFLLDIV2(config->div2) | in CLOCK_InitLpFll()
Dfsl_clock.h515 scg_async_clk_div_t div1; /*!< SIRCDIV1 value. */ member
599 scg_async_clk_div_t div1; /*!< FIRCDIV1 value. */ member
682 scg_async_clk_div_t div1; /*!< LPFLLDIV1 value. */ member
/hal_nxp-latest/mcux/mcux-sdk/boards/evkmimx8ulp/
Dclock_config.c54 .div1 = 0U,
76 .div1 = 0U,
/hal_nxp-latest/mcux/mcux-sdk/devices/MIMX8UD7/drivers/
Dfsl_clock.c2400 …config->div1 > 0U ? CGC_PLL0DIV_VCO_DIV1((uint32_t)config->div1 - 1U) : (uint32_t)CGC_PLL0DIV_VCO_… in CLOCK_InitPll0()
2712 …(config->div1 > 0U ? CGC_PLL1DIV_VCO_DIV1((uint32_t)config->div1 - 1U) : CGC_PLL1DIV_VCO_DIV1HALT_… in CLOCK_InitPll1()
3192 …CGC_LPAV->PLL4DIV_VCO = (config->div1 > 0U ? CGC_LPAV_PLL4DIV_VCO_DIV1((uint32_t)config->div1 - … in CLOCK_InitPll4()
/hal_nxp-latest/mcux/mcux-sdk/devices/MIMX8UD5/drivers/
Dfsl_clock.c2400 …config->div1 > 0U ? CGC_PLL0DIV_VCO_DIV1((uint32_t)config->div1 - 1U) : (uint32_t)CGC_PLL0DIV_VCO_… in CLOCK_InitPll0()
2712 …(config->div1 > 0U ? CGC_PLL1DIV_VCO_DIV1((uint32_t)config->div1 - 1U) : CGC_PLL1DIV_VCO_DIV1HALT_… in CLOCK_InitPll1()
3192 …CGC_LPAV->PLL4DIV_VCO = (config->div1 > 0U ? CGC_LPAV_PLL4DIV_VCO_DIV1((uint32_t)config->div1 - … in CLOCK_InitPll4()
/hal_nxp-latest/mcux/mcux-sdk/devices/MIMX8US5/drivers/
Dfsl_clock.c2400 …config->div1 > 0U ? CGC_PLL0DIV_VCO_DIV1((uint32_t)config->div1 - 1U) : (uint32_t)CGC_PLL0DIV_VCO_… in CLOCK_InitPll0()
2712 …(config->div1 > 0U ? CGC_PLL1DIV_VCO_DIV1((uint32_t)config->div1 - 1U) : CGC_PLL1DIV_VCO_DIV1HALT_… in CLOCK_InitPll1()
3192 …CGC_LPAV->PLL4DIV_VCO = (config->div1 > 0U ? CGC_LPAV_PLL4DIV_VCO_DIV1((uint32_t)config->div1 - … in CLOCK_InitPll4()
/hal_nxp-latest/mcux/mcux-sdk/devices/MIMX8US3/drivers/
Dfsl_clock.c2400 …config->div1 > 0U ? CGC_PLL0DIV_VCO_DIV1((uint32_t)config->div1 - 1U) : (uint32_t)CGC_PLL0DIV_VCO_… in CLOCK_InitPll0()
2712 …(config->div1 > 0U ? CGC_PLL1DIV_VCO_DIV1((uint32_t)config->div1 - 1U) : CGC_PLL1DIV_VCO_DIV1HALT_… in CLOCK_InitPll1()
3192 …CGC_LPAV->PLL4DIV_VCO = (config->div1 > 0U ? CGC_LPAV_PLL4DIV_VCO_DIV1((uint32_t)config->div1 - … in CLOCK_InitPll4()

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