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Searched refs:denom (Results 1 – 25 of 28) sorted by relevance

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/hal_nxp-latest/mcux/mcux-sdk/devices/MIMXRT1181/drivers/
Dfsl_clock.c151 …PLL_Type *base, uint8_t div, uint32_t numer, uint8_t post_div, uint32_t denom, const clock_pll_ss_…
685 …PLL_Type *base, uint8_t div, uint32_t numer, uint8_t post_div, uint32_t denom, const clock_pll_ss_… in ANATOP_PllConfigure() argument
697 base->DENOMINATOR.RW = denom; in ANATOP_PllConfigure()
1297 double denom; in CLOCK_GetAudioPllFreq() local
1302 denom = (double)(AUDIO_PLL->DENOMINATOR.RW); in CLOCK_GetAudioPllFreq()
1305 …tmpDouble = ((double)XTAL_FREQ * ((double)div + (numer / denom)) / (double)(uint32_t)(1UL << post_… in CLOCK_GetAudioPllFreq()
/hal_nxp-latest/mcux/mcux-sdk/devices/MIMXRT1189/drivers/
Dfsl_clock.c151 …PLL_Type *base, uint8_t div, uint32_t numer, uint8_t post_div, uint32_t denom, const clock_pll_ss_…
685 …PLL_Type *base, uint8_t div, uint32_t numer, uint8_t post_div, uint32_t denom, const clock_pll_ss_… in ANATOP_PllConfigure() argument
697 base->DENOMINATOR.RW = denom; in ANATOP_PllConfigure()
1297 double denom; in CLOCK_GetAudioPllFreq() local
1302 denom = (double)(AUDIO_PLL->DENOMINATOR.RW); in CLOCK_GetAudioPllFreq()
1305 …tmpDouble = ((double)XTAL_FREQ * ((double)div + (numer / denom)) / (double)(uint32_t)(1UL << post_… in CLOCK_GetAudioPllFreq()
/hal_nxp-latest/mcux/mcux-sdk/devices/MIMXRT1182/drivers/
Dfsl_clock.c151 …PLL_Type *base, uint8_t div, uint32_t numer, uint8_t post_div, uint32_t denom, const clock_pll_ss_…
685 …PLL_Type *base, uint8_t div, uint32_t numer, uint8_t post_div, uint32_t denom, const clock_pll_ss_… in ANATOP_PllConfigure() argument
697 base->DENOMINATOR.RW = denom; in ANATOP_PllConfigure()
1297 double denom; in CLOCK_GetAudioPllFreq() local
1302 denom = (double)(AUDIO_PLL->DENOMINATOR.RW); in CLOCK_GetAudioPllFreq()
1305 …tmpDouble = ((double)XTAL_FREQ * ((double)div + (numer / denom)) / (double)(uint32_t)(1UL << post_… in CLOCK_GetAudioPllFreq()
/hal_nxp-latest/mcux/mcux-sdk/devices/MIMXRT1187/drivers/
Dfsl_clock.c151 …PLL_Type *base, uint8_t div, uint32_t numer, uint8_t post_div, uint32_t denom, const clock_pll_ss_…
685 …PLL_Type *base, uint8_t div, uint32_t numer, uint8_t post_div, uint32_t denom, const clock_pll_ss_… in ANATOP_PllConfigure() argument
697 base->DENOMINATOR.RW = denom; in ANATOP_PllConfigure()
1297 double denom; in CLOCK_GetAudioPllFreq() local
1302 denom = (double)(AUDIO_PLL->DENOMINATOR.RW); in CLOCK_GetAudioPllFreq()
1305 …tmpDouble = ((double)XTAL_FREQ * ((double)div + (numer / denom)) / (double)(uint32_t)(1UL << post_… in CLOCK_GetAudioPllFreq()
/hal_nxp-latest/mcux/mcux-sdk/devices/MIMXRT1175/drivers/
Dfsl_clock.c181 uint32_t denom,
676 …anatop_ai_itf_t itf, uint8_t div, uint32_t numer, uint8_t post_div, uint32_t denom, const clock_pl… in ANATOP_PllConfigure() argument
688 ANATOP_AI_Write(itf, PLL_AI_CTRL3_REG, denom); in ANATOP_PllConfigure()
1487 double denom; in CLOCK_GetAvPllFreq() local
1495 …denom = (double)ANATOP_AI_Read(pll == kCLOCK_PllAudio ? kAI_Itf_Audio : kAI_Itf_Video, PLL_AI_CTRL… in CLOCK_GetAvPllFreq()
1498 …tmpDouble = ((double)XTAL_FREQ * ((double)div + (numer / denom)) / (double)(uint32_t)(1UL << post_… in CLOCK_GetAvPllFreq()
/hal_nxp-latest/mcux/mcux-sdk/devices/MIMXRT1172/drivers/
Dfsl_clock.c181 uint32_t denom,
676 …anatop_ai_itf_t itf, uint8_t div, uint32_t numer, uint8_t post_div, uint32_t denom, const clock_pl… in ANATOP_PllConfigure() argument
688 ANATOP_AI_Write(itf, PLL_AI_CTRL3_REG, denom); in ANATOP_PllConfigure()
1487 double denom; in CLOCK_GetAvPllFreq() local
1495 …denom = (double)ANATOP_AI_Read(pll == kCLOCK_PllAudio ? kAI_Itf_Audio : kAI_Itf_Video, PLL_AI_CTRL… in CLOCK_GetAvPllFreq()
1498 …tmpDouble = ((double)XTAL_FREQ * ((double)div + (numer / denom)) / (double)(uint32_t)(1UL << post_… in CLOCK_GetAvPllFreq()
/hal_nxp-latest/mcux/mcux-sdk/devices/MIMXRT1165/drivers/
Dfsl_clock.c181 uint32_t denom,
682 …anatop_ai_itf_t itf, uint8_t div, uint32_t numer, uint8_t post_div, uint32_t denom, const clock_pl… in ANATOP_PllConfigure() argument
694 ANATOP_AI_Write(itf, PLL_AI_CTRL3_REG, denom); in ANATOP_PllConfigure()
1478 double denom; in CLOCK_GetAvPllFreq() local
1486 …denom = (double)ANATOP_AI_Read(pll == kCLOCK_PllAudio ? kAI_Itf_Audio : kAI_Itf_Video, PLL_AI_CTRL… in CLOCK_GetAvPllFreq()
1489 …tmpDouble = ((double)XTAL_FREQ * ((double)div + (numer / denom)) / (double)(uint32_t)(1UL << post_… in CLOCK_GetAvPllFreq()
/hal_nxp-latest/mcux/mcux-sdk/devices/MIMXRT1176/drivers/
Dfsl_clock.c181 uint32_t denom,
676 …anatop_ai_itf_t itf, uint8_t div, uint32_t numer, uint8_t post_div, uint32_t denom, const clock_pl… in ANATOP_PllConfigure() argument
688 ANATOP_AI_Write(itf, PLL_AI_CTRL3_REG, denom); in ANATOP_PllConfigure()
1487 double denom; in CLOCK_GetAvPllFreq() local
1495 …denom = (double)ANATOP_AI_Read(pll == kCLOCK_PllAudio ? kAI_Itf_Audio : kAI_Itf_Video, PLL_AI_CTRL… in CLOCK_GetAvPllFreq()
1498 …tmpDouble = ((double)XTAL_FREQ * ((double)div + (numer / denom)) / (double)(uint32_t)(1UL << post_… in CLOCK_GetAvPllFreq()
/hal_nxp-latest/mcux/mcux-sdk/devices/MIMXRT1173/drivers/
Dfsl_clock.c181 uint32_t denom,
676 …anatop_ai_itf_t itf, uint8_t div, uint32_t numer, uint8_t post_div, uint32_t denom, const clock_pl… in ANATOP_PllConfigure() argument
688 ANATOP_AI_Write(itf, PLL_AI_CTRL3_REG, denom); in ANATOP_PllConfigure()
1487 double denom; in CLOCK_GetAvPllFreq() local
1495 …denom = (double)ANATOP_AI_Read(pll == kCLOCK_PllAudio ? kAI_Itf_Audio : kAI_Itf_Video, PLL_AI_CTRL… in CLOCK_GetAvPllFreq()
1498 …tmpDouble = ((double)XTAL_FREQ * ((double)div + (numer / denom)) / (double)(uint32_t)(1UL << post_… in CLOCK_GetAvPllFreq()
/hal_nxp-latest/mcux/mcux-sdk/devices/MIMXRT1171/drivers/
Dfsl_clock.c181 uint32_t denom,
676 …anatop_ai_itf_t itf, uint8_t div, uint32_t numer, uint8_t post_div, uint32_t denom, const clock_pl… in ANATOP_PllConfigure() argument
688 ANATOP_AI_Write(itf, PLL_AI_CTRL3_REG, denom); in ANATOP_PllConfigure()
1487 double denom; in CLOCK_GetAvPllFreq() local
1495 …denom = (double)ANATOP_AI_Read(pll == kCLOCK_PllAudio ? kAI_Itf_Audio : kAI_Itf_Video, PLL_AI_CTRL… in CLOCK_GetAvPllFreq()
1498 …tmpDouble = ((double)XTAL_FREQ * ((double)div + (numer / denom)) / (double)(uint32_t)(1UL << post_… in CLOCK_GetAvPllFreq()
/hal_nxp-latest/mcux/mcux-sdk/devices/MIMXRT1166/drivers/
Dfsl_clock.c181 uint32_t denom,
682 …anatop_ai_itf_t itf, uint8_t div, uint32_t numer, uint8_t post_div, uint32_t denom, const clock_pl… in ANATOP_PllConfigure() argument
694 ANATOP_AI_Write(itf, PLL_AI_CTRL3_REG, denom); in ANATOP_PllConfigure()
1478 double denom; in CLOCK_GetAvPllFreq() local
1486 …denom = (double)ANATOP_AI_Read(pll == kCLOCK_PllAudio ? kAI_Itf_Audio : kAI_Itf_Video, PLL_AI_CTRL… in CLOCK_GetAvPllFreq()
1489 …tmpDouble = ((double)XTAL_FREQ * ((double)div + (numer / denom)) / (double)(uint32_t)(1UL << post_… in CLOCK_GetAvPllFreq()
/hal_nxp-latest/mcux/middleware/wireless/framework_5.3.3/XCVR/MKW40Z4/
DKW4xXcvrDrv.c1859 int32_t denom = 0x04000000; in XcvrOverrideFrequency() local
1883 num = (int32_t) (fract_check * denom); in XcvrOverrideFrequency()
1890 XCVR_BWR_PLL_LP_SDM_CTRL3_LPM_DENOM(XCVR, denom); in XcvrOverrideFrequency()
/hal_nxp-latest/mcux/mcux-sdk/boards/evkmcimx7ulp/
Dclock_config.c103 … .denom = 1000000U}; /* 24 x 22.528 = 540.672MHz */
/hal_nxp-latest/mcux/mcux-sdk/boards/evkmimx8ulp/
Dclock_config.c82 .denom = 1000000U};
/hal_nxp-latest/mcux/mcux-sdk/devices/MIMX8UD7/drivers/
Dfsl_clock.h1450 uint32_t denom : 30; /*!< 30-bit denominator of the PLL1 Fractional-Loop divider. */ member
1485 uint32_t denom : 30; /*!< 30-bit denominator of the PLL4 Fractional-Loop divider. */ member
Dfsl_clock.c2722 CGC_RTD->PLL1DENOM = config->denom; in CLOCK_InitPll1()
3215 CGC_LPAV->PLL4DENOM = config->denom; in CLOCK_InitPll4()
/hal_nxp-latest/mcux/mcux-sdk/devices/MIMX8US5/drivers/
Dfsl_clock.h1450 uint32_t denom : 30; /*!< 30-bit denominator of the PLL1 Fractional-Loop divider. */ member
1485 uint32_t denom : 30; /*!< 30-bit denominator of the PLL4 Fractional-Loop divider. */ member
/hal_nxp-latest/mcux/mcux-sdk/devices/MIMX8UD5/drivers/
Dfsl_clock.h1450 uint32_t denom : 30; /*!< 30-bit denominator of the PLL1 Fractional-Loop divider. */ member
1485 uint32_t denom : 30; /*!< 30-bit denominator of the PLL4 Fractional-Loop divider. */ member
Dfsl_clock.c2722 CGC_RTD->PLL1DENOM = config->denom; in CLOCK_InitPll1()
3215 CGC_LPAV->PLL4DENOM = config->denom; in CLOCK_InitPll4()
/hal_nxp-latest/mcux/mcux-sdk/devices/MIMX8US3/drivers/
Dfsl_clock.h1450 uint32_t denom : 30; /*!< 30-bit denominator of the PLL1 Fractional-Loop divider. */ member
1485 uint32_t denom : 30; /*!< 30-bit denominator of the PLL4 Fractional-Loop divider. */ member
/hal_nxp-latest/mcux/mcux-sdk/devices/MIMX8UD3/drivers/
Dfsl_clock.h1450 uint32_t denom : 30; /*!< 30-bit denominator of the PLL1 Fractional-Loop divider. */ member
1485 uint32_t denom : 30; /*!< 30-bit denominator of the PLL4 Fractional-Loop divider. */ member
/hal_nxp-latest/mcux/mcux-sdk/devices/MCIMX7U3/drivers/
Dfsl_clock.h864 uint32_t denom : 30; /*!< 30-bit denominator of the Auxiliary PLL Fractional-Loop divider. */ member
Dfsl_clock.c1129 SCG->APLLDENOM = config->denom; in CLOCK_InitAuxPll()
/hal_nxp-latest/mcux/mcux-sdk/devices/MCIMX7U5/drivers/
Dfsl_clock.h864 uint32_t denom : 30; /*!< 30-bit denominator of the Auxiliary PLL Fractional-Loop divider. */ member
Dfsl_clock.c1129 SCG->APLLDENOM = config->denom; in CLOCK_InitAuxPll()

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