Searched refs:clkOutputPhase (Results 1 – 2 of 2) sorted by relevance
115 …bool clkOutputPhase; /*!< True: Inverted divided clock is output, False: Non-inverted divided cloc… member
94 … ENETC_PF_TMR_TMR_CTRL_TCLK_PERIOD(period) | ENETC_PF_TMR_TMR_CTRL_COPH(config->clkOutputPhase) | in NETC_TimerInit()
