| /hal_nxp-latest/mcux/mcux-sdk/drivers/netc/ |
| D | fsl_netc_timer.c | 205 uint32_t clear; in NETC_TimerStartFIPER() local
214 clear = ENETC_PF_TMR_TMR_FIPER_CTRL_FIPER1_PW_MASK | ENETC_PF_TMR_TMR_FIPER_CTRL_PG1_MASK; in NETC_TimerStartFIPER()
225 clear = ENETC_PF_TMR_TMR_FIPER_CTRL_FIPER2_PW_MASK | ENETC_PF_TMR_TMR_FIPER_CTRL_PG2_MASK; in NETC_TimerStartFIPER()
236 clear = ENETC_PF_TMR_TMR_FIPER_CTRL_FIPER3_PW_MASK | ENETC_PF_TMR_TMR_FIPER_CTRL_PG3_MASK; in NETC_TimerStartFIPER()
242 handle->hw.base->TMR_FIPER_CTRL &= ~clear; in NETC_TimerStartFIPER()
273 uint32_t clear; in NETC_TimerConfigureExtPulseTrig() local
275 …clear = (extTrigId == kNETC_TimerExtTrig1) ? ENETC_PF_TMR_TMR_CTRL_ETEP1_MASK : ENETC_PF_TMR_TMR… in NETC_TimerConfigureExtPulseTrig()
278 handle->hw.base->TMR_CTRL &= ~clear; in NETC_TimerConfigureExtPulseTrig()
281 clear = (extTrigId == kNETC_TimerExtTrig1) ? in NETC_TimerConfigureExtPulseTrig()
293 handle->hw.base->TMR_TEMASK &= ~clear; in NETC_TimerConfigureExtPulseTrig()
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| /hal_nxp-latest/mcux/mcux-sdk/boards/mcimx93qsb/ |
| D | board.h | 62 #define CLRBIT32(addr, clear) W32(addr, R32(addr) & ~clear) argument
63 #define CLRSETBIT32(addr, clear, set) W32(addr, (R32(addr) & ~clear) | set) argument
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| /hal_nxp-latest/mcux/mcux-sdk/boards/mcimx93autoevk/ |
| D | board.h | 72 #define CLRBIT32(addr, clear) W32(addr, R32(addr) & ~clear) argument
73 #define CLRSETBIT32(addr, clear, set) W32(addr, (R32(addr) & ~clear) | set) argument
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| /hal_nxp-latest/mcux/mcux-sdk/boards/mcimx93evk/ |
| D | board.h | 78 #define CLRBIT32(addr, clear) W32(addr, R32(addr) & ~clear) argument
79 #define CLRSETBIT32(addr, clear, set) W32(addr, (R32(addr) & ~clear) | set) argument
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| /hal_nxp-latest/mcux/mcux-sdk/drivers/edma_rev2/ |
| D | fsl_edma_rev2.c | 92 uint32_t set, uint32_t clear) in EDMA_ChannelRegUpdate() argument
99 val &= ~clear; in EDMA_ChannelRegUpdate()
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| D | fsl_edma_rev2.h | 257 uint32_t set, uint32_t clear);
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| /hal_nxp-latest/mcux/mcux-sdk/boards/evkmimx8ulp/ |
| D | board.h | 208 #define CLRBIT32(addr, clear) W32(addr, R32(addr) & ~clear) argument
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| /hal_nxp-latest/mcux/mcux-sdk/boards/evkmimxrt1180/jlinkscript/ |
| D | evkmimxrt1180_cm33.jlinkscript | 388 _WriteViaCM33AP32(0x52010000, 0x40000000); // DMA4->TDC[0].CH_CSR, clear DONE flag
411 _WriteViaCM33AP32(0x52010000, 0x40000000); // DMA4->TDC[0].CH_CSR, clear DONE flag
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| D | evkmimxrt1180_cm7.jlinkscript | 388 _WriteViaCM33AP32(0x52010000, 0x40000000); // DMA4->TDC[0].CH_CSR, clear DONE flag
411 _WriteViaCM33AP32(0x52010000, 0x40000000); // DMA4->TDC[0].CH_CSR, clear DONE flag
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| /hal_nxp-latest/mcux/mcux-sdk/boards/evkmimxrt1170/ |
| D | evkmimxrt1170_connect_cm4_cm4side_sdram.jlinkscript | 36 MEM_WriteU32(0x400D403C, 0x00000003); // clear IPCMDERR and IPCMDDONE bits
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| /hal_nxp-latest/mcux/mcux-sdk/boards/evkbmimxrt1170/ |
| D | evkbmimxrt1170_connect_cm4_cm4side_sdram.jlinkscript | 36 MEM_WriteU32(0x400D403C, 0x00000003); // clear IPCMDERR and IPCMDDONE bits
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| /hal_nxp-latest/mcux/mcux-sdk/ |
| D | CONTRIBUTING.md | 120 * Have a short and clear subject line. A suggest subject line length limits to 72 characters and us…
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| D | LA_OPT_NXP_Software_License RTAudio.txt | 61 22. AUDIT. You will keep full, clear and accurate records with respect to your compliance w…
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| D | LA_OPT_NXP_Software_License.txt | 343 21. AUDIT. You will keep full, clear and accurate records with respect
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| /hal_nxp-latest/mcux/mcux-sdk/middleware/mmcau/asm-cm0p/src/ |
| D | mmcau_sha256_functions.s | 80 movs r0, #0 @ clear the return value
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| /hal_nxp-latest/zephyr/blobs/license/ |
| D | LA_OPT_NXP_Online_Code_Hosting.txt | 343 20. AUDIT. You will keep full, clear and accurate records with respect to
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| D | LA_OPT_NXP_Software_License.txt | 343 21. AUDIT. You will keep full, clear and accurate records with respect
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