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/hal_nxp-latest/mcux/mcux-sdk/devices/MKW40Z4/drivers/
Dfsl_bitaccess.h79 #define BME_BFI8(addr, wdata, bit, width) (*(volatile uint8_t*)((uintptr_t)addr | BME_BFI_MASK(bit,… argument
80 #define BME_BFI16(addr, wdata, bit, width) (*(volatile uint16_t*)((uintptr_t)addr | BME_BFI_MASK(bi… argument
81 #define BME_BFI32(addr, wdata, bit, width) (*(volatile uint32_t*)((uintptr_t)addr | BME_BFI_MASK(bi… argument
84 #define BME_UBFX8(addr, bit, width) (*(volatile uint8_t*)((uintptr_t)addr | BME_UBFX_MASK(bit,width… argument
85 #define BME_UBFX16(addr, bit, width) (*(volatile uint16_t*)((uintptr_t)addr | BME_UBFX_MASK(bit,wid… argument
86 #define BME_UBFX32(addr, bit, width) (*(volatile uint32_t*)((uintptr_t)addr | BME_UBFX_MASK(bit,wid… argument
/hal_nxp-latest/mcux/mcux-sdk/components/crc/
Dfsl_adapter_software_crc.c25 uint8_t bit; in HAL_CrcCompute() local
36 bit = 0U; in HAL_CrcCompute()
39 bit = (bit << 1); in HAL_CrcCompute()
40 bit |= ((data & 1U) != 0U) ? 1U : 0U; in HAL_CrcCompute()
43 data = bit; in HAL_CrcCompute()
48 bit = ((data & 0x80U) != 0U) ? 1U : 0U; in HAL_CrcCompute()
53 bit = (bit != 0U) ? 0U : 1U; in HAL_CrcCompute()
58 if (bit != 0U) in HAL_CrcCompute()
63 if ((bool)bit && ((crcPoly & (1UL << (32U - crcBits))) != 0U)) in HAL_CrcCompute()
/hal_nxp-latest/mcux/mcux-sdk/devices/MIMXRT735S/drivers/
Dfsl_power.h42 #define GET_PD_REG_FROM_BITS(bit) (((uint32_t)(bit) >> 8U) & 0xFFU) argument
248 #define GET_LP_CTRL_REG_FROM_BITS(bit) (((uint32_t)(bit) >> POWER_LP_REQ_CTRL_REG_OFFSET) & 0x7U) argument
249 #define GET_LP_CTRL_BIT_FROM_BITS(bit) (((uint32_t)(bit)) & 0x1FU) argument
250 #define GET_LP_STATE_REG_FROM_BITS(bit) (((uint32_t)(bit) >> POWER_LP_REQ_STATE_REG_OFFSET) & 0x7U) argument
251 #define GET_LP_STATE_BIT_FROM_BITS(bit) ((((uint32_t)(bit)) >> POWER_LP_REQ_STATE_BIT_OFFSET) & 0x1… argument
/hal_nxp-latest/mcux/mcux-sdk/devices/MIMXRT798S/drivers/
Dfsl_power.h42 #define GET_PD_REG_FROM_BITS(bit) (((uint32_t)(bit) >> 8U) & 0xFFU) argument
248 #define GET_LP_CTRL_REG_FROM_BITS(bit) (((uint32_t)(bit) >> POWER_LP_REQ_CTRL_REG_OFFSET) & 0x7U) argument
249 #define GET_LP_CTRL_BIT_FROM_BITS(bit) (((uint32_t)(bit)) & 0x1FU) argument
250 #define GET_LP_STATE_REG_FROM_BITS(bit) (((uint32_t)(bit) >> POWER_LP_REQ_STATE_REG_OFFSET) & 0x7U) argument
251 #define GET_LP_STATE_BIT_FROM_BITS(bit) ((((uint32_t)(bit)) >> POWER_LP_REQ_STATE_BIT_OFFSET) & 0x1… argument
/hal_nxp-latest/mcux/mcux-sdk/devices/MIMXRT758S/drivers/
Dfsl_power.h42 #define GET_PD_REG_FROM_BITS(bit) (((uint32_t)(bit) >> 8U) & 0xFFU) argument
248 #define GET_LP_CTRL_REG_FROM_BITS(bit) (((uint32_t)(bit) >> POWER_LP_REQ_CTRL_REG_OFFSET) & 0x7U) argument
249 #define GET_LP_CTRL_BIT_FROM_BITS(bit) (((uint32_t)(bit)) & 0x1FU) argument
250 #define GET_LP_STATE_REG_FROM_BITS(bit) (((uint32_t)(bit) >> POWER_LP_REQ_STATE_REG_OFFSET) & 0x7U) argument
251 #define GET_LP_STATE_BIT_FROM_BITS(bit) ((((uint32_t)(bit)) >> POWER_LP_REQ_STATE_BIT_OFFSET) & 0x1… argument
/hal_nxp-latest/mcux/mcux-sdk/middleware/mmcau/asm-cm0p/src/
Dmmcau_des_functions.s38 # *key pointer to 64-bit DES key with parity bits
63 # load the 64-bit key into the CAU's CA0/CA1 regs
131 # load the 64-bit plaintext input block into the CAU's CA2/CA3 regs
224 # load the 64-bit ciphertext input block into the CAU's CA2/CA3 regs
Dmmcau_sha256_functions.s37 # *output pointer to 256-bit message digest output
93 # num_blks number of 512-bit blocks to process
94 # *output pointer to 256-bit message digest
563 # num_blks number of 512-bit blocks to process
564 # *output pointer to 256-bit message digest
624 # *output pointer to 256-bit message digest
/hal_nxp-latest/mcux/mcux-sdk/middleware/mmcau/asm-cm4-cm7/src/
Dmmcau_des_functions.s42 # *key pointer to 64-bit DES key with parity bits
59 # load the 64-bit key into the CAU's CA0/CA1 registers
121 # and the 64-bit plaintext input block into CA2/CA3
163 # *key pointer to 64-bit DES key with parity bits
196 # load the 64-bit key into the CAU's CA0/CA1 registers
/hal_nxp-latest/mcux/mcux-sdk/utilities/unity/
Dunity.h322 #define TEST_ASSERT_BIT_HIGH(bit, actual) \ argument
323 UNITY_TEST_ASSERT_BITS(((_UU32)1 << bit), (_UU32)(-1), (actual), __LINE__, NULL)
324 #define TEST_ASSERT_BIT_LOW(bit, actual) UNITY_TEST_ASSERT_BITS(((_UU32)1 << bit), (_UU32)(0), (act… argument
459 #define TEST_ASSERT_BIT_HIGH_MESSAGE(bit, actual, message) \ argument
460 UNITY_TEST_ASSERT_BITS(((_UU32)1 << bit), (_UU32)(-1), (actual), __LINE__, message)
461 #define TEST_ASSERT_BIT_LOW_MESSAGE(bit, actual, message) \ argument
462 UNITY_TEST_ASSERT_BITS(((_UU32)1 << bit), (_UU32)(0), (actual), __LINE__, message)
/hal_nxp-latest/mcux/middleware/wifi_nxp/wifidriver/
Dmlan_11k.c77 static void wlan_rrm_bit_field_set(t_u8 *bits_field, t_u8 bit) in wlan_rrm_bit_field_set() argument
79 if (bit >= (t_u8)rrm_bits_max) in wlan_rrm_bit_field_set()
84 bits_field[bit / 8U] |= BIT(bit % 8U); in wlan_rrm_bit_field_set()
87 static bool wlan_rrm_bit_field_is_set(t_u8 *bit_field, t_u8 bit) in wlan_rrm_bit_field_is_set() argument
89 if (bit >= (t_u8)rrm_bits_max) in wlan_rrm_bit_field_is_set()
94 return ((bit_field[bit / (t_u8)8U] & (t_u8)(BIT((bit % 8U)))) != (t_u8)0U); in wlan_rrm_bit_field_is_set()
/hal_nxp-latest/mcux/mcux-sdk/devices/LPC5536/drivers/
Dfsl_clock.h933 uint32_t bit = CLK_GATE_ABSTRACT_BITS_SHIFT(clk); in CLOCK_EnableClock() local
937 SYSCON->PWM0SUBCTL |= (1UL << bit); in CLOCK_EnableClock()
942 SYSCON->PWM1SUBCTL |= (1UL << bit); in CLOCK_EnableClock()
947 SYSCON->AHBCLKCTRLSET[index] = (1UL << bit); in CLOCK_EnableClock()
958 uint32_t bit = CLK_GATE_ABSTRACT_BITS_SHIFT(clk); in CLOCK_DisableClock() local
962 SYSCON->PWM0SUBCTL &= ~(1UL << bit); in CLOCK_DisableClock()
970 SYSCON->PWM1SUBCTL &= ~(1UL << bit); in CLOCK_DisableClock()
978 SYSCON->AHBCLKCTRLCLR[index] = (1UL << bit); in CLOCK_DisableClock()
/hal_nxp-latest/mcux/mcux-sdk/devices/LPC55S36/drivers/
Dfsl_clock.h933 uint32_t bit = CLK_GATE_ABSTRACT_BITS_SHIFT(clk); in CLOCK_EnableClock() local
937 SYSCON->PWM0SUBCTL |= (1UL << bit); in CLOCK_EnableClock()
942 SYSCON->PWM1SUBCTL |= (1UL << bit); in CLOCK_EnableClock()
947 SYSCON->AHBCLKCTRLSET[index] = (1UL << bit); in CLOCK_EnableClock()
958 uint32_t bit = CLK_GATE_ABSTRACT_BITS_SHIFT(clk); in CLOCK_DisableClock() local
962 SYSCON->PWM0SUBCTL &= ~(1UL << bit); in CLOCK_DisableClock()
970 SYSCON->PWM1SUBCTL &= ~(1UL << bit); in CLOCK_DisableClock()
978 SYSCON->AHBCLKCTRLCLR[index] = (1UL << bit); in CLOCK_DisableClock()
/hal_nxp-latest/mcux/mcux-sdk/devices/LPC5534/drivers/
Dfsl_clock.h933 uint32_t bit = CLK_GATE_ABSTRACT_BITS_SHIFT(clk); in CLOCK_EnableClock() local
937 SYSCON->PWM0SUBCTL |= (1UL << bit); in CLOCK_EnableClock()
942 SYSCON->PWM1SUBCTL |= (1UL << bit); in CLOCK_EnableClock()
947 SYSCON->AHBCLKCTRLSET[index] = (1UL << bit); in CLOCK_EnableClock()
958 uint32_t bit = CLK_GATE_ABSTRACT_BITS_SHIFT(clk); in CLOCK_DisableClock() local
962 SYSCON->PWM0SUBCTL &= ~(1UL << bit); in CLOCK_DisableClock()
970 SYSCON->PWM1SUBCTL &= ~(1UL << bit); in CLOCK_DisableClock()
978 SYSCON->AHBCLKCTRLCLR[index] = (1UL << bit); in CLOCK_DisableClock()
/hal_nxp-latest/mcux/mcux-sdk/devices/MCXN236/drivers/
Dfsl_clock.h1143 uint32_t bit = CLK_GATE_ABSTRACT_BITS_SHIFT(clk); in CLOCK_EnableClock() local
1147 SYSCON->PWM0SUBCTL |= (1UL << bit); in CLOCK_EnableClock()
1152 SYSCON->PWM1SUBCTL |= (1UL << bit); in CLOCK_EnableClock()
1157 SYSCON->AHBCLKCTRLSET[index] = (1UL << bit); in CLOCK_EnableClock()
1169 uint32_t bit = CLK_GATE_ABSTRACT_BITS_SHIFT(clk); in CLOCK_DisableClock() local
1173 SYSCON->PWM0SUBCTL &= ~(1UL << bit); in CLOCK_DisableClock()
1181 SYSCON->PWM1SUBCTL &= ~(1UL << bit); in CLOCK_DisableClock()
1189 SYSCON->AHBCLKCTRLCLR[index] = (1UL << bit); in CLOCK_DisableClock()
/hal_nxp-latest/mcux/mcux-sdk/devices/MCXN235/drivers/
Dfsl_clock.h1143 uint32_t bit = CLK_GATE_ABSTRACT_BITS_SHIFT(clk); in CLOCK_EnableClock() local
1147 SYSCON->PWM0SUBCTL |= (1UL << bit); in CLOCK_EnableClock()
1152 SYSCON->PWM1SUBCTL |= (1UL << bit); in CLOCK_EnableClock()
1157 SYSCON->AHBCLKCTRLSET[index] = (1UL << bit); in CLOCK_EnableClock()
1169 uint32_t bit = CLK_GATE_ABSTRACT_BITS_SHIFT(clk); in CLOCK_DisableClock() local
1173 SYSCON->PWM0SUBCTL &= ~(1UL << bit); in CLOCK_DisableClock()
1181 SYSCON->PWM1SUBCTL &= ~(1UL << bit); in CLOCK_DisableClock()
1189 SYSCON->AHBCLKCTRLCLR[index] = (1UL << bit); in CLOCK_DisableClock()
/hal_nxp-latest/mcux/mcux-sdk/devices/MCXN546/drivers/
Dfsl_clock.h1397 uint32_t bit = CLK_GATE_ABSTRACT_BITS_SHIFT(clk); in CLOCK_EnableClock() local
1401 SYSCON->PWM0SUBCTL |= (1UL << bit); in CLOCK_EnableClock()
1406 SYSCON->PWM1SUBCTL |= (1UL << bit); in CLOCK_EnableClock()
1411 SYSCON->AHBCLKCTRLSET[index] = (1UL << bit); in CLOCK_EnableClock()
1423 uint32_t bit = CLK_GATE_ABSTRACT_BITS_SHIFT(clk); in CLOCK_DisableClock() local
1427 SYSCON->PWM0SUBCTL &= ~(1UL << bit); in CLOCK_DisableClock()
1435 SYSCON->PWM1SUBCTL &= ~(1UL << bit); in CLOCK_DisableClock()
1443 SYSCON->AHBCLKCTRLCLR[index] = (1UL << bit); in CLOCK_DisableClock()
/hal_nxp-latest/mcux/mcux-sdk/devices/MCXN946/drivers/
Dfsl_clock.h1397 uint32_t bit = CLK_GATE_ABSTRACT_BITS_SHIFT(clk); in CLOCK_EnableClock() local
1401 SYSCON->PWM0SUBCTL |= (1UL << bit); in CLOCK_EnableClock()
1406 SYSCON->PWM1SUBCTL |= (1UL << bit); in CLOCK_EnableClock()
1411 SYSCON->AHBCLKCTRLSET[index] = (1UL << bit); in CLOCK_EnableClock()
1423 uint32_t bit = CLK_GATE_ABSTRACT_BITS_SHIFT(clk); in CLOCK_DisableClock() local
1427 SYSCON->PWM0SUBCTL &= ~(1UL << bit); in CLOCK_DisableClock()
1435 SYSCON->PWM1SUBCTL &= ~(1UL << bit); in CLOCK_DisableClock()
1443 SYSCON->AHBCLKCTRLCLR[index] = (1UL << bit); in CLOCK_DisableClock()
/hal_nxp-latest/mcux/mcux-sdk/devices/MCXN947/drivers/
Dfsl_clock.h1397 uint32_t bit = CLK_GATE_ABSTRACT_BITS_SHIFT(clk); in CLOCK_EnableClock() local
1401 SYSCON->PWM0SUBCTL |= (1UL << bit); in CLOCK_EnableClock()
1406 SYSCON->PWM1SUBCTL |= (1UL << bit); in CLOCK_EnableClock()
1411 SYSCON->AHBCLKCTRLSET[index] = (1UL << bit); in CLOCK_EnableClock()
1423 uint32_t bit = CLK_GATE_ABSTRACT_BITS_SHIFT(clk); in CLOCK_DisableClock() local
1427 SYSCON->PWM0SUBCTL &= ~(1UL << bit); in CLOCK_DisableClock()
1435 SYSCON->PWM1SUBCTL &= ~(1UL << bit); in CLOCK_DisableClock()
1443 SYSCON->AHBCLKCTRLCLR[index] = (1UL << bit); in CLOCK_DisableClock()
/hal_nxp-latest/mcux/mcux-sdk/devices/MCXN547/drivers/
Dfsl_clock.h1397 uint32_t bit = CLK_GATE_ABSTRACT_BITS_SHIFT(clk); in CLOCK_EnableClock() local
1401 SYSCON->PWM0SUBCTL |= (1UL << bit); in CLOCK_EnableClock()
1406 SYSCON->PWM1SUBCTL |= (1UL << bit); in CLOCK_EnableClock()
1411 SYSCON->AHBCLKCTRLSET[index] = (1UL << bit); in CLOCK_EnableClock()
1423 uint32_t bit = CLK_GATE_ABSTRACT_BITS_SHIFT(clk); in CLOCK_DisableClock() local
1427 SYSCON->PWM0SUBCTL &= ~(1UL << bit); in CLOCK_DisableClock()
1435 SYSCON->PWM1SUBCTL &= ~(1UL << bit); in CLOCK_DisableClock()
1443 SYSCON->AHBCLKCTRLCLR[index] = (1UL << bit); in CLOCK_DisableClock()
/hal_nxp-latest/mcux/mcux-sdk/components/serial_manager/usb_cdc_adapter/inf/
Dfsl_ucwxp.inf24 ; Windows 2000/XP/Vista-32bit Sections
47 ; Vista-64bit Sections
/hal_nxp-latest/mcux/mcux-sdk/drivers/flexio/mculcd/
Dfsl_flexio_mculcd.h52 #error Only support data bus 8-bit or 16-bit
/hal_nxp-latest/mcux/mcux-sdk/devices/LPC802/drivers/
Dfsl_clock.h162 #define CLK_GATE_DEFINE(reg, bit) ((((reg)&0xFFU) << 8U) | ((bit)&0xFFU)) argument
/hal_nxp-latest/mcux/mcux-sdk/devices/LPC812/drivers/
Dfsl_clock.h142 #define CLK_GATE_DEFINE(reg, bit) ((((reg)&0xFFU) << 8U) | ((bit)&0xFFU)) argument
/hal_nxp-latest/mcux/mcux-sdk/devices/LPC811/drivers/
Dfsl_clock.h144 #define CLK_GATE_DEFINE(reg, bit) ((((reg)&0xFFU) << 8U) | ((bit)&0xFFU)) argument
/hal_nxp-latest/mcux/mcux-sdk/devices/LPC810/drivers/
Dfsl_clock.h144 #define CLK_GATE_DEFINE(reg, bit) ((((reg)&0xFFU) << 8U) | ((bit)&0xFFU)) argument

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