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Searched refs:anatop_ai_itf_t (Results 1 – 21 of 21) sorted by relevance

/hal_nxp-latest/mcux/mcux-sdk/devices/MIMXRT1172/drivers/
Dfsl_anatop_ai.h35 } anatop_ai_itf_t; typedef
490 uint32_t ANATOP_AI_Access(anatop_ai_itf_t itf, bool isWrite, anatop_ai_reg_t addr, uint32_t wdata);
500 void ANATOP_AI_Write(anatop_ai_itf_t itf, anatop_ai_reg_t addr, uint32_t wdata);
510 uint32_t ANATOP_AI_Read(anatop_ai_itf_t itf, anatop_ai_reg_t addr);
523 anatop_ai_itf_t itf, anatop_ai_reg_t addr, uint32_t wdata, uint32_t mask, uint32_t shift);
Dfsl_clock.c171 static void ANATOP_PllSetPower(anatop_ai_itf_t itf, bool enable);
172 static void ANATOP_PllBypass(anatop_ai_itf_t itf, bool bypass);
173 static void ANATOP_PllEnablePllReg(anatop_ai_itf_t itf, bool enable);
174 static void ANATOP_PllHoldRingOff(anatop_ai_itf_t itf, bool off);
175 static void ANATOP_PllToggleHoldRingOff(anatop_ai_itf_t itf, uint32_t delayUsValue);
176 static void ANATOP_PllEnableClk(anatop_ai_itf_t itf, bool enable);
177 static void ANATOP_PllConfigure(anatop_ai_itf_t itf,
192 static void ANATOP_PllEnableSs(anatop_ai_itf_t itf, bool enable);
637 static void ANATOP_PllSetPower(anatop_ai_itf_t itf, bool enable) in ANATOP_PllSetPower()
643 static void ANATOP_PllBypass(anatop_ai_itf_t itf, bool bypass) in ANATOP_PllBypass()
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Dfsl_anatop_ai.c14 uint32_t ANATOP_AI_Access(anatop_ai_itf_t itf, bool isWrite, anatop_ai_reg_t addr, uint32_t wdata) in ANATOP_AI_Access()
338 void ANATOP_AI_Write(anatop_ai_itf_t itf, anatop_ai_reg_t addr, uint32_t wdata) in ANATOP_AI_Write()
343 uint32_t ANATOP_AI_Read(anatop_ai_itf_t itf, anatop_ai_reg_t addr) in ANATOP_AI_Read()
351 anatop_ai_itf_t itf, anatop_ai_reg_t addr, uint32_t wdata, uint32_t mask, uint32_t shift) in ANATOP_AI_WriteWithMaskShift()
/hal_nxp-latest/mcux/mcux-sdk/devices/MIMXRT1165/drivers/
Dfsl_anatop_ai.h35 } anatop_ai_itf_t; typedef
490 uint32_t ANATOP_AI_Access(anatop_ai_itf_t itf, bool isWrite, anatop_ai_reg_t addr, uint32_t wdata);
500 void ANATOP_AI_Write(anatop_ai_itf_t itf, anatop_ai_reg_t addr, uint32_t wdata);
510 uint32_t ANATOP_AI_Read(anatop_ai_itf_t itf, anatop_ai_reg_t addr);
523 anatop_ai_itf_t itf, anatop_ai_reg_t addr, uint32_t wdata, uint32_t mask, uint32_t shift);
Dfsl_clock.c171 static void ANATOP_PllSetPower(anatop_ai_itf_t itf, bool enable);
172 static void ANATOP_PllBypass(anatop_ai_itf_t itf, bool bypass);
173 static void ANATOP_PllEnablePllReg(anatop_ai_itf_t itf, bool enable);
174 static void ANATOP_PllHoldRingOff(anatop_ai_itf_t itf, bool off);
175 static void ANATOP_PllToggleHoldRingOff(anatop_ai_itf_t itf, uint32_t delay_us);
176 static void ANATOP_PllEnableClk(anatop_ai_itf_t itf, bool enable);
177 static void ANATOP_PllConfigure(anatop_ai_itf_t itf,
192 static void ANATOP_PllEnableSs(anatop_ai_itf_t itf, bool enable);
643 static void ANATOP_PllSetPower(anatop_ai_itf_t itf, bool enable) in ANATOP_PllSetPower()
649 static void ANATOP_PllBypass(anatop_ai_itf_t itf, bool bypass) in ANATOP_PllBypass()
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Dfsl_anatop_ai.c14 uint32_t ANATOP_AI_Access(anatop_ai_itf_t itf, bool isWrite, anatop_ai_reg_t addr, uint32_t wdata) in ANATOP_AI_Access()
338 void ANATOP_AI_Write(anatop_ai_itf_t itf, anatop_ai_reg_t addr, uint32_t wdata) in ANATOP_AI_Write()
343 uint32_t ANATOP_AI_Read(anatop_ai_itf_t itf, anatop_ai_reg_t addr) in ANATOP_AI_Read()
351 anatop_ai_itf_t itf, anatop_ai_reg_t addr, uint32_t wdata, uint32_t mask, uint32_t shift) in ANATOP_AI_WriteWithMaskShift()
/hal_nxp-latest/mcux/mcux-sdk/devices/MIMXRT1176/drivers/
Dfsl_anatop_ai.h35 } anatop_ai_itf_t; typedef
490 uint32_t ANATOP_AI_Access(anatop_ai_itf_t itf, bool isWrite, anatop_ai_reg_t addr, uint32_t wdata);
500 void ANATOP_AI_Write(anatop_ai_itf_t itf, anatop_ai_reg_t addr, uint32_t wdata);
510 uint32_t ANATOP_AI_Read(anatop_ai_itf_t itf, anatop_ai_reg_t addr);
523 anatop_ai_itf_t itf, anatop_ai_reg_t addr, uint32_t wdata, uint32_t mask, uint32_t shift);
Dfsl_clock.c171 static void ANATOP_PllSetPower(anatop_ai_itf_t itf, bool enable);
172 static void ANATOP_PllBypass(anatop_ai_itf_t itf, bool bypass);
173 static void ANATOP_PllEnablePllReg(anatop_ai_itf_t itf, bool enable);
174 static void ANATOP_PllHoldRingOff(anatop_ai_itf_t itf, bool off);
175 static void ANATOP_PllToggleHoldRingOff(anatop_ai_itf_t itf, uint32_t delayUsValue);
176 static void ANATOP_PllEnableClk(anatop_ai_itf_t itf, bool enable);
177 static void ANATOP_PllConfigure(anatop_ai_itf_t itf,
192 static void ANATOP_PllEnableSs(anatop_ai_itf_t itf, bool enable);
637 static void ANATOP_PllSetPower(anatop_ai_itf_t itf, bool enable) in ANATOP_PllSetPower()
643 static void ANATOP_PllBypass(anatop_ai_itf_t itf, bool bypass) in ANATOP_PllBypass()
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Dfsl_anatop_ai.c14 uint32_t ANATOP_AI_Access(anatop_ai_itf_t itf, bool isWrite, anatop_ai_reg_t addr, uint32_t wdata) in ANATOP_AI_Access()
338 void ANATOP_AI_Write(anatop_ai_itf_t itf, anatop_ai_reg_t addr, uint32_t wdata) in ANATOP_AI_Write()
343 uint32_t ANATOP_AI_Read(anatop_ai_itf_t itf, anatop_ai_reg_t addr) in ANATOP_AI_Read()
351 anatop_ai_itf_t itf, anatop_ai_reg_t addr, uint32_t wdata, uint32_t mask, uint32_t shift) in ANATOP_AI_WriteWithMaskShift()
/hal_nxp-latest/mcux/mcux-sdk/devices/MIMXRT1173/drivers/
Dfsl_anatop_ai.h35 } anatop_ai_itf_t; typedef
490 uint32_t ANATOP_AI_Access(anatop_ai_itf_t itf, bool isWrite, anatop_ai_reg_t addr, uint32_t wdata);
500 void ANATOP_AI_Write(anatop_ai_itf_t itf, anatop_ai_reg_t addr, uint32_t wdata);
510 uint32_t ANATOP_AI_Read(anatop_ai_itf_t itf, anatop_ai_reg_t addr);
523 anatop_ai_itf_t itf, anatop_ai_reg_t addr, uint32_t wdata, uint32_t mask, uint32_t shift);
Dfsl_clock.c171 static void ANATOP_PllSetPower(anatop_ai_itf_t itf, bool enable);
172 static void ANATOP_PllBypass(anatop_ai_itf_t itf, bool bypass);
173 static void ANATOP_PllEnablePllReg(anatop_ai_itf_t itf, bool enable);
174 static void ANATOP_PllHoldRingOff(anatop_ai_itf_t itf, bool off);
175 static void ANATOP_PllToggleHoldRingOff(anatop_ai_itf_t itf, uint32_t delayUsValue);
176 static void ANATOP_PllEnableClk(anatop_ai_itf_t itf, bool enable);
177 static void ANATOP_PllConfigure(anatop_ai_itf_t itf,
192 static void ANATOP_PllEnableSs(anatop_ai_itf_t itf, bool enable);
637 static void ANATOP_PllSetPower(anatop_ai_itf_t itf, bool enable) in ANATOP_PllSetPower()
643 static void ANATOP_PllBypass(anatop_ai_itf_t itf, bool bypass) in ANATOP_PllBypass()
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Dfsl_anatop_ai.c14 uint32_t ANATOP_AI_Access(anatop_ai_itf_t itf, bool isWrite, anatop_ai_reg_t addr, uint32_t wdata) in ANATOP_AI_Access()
338 void ANATOP_AI_Write(anatop_ai_itf_t itf, anatop_ai_reg_t addr, uint32_t wdata) in ANATOP_AI_Write()
343 uint32_t ANATOP_AI_Read(anatop_ai_itf_t itf, anatop_ai_reg_t addr) in ANATOP_AI_Read()
351 anatop_ai_itf_t itf, anatop_ai_reg_t addr, uint32_t wdata, uint32_t mask, uint32_t shift) in ANATOP_AI_WriteWithMaskShift()
/hal_nxp-latest/mcux/mcux-sdk/devices/MIMXRT1171/drivers/
Dfsl_anatop_ai.h35 } anatop_ai_itf_t; typedef
490 uint32_t ANATOP_AI_Access(anatop_ai_itf_t itf, bool isWrite, anatop_ai_reg_t addr, uint32_t wdata);
500 void ANATOP_AI_Write(anatop_ai_itf_t itf, anatop_ai_reg_t addr, uint32_t wdata);
510 uint32_t ANATOP_AI_Read(anatop_ai_itf_t itf, anatop_ai_reg_t addr);
523 anatop_ai_itf_t itf, anatop_ai_reg_t addr, uint32_t wdata, uint32_t mask, uint32_t shift);
Dfsl_clock.c171 static void ANATOP_PllSetPower(anatop_ai_itf_t itf, bool enable);
172 static void ANATOP_PllBypass(anatop_ai_itf_t itf, bool bypass);
173 static void ANATOP_PllEnablePllReg(anatop_ai_itf_t itf, bool enable);
174 static void ANATOP_PllHoldRingOff(anatop_ai_itf_t itf, bool off);
175 static void ANATOP_PllToggleHoldRingOff(anatop_ai_itf_t itf, uint32_t delayUsValue);
176 static void ANATOP_PllEnableClk(anatop_ai_itf_t itf, bool enable);
177 static void ANATOP_PllConfigure(anatop_ai_itf_t itf,
192 static void ANATOP_PllEnableSs(anatop_ai_itf_t itf, bool enable);
637 static void ANATOP_PllSetPower(anatop_ai_itf_t itf, bool enable) in ANATOP_PllSetPower()
643 static void ANATOP_PllBypass(anatop_ai_itf_t itf, bool bypass) in ANATOP_PllBypass()
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Dfsl_anatop_ai.c14 uint32_t ANATOP_AI_Access(anatop_ai_itf_t itf, bool isWrite, anatop_ai_reg_t addr, uint32_t wdata) in ANATOP_AI_Access()
338 void ANATOP_AI_Write(anatop_ai_itf_t itf, anatop_ai_reg_t addr, uint32_t wdata) in ANATOP_AI_Write()
343 uint32_t ANATOP_AI_Read(anatop_ai_itf_t itf, anatop_ai_reg_t addr) in ANATOP_AI_Read()
351 anatop_ai_itf_t itf, anatop_ai_reg_t addr, uint32_t wdata, uint32_t mask, uint32_t shift) in ANATOP_AI_WriteWithMaskShift()
/hal_nxp-latest/mcux/mcux-sdk/devices/MIMXRT1166/drivers/
Dfsl_anatop_ai.h35 } anatop_ai_itf_t; typedef
490 uint32_t ANATOP_AI_Access(anatop_ai_itf_t itf, bool isWrite, anatop_ai_reg_t addr, uint32_t wdata);
500 void ANATOP_AI_Write(anatop_ai_itf_t itf, anatop_ai_reg_t addr, uint32_t wdata);
510 uint32_t ANATOP_AI_Read(anatop_ai_itf_t itf, anatop_ai_reg_t addr);
523 anatop_ai_itf_t itf, anatop_ai_reg_t addr, uint32_t wdata, uint32_t mask, uint32_t shift);
Dfsl_clock.c171 static void ANATOP_PllSetPower(anatop_ai_itf_t itf, bool enable);
172 static void ANATOP_PllBypass(anatop_ai_itf_t itf, bool bypass);
173 static void ANATOP_PllEnablePllReg(anatop_ai_itf_t itf, bool enable);
174 static void ANATOP_PllHoldRingOff(anatop_ai_itf_t itf, bool off);
175 static void ANATOP_PllToggleHoldRingOff(anatop_ai_itf_t itf, uint32_t delay_us);
176 static void ANATOP_PllEnableClk(anatop_ai_itf_t itf, bool enable);
177 static void ANATOP_PllConfigure(anatop_ai_itf_t itf,
192 static void ANATOP_PllEnableSs(anatop_ai_itf_t itf, bool enable);
643 static void ANATOP_PllSetPower(anatop_ai_itf_t itf, bool enable) in ANATOP_PllSetPower()
649 static void ANATOP_PllBypass(anatop_ai_itf_t itf, bool bypass) in ANATOP_PllBypass()
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Dfsl_anatop_ai.c14 uint32_t ANATOP_AI_Access(anatop_ai_itf_t itf, bool isWrite, anatop_ai_reg_t addr, uint32_t wdata) in ANATOP_AI_Access()
338 void ANATOP_AI_Write(anatop_ai_itf_t itf, anatop_ai_reg_t addr, uint32_t wdata) in ANATOP_AI_Write()
343 uint32_t ANATOP_AI_Read(anatop_ai_itf_t itf, anatop_ai_reg_t addr) in ANATOP_AI_Read()
351 anatop_ai_itf_t itf, anatop_ai_reg_t addr, uint32_t wdata, uint32_t mask, uint32_t shift) in ANATOP_AI_WriteWithMaskShift()
/hal_nxp-latest/mcux/mcux-sdk/devices/MIMXRT1175/drivers/
Dfsl_anatop_ai.h35 } anatop_ai_itf_t; typedef
490 uint32_t ANATOP_AI_Access(anatop_ai_itf_t itf, bool isWrite, anatop_ai_reg_t addr, uint32_t wdata);
500 void ANATOP_AI_Write(anatop_ai_itf_t itf, anatop_ai_reg_t addr, uint32_t wdata);
510 uint32_t ANATOP_AI_Read(anatop_ai_itf_t itf, anatop_ai_reg_t addr);
523 anatop_ai_itf_t itf, anatop_ai_reg_t addr, uint32_t wdata, uint32_t mask, uint32_t shift);
Dfsl_clock.c171 static void ANATOP_PllSetPower(anatop_ai_itf_t itf, bool enable);
172 static void ANATOP_PllBypass(anatop_ai_itf_t itf, bool bypass);
173 static void ANATOP_PllEnablePllReg(anatop_ai_itf_t itf, bool enable);
174 static void ANATOP_PllHoldRingOff(anatop_ai_itf_t itf, bool off);
175 static void ANATOP_PllToggleHoldRingOff(anatop_ai_itf_t itf, uint32_t delayUsValue);
176 static void ANATOP_PllEnableClk(anatop_ai_itf_t itf, bool enable);
177 static void ANATOP_PllConfigure(anatop_ai_itf_t itf,
192 static void ANATOP_PllEnableSs(anatop_ai_itf_t itf, bool enable);
637 static void ANATOP_PllSetPower(anatop_ai_itf_t itf, bool enable) in ANATOP_PllSetPower()
643 static void ANATOP_PllBypass(anatop_ai_itf_t itf, bool bypass) in ANATOP_PllBypass()
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Dfsl_anatop_ai.c14 uint32_t ANATOP_AI_Access(anatop_ai_itf_t itf, bool isWrite, anatop_ai_reg_t addr, uint32_t wdata) in ANATOP_AI_Access()
338 void ANATOP_AI_Write(anatop_ai_itf_t itf, anatop_ai_reg_t addr, uint32_t wdata) in ANATOP_AI_Write()
343 uint32_t ANATOP_AI_Read(anatop_ai_itf_t itf, anatop_ai_reg_t addr) in ANATOP_AI_Read()
351 anatop_ai_itf_t itf, anatop_ai_reg_t addr, uint32_t wdata, uint32_t mask, uint32_t shift) in ANATOP_AI_WriteWithMaskShift()