Searched refs:_u32 (Results 1 – 9 of 9) sorted by relevance
39 uint32_t _u32; member211 base->MDA_DFMT0[master].MDA_W_DFMT0[regNum] = pid._u32 | TRDC_MDA_W_DFMT0_VLD_MASK; in TRDC_SetProcessorDomainAssignment()213 base->MDA_W0_0_DFMT0 = pid._u32 | TRDC_MDA_W0_0_DFMT0_VLD_MASK; in TRDC_SetProcessorDomainAssignment()254 base->MDA_DFMT1[master].MDA_W_DFMT1[0] = pid._u32 | TRDC_MDA_W_DFMT1_VLD_MASK; in TRDC_SetNonProcessorDomainAssignment()256 base->MDA_W0_DFMT1[master - 1U].MDA_W0_x_DFMT1 = pid._u32 | TRDC_MDA_W0_x_DFMT1_VLD_MASK; in TRDC_SetNonProcessorDomainAssignment()279 base->PID[master] = pid._u32; in TRDC_SetPid()329 base->TRDC_IDAU_CR = pid._u32 | TRDC_TRDC_IDAU_CR_VLD_MASK; in TRDC_SetIDAU()578 base->MRC_INDEX[mrcIdx].MRC_GLBAC[regIdx] = pid._u32; in TRDC_MrcSetMemoryAccessConfig()714 base->MBC_INDEX[mbcIdx].MBC_NSE_BLK_INDEX = pid._u32; in TRDC_MbcSetNseUpdateConfig()811 base->MBC_INDEX[mbcIdx].MBC_MEMN_GLBAC[rgdIdx] = pid._u32; in TRDC_MbcSetMemoryAccessConfig()[all …]
49 uint32_t _u32; member204 …TRDC_DOMAIN_ASSIGNMENT_BASE(base)->MDA_DFMT0[master].MDA_W_DFMT0[regNum] = pid._u32 | TRDC_MDA_W_D… in TRDC_SetProcessorDomainAssignment()245 …TRDC_DOMAIN_ASSIGNMENT_BASE(base)->MDA_DFMT1[master].MDA_W_DFMT1[0] = pid._u32 | TRDC_MDA_W_DFMT1_… in TRDC_SetNonProcessorDomainAssignment()274 TRDC_DOMAIN_ASSIGNMENT_BASE(base)->PID[master] = pid._u32; in TRDC_SetPid()325 TRDC_GENERAL_BASE(base)->TRDC_IDAU_CR = pid._u32 | TRDC_TRDC_IDAU_CR_VLD_MASK; in TRDC_SetIDAU()584 TRDC_MRC_BASE(base, mrcIdx)->MRC_GLBAC[regIdx] = pid._u32; in TRDC_MrcSetMemoryAccessConfig()723 TRDC_MBC_BASE(base, mbcIdx)->MBC_NSE_BLK_INDEX = pid._u32; in TRDC_MbcSetNseUpdateConfig()825 TRDC_MBC_BASE(base, mbcIdx)->MBC_MEMN_GLBAC[rgdIdx] = pid._u32; in TRDC_MbcSetMemoryAccessConfig()847 configWord = (pid._u32 & 0xFU) << shift; in TRDC_MbcSetMemoryBlockConfig()
22 uint32_t _u32; member28 uint32_t _u32; member118 vir._u32 = base->VIR; in RDC_GetHardwareConfig()138 base->MDA[master] = mda._u32; in RDC_SetMasterDomainAssignment()157 mda._u32 = 0U; in RDC_GetDefaultMasterDomainAssignment()
40 uint32_t _u32; member47 uint32_t _u32; member268 pid._u32 = 0U; in XRDC_GetPidDefaultConfig()290 base->PID[master] = pid._u32; in XRDC_SetPidConfig()318 mda._u32 = 0U; in XRDC_GetDefaultNonProcessorDomainAssignment()349 mda._u32 = 0U; in XRDC_GetDefaultProcessorDomainAssignment()392 base->MDA[master].MDA_W[assignIndex] = (mda._u32 | XRDC_MDA_W_VLD_MASK); in XRDC_SetNonProcessorDomainAssignment()443 base->MDA[master].MDA_W[assignIndex] = (mda._u32 | XRDC_MDA_W_VLD_MASK); in XRDC_SetProcessorDomainAssignment()
32 uint32_t _u32; member184 base->FIFOCTRL.RW = pid._u32; in EPDC_ConfigFifo()297 uint32_t dataAddr = (uint32_t) & (pid._u32); in EPDC_ConfigPigeon()373 uint32_t dataAddr = (uint32_t) & (pid._u32); in EPDC_UpdateDisplay()411 base->AUTOWV_LUT = pid._u32; in EPDC_SetAutowaveMap()427 base->GPIO.RW = pid._u32; in EPDC_SetGpioOutput()
28 uint32_t _u32; member324 base->VIDEOGLOBALALPHA = (uint32_t)(pid._u32 >> 16U); in LCDIF_SetFrameBufferConfig()325 base->VIDEOALPHABLENDCONFIG = (pid._u32 & 0xFFFFUL); in LCDIF_SetFrameBufferConfig()383 base->OVERLAYGLOBALALPHA = (uint32_t)(pid._u32 >> 16U); in LCDIF_SetOverlayLayerConfig()384 base->OVERLAYALPHABLENDCONFIG = (pid._u32 & 0xFFFFUL); in LCDIF_SetOverlayLayerConfig()398 base->OVERLAYGLOBALALPHA1 = (uint32_t)(pid._u32 >> 16U); in LCDIF_SetOverlayLayerConfig()399 base->OVERLAYALPHABLENDCONFIG1 = (pid._u32 & 0xFFFFUL); in LCDIF_SetOverlayLayerConfig()538 pid._u32 = pdCtrl[(uint32_t)mode] | in LCDIF_GetPorterDuffConfig()
15 file(GLOB SRCU32 "./*_u32.c")
2042 uint32_t _u32; in PXP_SetDitherConfig() member2048 base->DITHER_CTRL = pid._u32 & 0x00FFFFFFU; in PXP_SetDitherConfig()
