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Searched refs:__ROR (Results 1 – 25 of 33) sorted by relevance

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/hal_nxp-latest/mcux/mcux-sdk/CMSIS/DSP/Source/SupportFunctions/
Darm_q7_to_q31.c120 *pDst++ = (__ROR(in, 8)) & 0xFF000000; in arm_q7_to_q31()
121 *pDst++ = (__ROR(in, 16)) & 0xFF000000; in arm_q7_to_q31()
122 *pDst++ = (__ROR(in, 24)) & 0xFF000000; in arm_q7_to_q31()
128 *pDst++ = (__ROR(in, 24)) & 0xFF000000; in arm_q7_to_q31()
129 *pDst++ = (__ROR(in, 16)) & 0xFF000000; in arm_q7_to_q31()
130 *pDst++ = (__ROR(in, 8)) & 0xFF000000; in arm_q7_to_q31()
Darm_q7_to_q15.c127 in1 = __SXTB16(__ROR(in, 8)); in arm_q7_to_q15()
/hal_nxp-latest/mcux/mcux-sdk/CMSIS/NN/Source/ConvolutionFunctions/
Darm_depthwise_separable_conv_HWC_q7.c181 opA = __SXTB16(__ROR(inA1, 8)); in arm_depthwise_separable_conv_HWC_q7()
182 opB = __SXTB16(__ROR(inB1, 8)); in arm_depthwise_separable_conv_HWC_q7()
187 opA = __SXTB16(__ROR(inA2, 8)); in arm_depthwise_separable_conv_HWC_q7()
188 opB = __SXTB16(__ROR(inB2, 8)); in arm_depthwise_separable_conv_HWC_q7()
213 opA = __SXTB16(__ROR(inA1, 8)); in arm_depthwise_separable_conv_HWC_q7()
214 opB = __SXTB16(__ROR(inB1, 8)); in arm_depthwise_separable_conv_HWC_q7()
219 opA = __SXTB16(__ROR(inA2, 8)); in arm_depthwise_separable_conv_HWC_q7()
220 opB = __SXTB16(__ROR(inB2, 8)); in arm_depthwise_separable_conv_HWC_q7()
Darm_depthwise_separable_conv_HWC_q7_nonsquare.c191 opA = __SXTB16(__ROR(inA1, 8)); in arm_depthwise_separable_conv_HWC_q7_nonsquare()
192 opB = __SXTB16(__ROR(inB1, 8)); in arm_depthwise_separable_conv_HWC_q7_nonsquare()
197 opA = __SXTB16(__ROR(inA2, 8)); in arm_depthwise_separable_conv_HWC_q7_nonsquare()
198 opB = __SXTB16(__ROR(inB2, 8)); in arm_depthwise_separable_conv_HWC_q7_nonsquare()
223 opA = __SXTB16(__ROR(inA1, 8)); in arm_depthwise_separable_conv_HWC_q7_nonsquare()
224 opB = __SXTB16(__ROR(inB1, 8)); in arm_depthwise_separable_conv_HWC_q7_nonsquare()
229 opA = __SXTB16(__ROR(inA2, 8)); in arm_depthwise_separable_conv_HWC_q7_nonsquare()
230 opB = __SXTB16(__ROR(inB2, 8)); in arm_depthwise_separable_conv_HWC_q7_nonsquare()
Darm_depthwise_conv_s8_opt.c298 ip_b1 = __SXTB16(__ROR(ip_b1, 8)); in arm_depthwise_conv_s8_opt()
301 ip_a1 = __SXTB16(__ROR(ip_a1, 8)); in arm_depthwise_conv_s8_opt()
/hal_nxp-latest/mcux/mcux-sdk/CMSIS/NN/Source/FullyConnectedFunctions/
Darm_fully_connected_q7_opt.c172 inM12 = __SXTB16(__ROR(inM11, 8)); in arm_fully_connected_q7_opt()
177 inM14 = __SXTB16(__ROR(inM13, 8)); in arm_fully_connected_q7_opt()
184 inM12 = __SXTB16(__ROR(inM11, 8)); in arm_fully_connected_q7_opt()
189 inM14 = __SXTB16(__ROR(inM13, 8)); in arm_fully_connected_q7_opt()
203 inM12 = __SXTB16(__ROR(inM11, 8)); in arm_fully_connected_q7_opt()
208 inM14 = __SXTB16(__ROR(inM13, 8)); in arm_fully_connected_q7_opt()
215 inM12 = __SXTB16(__ROR(inM11, 8)); in arm_fully_connected_q7_opt()
220 inM14 = __SXTB16(__ROR(inM13, 8)); in arm_fully_connected_q7_opt()
Darm_fully_connected_mat_q7_vec_q15_opt.c160 inM12 = __SXTB16(__ROR(inM11, 8)); in arm_fully_connected_mat_q7_vec_q15_opt()
165 inM14 = __SXTB16(__ROR(inM13, 8)); in arm_fully_connected_mat_q7_vec_q15_opt()
181 inM12 = __SXTB16(__ROR(inM11, 8)); in arm_fully_connected_mat_q7_vec_q15_opt()
186 inM14 = __SXTB16(__ROR(inM13, 8)); in arm_fully_connected_mat_q7_vec_q15_opt()
/hal_nxp-latest/mcux/mcux-sdk/CMSIS/DSP/Source/MatrixFunctions/
Darm_mat_vec_mult_q7.c329 vecData2 = __SXTB16(__ROR(vecData, 8)); in arm_mat_vec_mult_q7()
333 matData2 = __SXTB16(__ROR(matData, 8)); in arm_mat_vec_mult_q7()
338 matData2 = __SXTB16(__ROR(matData, 8)); in arm_mat_vec_mult_q7()
343 matData2 = __SXTB16(__ROR(matData, 8)); in arm_mat_vec_mult_q7()
348 matData2 = __SXTB16(__ROR(matData, 8)); in arm_mat_vec_mult_q7()
395 vecData2 = __SXTB16(__ROR(vecData, 8)); in arm_mat_vec_mult_q7()
398 matData2 = __SXTB16(__ROR(matData, 8)); in arm_mat_vec_mult_q7()
/hal_nxp-latest/mcux/mcux-sdk/CMSIS/NN/Include/
Darm_nnsupportfunctions.h574 q31_t inAbuf1 = __SXTB16(__ROR((uint32_t)inA, 8)); in read_and_pad()
596 *out2 = __SXTB16(__ROR((uint32_t)inA, 8)); in read_and_pad_reordered()
599 *out1 = __SXTB16(__ROR((uint32_t)inA, 8)); in read_and_pad_reordered()
615 *out2 = __SXTB16(__ROR((uint32_t)inA, 8)); in read_and_pad_reordered_with_offset()
618 *out1 = __SXTB16(__ROR((uint32_t)inA, 8)); in read_and_pad_reordered_with_offset()
/hal_nxp-latest/mcux/mcux-sdk/CMSIS/DSP/Source/BasicMathFunctions/
Darm_dot_prod_q7.c137 inA1 = __SXTB16(__ROR(input1, 8)); in arm_dot_prod_q7()
141 inB1 = __SXTB16(__ROR(input2, 8)); in arm_dot_prod_q7()
/hal_nxp-latest/mcux/mcux-sdk/CMSIS/Core/Include/
Dcmsis_armclang.h241 #define __REV16(value) __ROR(__REV(value), 16)
260 __STATIC_FORCEINLINE uint32_t __ROR(uint32_t op1, uint32_t op2) in __ROR() function
1487 #define __SXTB16_RORn(ARG1, ARG2) __SXTB16(__ROR(ARG1, ARG2))
1489 #define __SXTAB16_RORn(ARG1, ARG2, ARG3) __SXTAB16(ARG1, __ROR(ARG2, ARG3))
Dcmsis_armcc.h238 #define __ROR __ror macro
880 #define __SXTB16_RORn(ARG1, ARG2) __SXTB16(__ROR(ARG1, ARG2))
882 #define __SXTAB16_RORn(ARG1, ARG2, ARG3) __SXTAB16(ARG1, __ROR(ARG2, ARG3))
Dcmsis_iccarm.h441 #define __ROR __iar_builtin_ROR macro
648 __IAR_FT uint32_t __ROR(uint32_t op1, uint32_t op2) in __ROR() function
998 #define __SXTB16_RORn(ARG1, ARG2) __SXTB16(__ROR(ARG1, ARG2))
1000 #define __SXTAB16_RORn(ARG1, ARG2, ARG3) __SXTAB16(ARG1, __ROR(ARG2, ARG3))
Dcmsis_armclang_ltm.h239 #define __REV16(value) __ROR(__REV(value), 16)
258 __STATIC_FORCEINLINE uint32_t __ROR(uint32_t op1, uint32_t op2) in __ROR() function
1912 #define __SXTB16_RORn(ARG1, ARG2) __SXTB16(__ROR(ARG1, ARG2))
1914 #define __SXTAB16_RORn(ARG1, ARG2, ARG3) __SXTAB16(ARG1, __ROR(ARG2, ARG3))
/hal_nxp-latest/mcux/mcux-sdk/CMSIS/NN/Source/NNSupportFunctions/
Darm_nn_vec_mat_mult_t_svdf_s8.c229 int32_t vec_1 = __SXTAB16(lhs_offset_s16x2, __ROR((uint32_t)vec_0, 8)); in arm_nn_vec_mat_mult_t_svdf_s8()
232 int32_t ker_1 = __SXTAB16(rhs_offset_s16x2, __ROR((uint32_t)ker_0, 8)); in arm_nn_vec_mat_mult_t_svdf_s8()
Darm_nn_add_q7.c55 q31_t temp_q15x2 = __SXTAB16(__SXTB16(in_q7x4), __ROR((uint32_t)in_q7x4, 8)); in arm_nn_add_q7()
Darm_q7_to_q15_reordered_no_shift.c100 in1 = __SXTB16(__ROR((uint32_t)in, 8)); in arm_q7_to_q15_reordered_no_shift()
Darm_q7_to_q15_reordered_with_offset.c71 out_q15x2_1 = __SXTAB16(offset_q15x2, __ROR((uint32_t)in_q7x4, 8)); in arm_q7_to_q15_reordered_with_offset()
Darm_q7_to_q15_no_shift.c77 in1 = __SXTB16(__ROR((uint32_t)in, 8)); in arm_q7_to_q15_no_shift()
Darm_nn_accumulate_q7_to_q15.c54 v1 = __SXTB16(__ROR((uint32_t)value, 8)); in arm_nn_accumulate_q7_to_q15()
Darm_q7_to_q15_with_offset.c83 in_q15x2_1 = __SXTAB16(offset_q15x2, __ROR(in_q7x4, 8)); in arm_q7_to_q15_with_offset()
/hal_nxp-latest/mcux/mcux-sdk/CMSIS/NN/Source/ActivationFunctions/
Darm_relu_q15.c72 buf = __ROR(in & 0x80008000, 15); in arm_relu_q15()
Darm_relu_q7.c72 buf = (int32_t)__ROR((uint32_t)in & 0x80808080, 7); in arm_relu_q7()
/hal_nxp-latest/mcux/mcux-sdk/CMSIS/DSP/Source/StatisticsFunctions/
Darm_power_q7.c127 in1 = __SXTB16(__ROR(in32, 8)); in arm_power_q7()
/hal_nxp-latest/mcux/mcux-sdk/CMSIS/Include/
Dcmsis_armclang.h883 #define __REV16(value) __ROR(__REV(value), 16)
902 __STATIC_FORCEINLINE uint32_t __ROR(uint32_t op1, uint32_t op2) in __ROR() function

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