| /hal_nxp-latest/mcux/mcux-sdk/drivers/trdc_1/ |
| D | fsl_trdc_core.h | 54 … __O uint32_t W3; /**< MBC Domain Error Word3 Register, array offset: 0x40C, array step: 0x10 */
61 … __O uint32_t W3; /**< MRC Domain Error Word3 Register, array offset: 0x48C, array step: 0x10 */
92 …__O uint32_t MBC_NSE_BLK_SET; /**< MBC NonSecure Enable Block Set, array offset: 0x10014, array…
93 …__O uint32_t MBC_NSE_BLK_CLR; /**< MBC NonSecure Enable Block Clear, array offset: 0x10018, arr…
94 __O uint32_t
379 …__O uint32_t MRC_NSE_RGN_SET; /**< MRC NonSecure Enable Region Set, array offset: 0x14014, array s…
380 …__O uint32_t MRC_NSE_RGN_CLR; /**< MRC NonSecure Enable Region Clear, array offset: 0x14018, array…
381 __O uint32_t
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| /hal_nxp-latest/s32/drivers/s32ze/BaseNXP/header/ |
| D | S32Z2_I3C.h | 84 __O uint32_t SWDATAB; /**< Target Write Data Byte, offset: 0x30 */
85 __O uint32_t SWDATABE; /**< Target Write Data Byte End, offset: 0x34 */
86 __O uint32_t SWDATAH; /**< Target Write Data Halfword, offset: 0x38 */
87 …__O uint32_t SWDATAHE; /**< Target Write Data Halfword End, offset: 0x3C…
96 __O uint32_t SWDATAB1; /**< Target Write Data Byte, offset: 0x54 */
116 __O uint32_t MWDATAB; /**< Controller Write Data Byte, offset: 0xB0 */
117 …__O uint32_t MWDATABE; /**< Controller Write Data Byte End, offset: 0xB4…
118 …__O uint32_t MWDATAH; /**< Controller Write Data Halfword, offset: 0xB8…
119 …__O uint32_t MWDATAHE; /**< Controller Write Data Halfword End, offset: …
123 …__O uint32_t MWDATAB1; /**< Controller Write Byte Data 1 (to Bus), offse…
[all …]
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| D | S32Z2_SCB.h | 113 …__O uint32_t STIR; /**< Software Triggered Interrupt Register, offse…
119 …__O uint32_t ICIALLU; /**< Instruction cache invalidate all to Point of…
121 …__O uint32_t ICIMVAU; /**< Instruction cache invalidate by address to P…
122 …__O uint32_t DCIMVAC; /**< Data cache invalidate by address to Point of…
123 …__O uint32_t DCISW; /**< Data cache invalidate by set/way, offset: 0x…
124 …__O uint32_t DCCMVAU; /**< Data cache by address to PoU, offset: 0xF64 …
125 …__O uint32_t DCCMVAC; /**< Data cache clean by address to PoC, offset: …
126 …__O uint32_t DCCSW; /**< Data cache clean by set/way, offset: 0xF6C */
127 …__O uint32_t DCCIMVAC; /**< Data cache clean and invalidate by address t…
128 …__O uint32_t DCCISW; /**< Data cache clean and invalidate by set/way, …
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| D | S32Z2_DBG.h | 74 …__O uint32_t DBGACS; /**< Error Access Control Register, offset: 0x4 */
95 …__O uint32_t CENSIRQ_S; /**< Critical Error Interrupt Request Shadow Regi…
96 …__O uint32_t CENSIRQ2_S; /**< Critical Error Interrupt Request 2 Shadow Re…
97 …__O uint32_t CWDOGIRQ_S; /**< Critical Error Interrupt Request Shadow Regi…
98 …__O uint32_t NENSIRQ_S; /**< Normal Error Interrupt Requests Shadow Regis…
99 …__O uint32_t TIMER_IRQ_S; /**< Timer Interrupt Shadow Register, offset: 0x7…
100 …__O uint32_t DMA_IRQ_S; /**< DMA Interrupt Shadow Register, offset: 0x74 …
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| /hal_nxp-latest/s32/drivers/s32k3/BaseNXP/header/ |
| D | S32K344_SCB.h | 111 …__O uint32_t STIR; /**< Software Triggered Interrupt Register, offse…
117 …__O uint32_t ICIALLU; /**< Instruction cache invalidate all to Point of…
119 …__O uint32_t ICIMVAU; /**< Instruction cache invalidate by address to P…
120 …__O uint32_t DCIMVAC; /**< Data cache invalidate by address to Point of…
121 …__O uint32_t DCISW; /**< Data cache invalidate by set/way, offset: 0x…
122 …__O uint32_t DCCMVAU; /**< Data cache by address to PoU, offset: 0xF64 …
123 …__O uint32_t DCCMVAC; /**< Data cache clean by address to PoC, offset: …
124 …__O uint32_t DCCSW; /**< Data cache clean by set/way, offset: 0xF6C */
125 …__O uint32_t DCCIMVAC; /**< Data cache clean and invalidate by address t…
126 …__O uint32_t DCCISW; /**< Data cache clean and invalidate by set/way, …
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| D | S32K344_MSCM.h | 93 …__O uint32_t IRCP0IGR0; /**< Interrupt Router CP0 Interrupt Generation, o…
95 …__O uint32_t IRCP0IGR1; /**< Interrupt Router CP0 Interrupt Generation, o…
97 …__O uint32_t IRCP0IGR2; /**< Interrupt Router CP0 Interrupt Generation, o…
99 …__O uint32_t IRCP0IGR3; /**< Interrupt Router CP0 Interrupt Generation, o…
101 …__O uint32_t IRCP1IGR0; /**< Interrupt Router CP1 Interrupt Generation, o…
103 …__O uint32_t IRCP1IGR1; /**< Interrupt Router CP1 Interrupt Generation, o…
105 …__O uint32_t IRCP1IGR2; /**< Interrupt Router CP1 Interrupt Generation, o…
107 …__O uint32_t IRCP1IGR3; /**< Interrupt Router CP1 Interrupt Generation, o…
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| /hal_nxp-latest/s32/drivers/s32k1/BaseNXP/header/ |
| D | S32K118_DMA.h | 83 …__O uint8_t CEEI; /**< Clear Enable Error Interrupt, offset: 0x18 */
84 __O uint8_t SEEI; /**< Set Enable Error Interrupt, offset: 0x19 */
85 __O uint8_t CERQ; /**< Clear Enable Request, offset: 0x1A */
86 __O uint8_t SERQ; /**< Set Enable Request, offset: 0x1B */
87 __O uint8_t CDNE; /**< Clear DONE Status Bit, offset: 0x1C */
88 __O uint8_t SSRT; /**< Set START Bit, offset: 0x1D */
89 __O uint8_t CERR; /**< Clear Error, offset: 0x1E */
90 __O uint8_t CINT; /**< Clear Interrupt Request, offset: 0x1F */
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| D | S32K116_DMA.h | 83 …__O uint8_t CEEI; /**< Clear Enable Error Interrupt, offset: 0x18 */
84 __O uint8_t SEEI; /**< Set Enable Error Interrupt, offset: 0x19 */
85 __O uint8_t CERQ; /**< Clear Enable Request, offset: 0x1A */
86 __O uint8_t SERQ; /**< Set Enable Request, offset: 0x1B */
87 __O uint8_t CDNE; /**< Clear DONE Status Bit, offset: 0x1C */
88 __O uint8_t SSRT; /**< Set START Bit, offset: 0x1D */
89 __O uint8_t CERR; /**< Clear Error, offset: 0x1E */
90 __O uint8_t CINT; /**< Clear Interrupt Request, offset: 0x1F */
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| D | S32K144_PORT.h | 77 …__O uint32_t GPCLR; /**< Global Pin Control Low Register, offset: 0x8…
78 …__O uint32_t GPCHR; /**< Global Pin Control High Register, offset: 0x…
79 …__O uint32_t GICLR; /**< Global Interrupt Control Low Register, offse…
80 …__O uint32_t GICHR; /**< Global Interrupt Control High Register, offs…
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| D | S32K142W_PORT.h | 77 …__O uint32_t GPCLR; /**< Global Pin Control Low Register, offset: 0x8…
78 …__O uint32_t GPCHR; /**< Global Pin Control High Register, offset: 0x…
79 …__O uint32_t GICLR; /**< Global Interrupt Control Low Register, offse…
80 …__O uint32_t GICHR; /**< Global Interrupt Control High Register, offs…
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| D | S32K116_PORT.h | 77 …__O uint32_t GPCLR; /**< Global Pin Control Low Register, offset: 0x8…
78 …__O uint32_t GPCHR; /**< Global Pin Control High Register, offset: 0x…
79 …__O uint32_t GICLR; /**< Global Interrupt Control Low Register, offse…
80 …__O uint32_t GICHR; /**< Global Interrupt Control High Register, offs…
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| D | S32K118_PORT.h | 77 …__O uint32_t GPCLR; /**< Global Pin Control Low Register, offset: 0x8…
78 …__O uint32_t GPCHR; /**< Global Pin Control High Register, offset: 0x…
79 …__O uint32_t GICLR; /**< Global Interrupt Control Low Register, offse…
80 …__O uint32_t GICHR; /**< Global Interrupt Control High Register, offs…
|
| D | S32K148_PORT.h | 77 …__O uint32_t GPCLR; /**< Global Pin Control Low Register, offset: 0x8…
78 …__O uint32_t GPCHR; /**< Global Pin Control High Register, offset: 0x…
79 …__O uint32_t GICLR; /**< Global Interrupt Control Low Register, offse…
80 …__O uint32_t GICHR; /**< Global Interrupt Control High Register, offs…
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| D | S32K142_PORT.h | 77 …__O uint32_t GPCLR; /**< Global Pin Control Low Register, offset: 0x8…
78 …__O uint32_t GPCHR; /**< Global Pin Control High Register, offset: 0x…
79 …__O uint32_t GICLR; /**< Global Interrupt Control Low Register, offse…
80 …__O uint32_t GICHR; /**< Global Interrupt Control High Register, offs…
|
| D | S32K146_PORT.h | 77 …__O uint32_t GPCLR; /**< Global Pin Control Low Register, offset: 0x8…
78 …__O uint32_t GPCHR; /**< Global Pin Control High Register, offset: 0x…
79 …__O uint32_t GICLR; /**< Global Interrupt Control Low Register, offse…
80 …__O uint32_t GICHR; /**< Global Interrupt Control High Register, offs…
|
| D | S32K144W_PORT.h | 77 …__O uint32_t GPCLR; /**< Global Pin Control Low Register, offset: 0x8…
78 …__O uint32_t GPCHR; /**< Global Pin Control High Register, offset: 0x…
79 …__O uint32_t GICLR; /**< Global Interrupt Control Low Register, offse…
80 …__O uint32_t GICHR; /**< Global Interrupt Control High Register, offs…
|
| D | S32K118_GPIO.h | 74 __O uint32_t PSOR; /**< Port Set Output Register, offset: 0x4 */
75 __O uint32_t PCOR; /**< Port Clear Output Register, offset: 0x8 */
76 __O uint32_t PTOR; /**< Port Toggle Output Register, offset: 0xC */
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| D | S32K116_GPIO.h | 74 __O uint32_t PSOR; /**< Port Set Output Register, offset: 0x4 */
75 __O uint32_t PCOR; /**< Port Clear Output Register, offset: 0x8 */
76 __O uint32_t PTOR; /**< Port Toggle Output Register, offset: 0xC */
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| D | S32K142_GPIO.h | 74 __O uint32_t PSOR; /**< Port Set Output Register, offset: 0x4 */
75 __O uint32_t PCOR; /**< Port Clear Output Register, offset: 0x8 */
76 __O uint32_t PTOR; /**< Port Toggle Output Register, offset: 0xC */
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| D | S32K148_GPIO.h | 74 __O uint32_t PSOR; /**< Port Set Output Register, offset: 0x4 */
75 __O uint32_t PCOR; /**< Port Clear Output Register, offset: 0x8 */
76 __O uint32_t PTOR; /**< Port Toggle Output Register, offset: 0xC */
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| D | S32K146_GPIO.h | 74 __O uint32_t PSOR; /**< Port Set Output Register, offset: 0x4 */
75 __O uint32_t PCOR; /**< Port Clear Output Register, offset: 0x8 */
76 __O uint32_t PTOR; /**< Port Toggle Output Register, offset: 0xC */
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| D | S32K142W_GPIO.h | 74 __O uint32_t PSOR; /**< Port Set Output Register, offset: 0x4 */
75 __O uint32_t PCOR; /**< Port Clear Output Register, offset: 0x8 */
76 __O uint32_t PTOR; /**< Port Toggle Output Register, offset: 0xC */
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| D | S32K144W_GPIO.h | 74 __O uint32_t PSOR; /**< Port Set Output Register, offset: 0x4 */
75 __O uint32_t PCOR; /**< Port Clear Output Register, offset: 0x8 */
76 __O uint32_t PTOR; /**< Port Toggle Output Register, offset: 0xC */
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| D | S32K144_GPIO.h | 74 __O uint32_t PSOR; /**< Port Set Output Register, offset: 0x4 */
75 __O uint32_t PCOR; /**< Port Clear Output Register, offset: 0x8 */
76 __O uint32_t PTOR; /**< Port Toggle Output Register, offset: 0xC */
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| /hal_nxp-latest/mcux/mcux-sdk/drivers/lpc_crc/ |
| D | fsl_crc.c | 162 *((__O uint8_t *)&(base->WR_DATA)) = *data; in CRC_WriteData()
171 *((__O uint32_t *)&(base->WR_DATA)) = *data32; in CRC_WriteData()
181 *((__O uint8_t *)&(base->WR_DATA)) = *data; in CRC_WriteData()
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