Searched refs:__MSR (Results 1 – 5 of 5) sorted by relevance
| /hal_nxp-latest/mcux/mcux-sdk/CMSIS/Core_AArch64/Include/ |
| D | timer_armv8a.h | 63 __MSR(CNTP_TVAL_EL0, val); in ARM_TIMER_SetInterval()
66 __MSR(CNTV_TVAL_EL0, val); in ARM_TIMER_SetInterval()
69 __MSR(CNTHP_TVAL_EL2, val); in ARM_TIMER_SetInterval()
72 __MSR(CNTPS_TVAL_EL1, val); in ARM_TIMER_SetInterval()
111 __MSR(CNTP_CTL_EL0, ctl); in ARM_TIMER_Start()
114 __MSR(CNTV_CTL_EL0, ctl); in ARM_TIMER_Start()
117 __MSR(CNTHP_CTL_EL2, ctl); in ARM_TIMER_Start()
120 __MSR(CNTPS_CTL_EL1, ctl); in ARM_TIMER_Start()
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| D | gic_v3.h | 599 __MSR(ICC_SGI1R_EL1, val); in GIC_SendSGI_ARE()
819 __MSR(ICC_IGRPEN1_EL1, 1); in GIC_EnableInterface()
826 __MSR(ICC_IGRPEN1_EL1, 0); in GIC_DisableInterface()
844 __MSR(ICC_EOIR1_EL1, (uint32_t)IRQn); in GIC_EndInterrupt()
852 __MSR(ICC_PMR_EL1, priority & 0xFFUL); in GIC_SetInterfacePriorityMask()
870 __MSR(ICC_BPR1_EL1, binary_point & 7U); in GIC_SetBinaryPoint()
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| D | cmsis_gcc.h | 53 #ifndef __MSR
54 #define __MSR(sysreg, val) \ macro
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| /hal_nxp-latest/mcux/mcux-sdk/CMSIS/Core_AArch64/Source/ |
| D | mmu_armv8a.c | 628 __MSR(MAIR_EL1, MEMORY_ATTRIBUTES); in enable_mmu_el1()
629 __MSR(TCR_EL1, get_tcr(1)); in enable_mmu_el1()
630 __MSR(TTBR0_EL1, (uint64_t)ptables->base_xlat_table); in enable_mmu_el1()
637 __MSR(SCTLR_EL1, val | SCTLR_M_BIT | SCTLR_C_BIT | SCTLR_I_BIT); in enable_mmu_el1()
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| D | cache_armv8a.c | 75 __MSR(CSSELR_EL1, csselr_el1); in dcache_all()
119 __MSR(CSSELR_EL1, 0); in dcache_all()
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