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Searched refs:__IOM (Results 1 – 25 of 36) sorted by relevance

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/hal_nxp-latest/mcux/mcux-sdk/CMSIS/Include/
Dcore_cm35p.h281 #define __IOM volatile /*! Defines 'read / write' structure member permissions */ macro
463 __IOM uint32_t ISER[16U]; /*!< Offset: 0x000 (R/W) Interrupt Set Enable Register */
465 …__IOM uint32_t ICER[16U]; /*!< Offset: 0x080 (R/W) Interrupt Clear Enable Register */
467 __IOM uint32_t ISPR[16U]; /*!< Offset: 0x100 (R/W) Interrupt Set Pending Register */
469 …__IOM uint32_t ICPR[16U]; /*!< Offset: 0x180 (R/W) Interrupt Clear Pending Register …
471 __IOM uint32_t IABR[16U]; /*!< Offset: 0x200 (R/W) Interrupt Active bit Register */
473 …__IOM uint32_t ITNS[16U]; /*!< Offset: 0x280 (R/W) Interrupt Non-Secure State Regist…
475 …__IOM uint8_t IPR[496U]; /*!< Offset: 0x300 (R/W) Interrupt Priority Register (8Bit…
500 …__IOM uint32_t ICSR; /*!< Offset: 0x004 (R/W) Interrupt Control and State Regis…
501 __IOM uint32_t VTOR; /*!< Offset: 0x008 (R/W) Vector Table Offset Register */
[all …]
Dcore_cm33.h281 #define __IOM volatile /*! Defines 'read / write' structure member permissions */ macro
463 __IOM uint32_t ISER[16U]; /*!< Offset: 0x000 (R/W) Interrupt Set Enable Register */
465 …__IOM uint32_t ICER[16U]; /*!< Offset: 0x080 (R/W) Interrupt Clear Enable Register */
467 __IOM uint32_t ISPR[16U]; /*!< Offset: 0x100 (R/W) Interrupt Set Pending Register */
469 …__IOM uint32_t ICPR[16U]; /*!< Offset: 0x180 (R/W) Interrupt Clear Pending Register …
471 __IOM uint32_t IABR[16U]; /*!< Offset: 0x200 (R/W) Interrupt Active bit Register */
473 …__IOM uint32_t ITNS[16U]; /*!< Offset: 0x280 (R/W) Interrupt Non-Secure State Regist…
475 …__IOM uint8_t IPR[496U]; /*!< Offset: 0x300 (R/W) Interrupt Priority Register (8Bit…
500 …__IOM uint32_t ICSR; /*!< Offset: 0x004 (R/W) Interrupt Control and State Regis…
501 __IOM uint32_t VTOR; /*!< Offset: 0x008 (R/W) Vector Table Offset Register */
[all …]
Dcore_armv81mml.h282 #define __IOM volatile /*! Defines 'read / write' structure member permissions */ macro
464 __IOM uint32_t ISER[16U]; /*!< Offset: 0x000 (R/W) Interrupt Set Enable Register */
466 …__IOM uint32_t ICER[16U]; /*!< Offset: 0x080 (R/W) Interrupt Clear Enable Register */
468 __IOM uint32_t ISPR[16U]; /*!< Offset: 0x100 (R/W) Interrupt Set Pending Register */
470 …__IOM uint32_t ICPR[16U]; /*!< Offset: 0x180 (R/W) Interrupt Clear Pending Register …
472 __IOM uint32_t IABR[16U]; /*!< Offset: 0x200 (R/W) Interrupt Active bit Register */
474 …__IOM uint32_t ITNS[16U]; /*!< Offset: 0x280 (R/W) Interrupt Non-Secure State Regist…
476 …__IOM uint8_t IPR[496U]; /*!< Offset: 0x300 (R/W) Interrupt Priority Register (8Bit…
501 …__IOM uint32_t ICSR; /*!< Offset: 0x004 (R/W) Interrupt Control and State Regis…
502 __IOM uint32_t VTOR; /*!< Offset: 0x008 (R/W) Vector Table Offset Register */
[all …]
Dcore_armv8mml.h281 #define __IOM volatile /*! Defines 'read / write' structure member permissions */ macro
463 __IOM uint32_t ISER[16U]; /*!< Offset: 0x000 (R/W) Interrupt Set Enable Register */
465 …__IOM uint32_t ICER[16U]; /*!< Offset: 0x080 (R/W) Interrupt Clear Enable Register */
467 __IOM uint32_t ISPR[16U]; /*!< Offset: 0x100 (R/W) Interrupt Set Pending Register */
469 …__IOM uint32_t ICPR[16U]; /*!< Offset: 0x180 (R/W) Interrupt Clear Pending Register …
471 __IOM uint32_t IABR[16U]; /*!< Offset: 0x200 (R/W) Interrupt Active bit Register */
473 …__IOM uint32_t ITNS[16U]; /*!< Offset: 0x280 (R/W) Interrupt Non-Secure State Regist…
475 …__IOM uint8_t IPR[496U]; /*!< Offset: 0x300 (R/W) Interrupt Priority Register (8Bit…
500 …__IOM uint32_t ICSR; /*!< Offset: 0x004 (R/W) Interrupt Control and State Regis…
501 __IOM uint32_t VTOR; /*!< Offset: 0x008 (R/W) Vector Table Offset Register */
[all …]
Dcore_cm23.h201 #define __IOM volatile /*! Defines 'read / write' structure member permissions */ macro
353 __IOM uint32_t ISER[16U]; /*!< Offset: 0x000 (R/W) Interrupt Set Enable Register */
355 …__IOM uint32_t ICER[16U]; /*!< Offset: 0x080 (R/W) Interrupt Clear Enable Register */
357 __IOM uint32_t ISPR[16U]; /*!< Offset: 0x100 (R/W) Interrupt Set Pending Register */
359 …__IOM uint32_t ICPR[16U]; /*!< Offset: 0x180 (R/W) Interrupt Clear Pending Register …
361 __IOM uint32_t IABR[16U]; /*!< Offset: 0x200 (R/W) Interrupt Active bit Register */
363 …__IOM uint32_t ITNS[16U]; /*!< Offset: 0x280 (R/W) Interrupt Non-Secure State Regist…
365 __IOM uint32_t IPR[124U]; /*!< Offset: 0x300 (R/W) Interrupt Priority Register */
384 …__IOM uint32_t ICSR; /*!< Offset: 0x004 (R/W) Interrupt Control and State Regis…
386 __IOM uint32_t VTOR; /*!< Offset: 0x008 (R/W) Vector Table Offset Register */
[all …]
Dcore_armv8mbl.h201 #define __IOM volatile /*! Defines 'read / write' structure member permissions */ macro
353 __IOM uint32_t ISER[16U]; /*!< Offset: 0x000 (R/W) Interrupt Set Enable Register */
355 …__IOM uint32_t ICER[16U]; /*!< Offset: 0x080 (R/W) Interrupt Clear Enable Register */
357 __IOM uint32_t ISPR[16U]; /*!< Offset: 0x100 (R/W) Interrupt Set Pending Register */
359 …__IOM uint32_t ICPR[16U]; /*!< Offset: 0x180 (R/W) Interrupt Clear Pending Register …
361 __IOM uint32_t IABR[16U]; /*!< Offset: 0x200 (R/W) Interrupt Active bit Register */
363 …__IOM uint32_t ITNS[16U]; /*!< Offset: 0x280 (R/W) Interrupt Non-Secure State Regist…
365 __IOM uint32_t IPR[124U]; /*!< Offset: 0x300 (R/W) Interrupt Priority Register */
384 …__IOM uint32_t ICSR; /*!< Offset: 0x004 (R/W) Interrupt Control and State Regis…
386 __IOM uint32_t VTOR; /*!< Offset: 0x008 (R/W) Vector Table Offset Register */
[all …]
Dcore_sc300.h175 #define __IOM volatile /*! Defines 'read / write' structure member permissions */ macro
342 __IOM uint32_t ISER[8U]; /*!< Offset: 0x000 (R/W) Interrupt Set Enable Register */
344 …__IOM uint32_t ICER[8U]; /*!< Offset: 0x080 (R/W) Interrupt Clear Enable Register */
346 __IOM uint32_t ISPR[8U]; /*!< Offset: 0x100 (R/W) Interrupt Set Pending Register */
348 …__IOM uint32_t ICPR[8U]; /*!< Offset: 0x180 (R/W) Interrupt Clear Pending Register …
350 __IOM uint32_t IABR[8U]; /*!< Offset: 0x200 (R/W) Interrupt Active bit Register */
352 …__IOM uint8_t IP[240U]; /*!< Offset: 0x300 (R/W) Interrupt Priority Register (8Bit…
377 …__IOM uint32_t ICSR; /*!< Offset: 0x004 (R/W) Interrupt Control and State Regis…
378 __IOM uint32_t VTOR; /*!< Offset: 0x008 (R/W) Vector Table Offset Register */
379 …__IOM uint32_t AIRCR; /*!< Offset: 0x00C (R/W) Application Interrupt and Reset C…
[all …]
Dcore_cm3.h175 #define __IOM volatile /*! Defines 'read / write' structure member permissions */ macro
342 __IOM uint32_t ISER[8U]; /*!< Offset: 0x000 (R/W) Interrupt Set Enable Register */
344 …__IOM uint32_t ICER[8U]; /*!< Offset: 0x080 (R/W) Interrupt Clear Enable Register */
346 __IOM uint32_t ISPR[8U]; /*!< Offset: 0x100 (R/W) Interrupt Set Pending Register */
348 …__IOM uint32_t ICPR[8U]; /*!< Offset: 0x180 (R/W) Interrupt Clear Pending Register …
350 __IOM uint32_t IABR[8U]; /*!< Offset: 0x200 (R/W) Interrupt Active bit Register */
352 …__IOM uint8_t IP[240U]; /*!< Offset: 0x300 (R/W) Interrupt Priority Register (8Bit…
377 …__IOM uint32_t ICSR; /*!< Offset: 0x004 (R/W) Interrupt Control and State Regis…
378 __IOM uint32_t VTOR; /*!< Offset: 0x008 (R/W) Vector Table Offset Register */
379 …__IOM uint32_t AIRCR; /*!< Offset: 0x00C (R/W) Application Interrupt and Reset C…
[all …]
Dcore_cm4.h227 #define __IOM volatile /*! Defines 'read / write' structure member permissions */ macro
408 __IOM uint32_t ISER[8U]; /*!< Offset: 0x000 (R/W) Interrupt Set Enable Register */
410 …__IOM uint32_t ICER[8U]; /*!< Offset: 0x080 (R/W) Interrupt Clear Enable Register */
412 __IOM uint32_t ISPR[8U]; /*!< Offset: 0x100 (R/W) Interrupt Set Pending Register */
414 …__IOM uint32_t ICPR[8U]; /*!< Offset: 0x180 (R/W) Interrupt Clear Pending Register …
416 __IOM uint32_t IABR[8U]; /*!< Offset: 0x200 (R/W) Interrupt Active bit Register */
418 …__IOM uint8_t IP[240U]; /*!< Offset: 0x300 (R/W) Interrupt Priority Register (8Bit…
443 …__IOM uint32_t ICSR; /*!< Offset: 0x004 (R/W) Interrupt Control and State Regis…
444 __IOM uint32_t VTOR; /*!< Offset: 0x008 (R/W) Vector Table Offset Register */
445 …__IOM uint32_t AIRCR; /*!< Offset: 0x00C (R/W) Application Interrupt and Reset C…
[all …]
Dcore_cm7.h242 #define __IOM volatile /*! Defines 'read / write' structure member permissions */ macro
423 __IOM uint32_t ISER[8U]; /*!< Offset: 0x000 (R/W) Interrupt Set Enable Register */
425 …__IOM uint32_t ICER[8U]; /*!< Offset: 0x080 (R/W) Interrupt Clear Enable Register */
427 __IOM uint32_t ISPR[8U]; /*!< Offset: 0x100 (R/W) Interrupt Set Pending Register */
429 …__IOM uint32_t ICPR[8U]; /*!< Offset: 0x180 (R/W) Interrupt Clear Pending Register …
431 __IOM uint32_t IABR[8U]; /*!< Offset: 0x200 (R/W) Interrupt Active bit Register */
433 …__IOM uint8_t IP[240U]; /*!< Offset: 0x300 (R/W) Interrupt Priority Register (8Bit…
458 …__IOM uint32_t ICSR; /*!< Offset: 0x004 (R/W) Interrupt Control and State Regis…
459 __IOM uint32_t VTOR; /*!< Offset: 0x008 (R/W) Vector Table Offset Register */
460 …__IOM uint32_t AIRCR; /*!< Offset: 0x00C (R/W) Application Interrupt and Reset C…
[all …]
Dcore_sc000.h175 #define __IOM volatile /*! Defines 'read / write' structure member permissions */ macro
322 __IOM uint32_t ISER[1U]; /*!< Offset: 0x000 (R/W) Interrupt Set Enable Register */
324 …__IOM uint32_t ICER[1U]; /*!< Offset: 0x080 (R/W) Interrupt Clear Enable Register */
326 __IOM uint32_t ISPR[1U]; /*!< Offset: 0x100 (R/W) Interrupt Set Pending Register */
328 …__IOM uint32_t ICPR[1U]; /*!< Offset: 0x180 (R/W) Interrupt Clear Pending Register …
331 __IOM uint32_t IP[8U]; /*!< Offset: 0x300 (R/W) Interrupt Priority Register */
350 …__IOM uint32_t ICSR; /*!< Offset: 0x004 (R/W) Interrupt Control and State Regis…
351 __IOM uint32_t VTOR; /*!< Offset: 0x008 (R/W) Vector Table Offset Register */
352 …__IOM uint32_t AIRCR; /*!< Offset: 0x00C (R/W) Application Interrupt and Reset C…
353 __IOM uint32_t SCR; /*!< Offset: 0x010 (R/W) System Control Register */
[all …]
Dcore_cm0plus.h180 #define __IOM volatile /*! Defines 'read / write' structure member permissions */ macro
330 __IOM uint32_t ISER[1U]; /*!< Offset: 0x000 (R/W) Interrupt Set Enable Register */
332 …__IOM uint32_t ICER[1U]; /*!< Offset: 0x080 (R/W) Interrupt Clear Enable Register */
334 __IOM uint32_t ISPR[1U]; /*!< Offset: 0x100 (R/W) Interrupt Set Pending Register */
336 …__IOM uint32_t ICPR[1U]; /*!< Offset: 0x180 (R/W) Interrupt Clear Pending Register …
339 __IOM uint32_t IP[8U]; /*!< Offset: 0x300 (R/W) Interrupt Priority Register */
358 …__IOM uint32_t ICSR; /*!< Offset: 0x004 (R/W) Interrupt Control and State Regis…
360 __IOM uint32_t VTOR; /*!< Offset: 0x008 (R/W) Vector Table Offset Register */
364 …__IOM uint32_t AIRCR; /*!< Offset: 0x00C (R/W) Application Interrupt and Reset C…
365 __IOM uint32_t SCR; /*!< Offset: 0x010 (R/W) System Control Register */
[all …]
Dcore_cm1.h170 #define __IOM volatile /*! Defines 'read / write' structure member permissions */ macro
316 __IOM uint32_t ISER[1U]; /*!< Offset: 0x000 (R/W) Interrupt Set Enable Register */
318 …__IOM uint32_t ICER[1U]; /*!< Offset: 0x080 (R/W) Interrupt Clear Enable Register */
320 __IOM uint32_t ISPR[1U]; /*!< Offset: 0x100 (R/W) Interrupt Set Pending Register */
322 …__IOM uint32_t ICPR[1U]; /*!< Offset: 0x180 (R/W) Interrupt Clear Pending Register …
325 __IOM uint32_t IP[8U]; /*!< Offset: 0x300 (R/W) Interrupt Priority Register */
344 …__IOM uint32_t ICSR; /*!< Offset: 0x004 (R/W) Interrupt Control and State Regis…
346 …__IOM uint32_t AIRCR; /*!< Offset: 0x00C (R/W) Application Interrupt and Reset C…
347 __IOM uint32_t SCR; /*!< Offset: 0x010 (R/W) System Control Register */
348 __IOM uint32_t CCR; /*!< Offset: 0x014 (R/W) Configuration Control Register */
[all …]
Dcore_cm0.h170 #define __IOM volatile /*! Defines 'read / write' structure member permissions */ macro
316 __IOM uint32_t ISER[1U]; /*!< Offset: 0x000 (R/W) Interrupt Set Enable Register */
318 …__IOM uint32_t ICER[1U]; /*!< Offset: 0x080 (R/W) Interrupt Clear Enable Register */
320 __IOM uint32_t ISPR[1U]; /*!< Offset: 0x100 (R/W) Interrupt Set Pending Register */
322 …__IOM uint32_t ICPR[1U]; /*!< Offset: 0x180 (R/W) Interrupt Clear Pending Register …
325 __IOM uint32_t IP[8U]; /*!< Offset: 0x300 (R/W) Interrupt Priority Register */
344 …__IOM uint32_t ICSR; /*!< Offset: 0x004 (R/W) Interrupt Control and State Regis…
346 …__IOM uint32_t AIRCR; /*!< Offset: 0x00C (R/W) Application Interrupt and Reset C…
347 __IOM uint32_t SCR; /*!< Offset: 0x010 (R/W) System Control Register */
348 __IOM uint32_t CCR; /*!< Offset: 0x014 (R/W) Configuration Control Register */
[all …]
Dcore_dsp.h53 #define __IOM volatile /*! Defines 'read / write' structure member permissions */ macro
/hal_nxp-latest/mcux/mcux-sdk/CMSIS/Core/Include/
Dcore_cm33.h288 #define __IOM volatile /*! Defines 'read / write' structure member permissions */ macro
470 __IOM uint32_t ISER[16U]; /*!< Offset: 0x000 (R/W) Interrupt Set Enable Register */
472 …__IOM uint32_t ICER[16U]; /*!< Offset: 0x080 (R/W) Interrupt Clear Enable Register */
474 __IOM uint32_t ISPR[16U]; /*!< Offset: 0x100 (R/W) Interrupt Set Pending Register */
476 …__IOM uint32_t ICPR[16U]; /*!< Offset: 0x180 (R/W) Interrupt Clear Pending Register …
478 __IOM uint32_t IABR[16U]; /*!< Offset: 0x200 (R/W) Interrupt Active bit Register */
480 …__IOM uint32_t ITNS[16U]; /*!< Offset: 0x280 (R/W) Interrupt Non-Secure State Regist…
482 …__IOM uint8_t IPR[496U]; /*!< Offset: 0x300 (R/W) Interrupt Priority Register (8Bit…
507 …__IOM uint32_t ICSR; /*!< Offset: 0x004 (R/W) Interrupt Control and State Regis…
508 __IOM uint32_t VTOR; /*!< Offset: 0x008 (R/W) Vector Table Offset Register */
[all …]
Dcore_cm4.h232 #define __IOM volatile /*! Defines 'read / write' structure member permissions */ macro
413 __IOM uint32_t ISER[8U]; /*!< Offset: 0x000 (R/W) Interrupt Set Enable Register */
415 …__IOM uint32_t ICER[8U]; /*!< Offset: 0x080 (R/W) Interrupt Clear Enable Register */
417 __IOM uint32_t ISPR[8U]; /*!< Offset: 0x100 (R/W) Interrupt Set Pending Register */
419 …__IOM uint32_t ICPR[8U]; /*!< Offset: 0x180 (R/W) Interrupt Clear Pending Register …
421 __IOM uint32_t IABR[8U]; /*!< Offset: 0x200 (R/W) Interrupt Active bit Register */
423 …__IOM uint8_t IP[240U]; /*!< Offset: 0x300 (R/W) Interrupt Priority Register (8Bit…
448 …__IOM uint32_t ICSR; /*!< Offset: 0x004 (R/W) Interrupt Control and State Regis…
449 __IOM uint32_t VTOR; /*!< Offset: 0x008 (R/W) Vector Table Offset Register */
450 …__IOM uint32_t AIRCR; /*!< Offset: 0x00C (R/W) Application Interrupt and Reset C…
[all …]
Dcore_cm7.h247 #define __IOM volatile /*! Defines 'read / write' structure member permissions */ macro
428 __IOM uint32_t ISER[8U]; /*!< Offset: 0x000 (R/W) Interrupt Set Enable Register */
430 …__IOM uint32_t ICER[8U]; /*!< Offset: 0x080 (R/W) Interrupt Clear Enable Register */
432 __IOM uint32_t ISPR[8U]; /*!< Offset: 0x100 (R/W) Interrupt Set Pending Register */
434 …__IOM uint32_t ICPR[8U]; /*!< Offset: 0x180 (R/W) Interrupt Clear Pending Register …
436 __IOM uint32_t IABR[8U]; /*!< Offset: 0x200 (R/W) Interrupt Active bit Register */
438 …__IOM uint8_t IP[240U]; /*!< Offset: 0x300 (R/W) Interrupt Priority Register (8Bit…
463 …__IOM uint32_t ICSR; /*!< Offset: 0x004 (R/W) Interrupt Control and State Regis…
464 __IOM uint32_t VTOR; /*!< Offset: 0x008 (R/W) Vector Table Offset Register */
465 …__IOM uint32_t AIRCR; /*!< Offset: 0x00C (R/W) Application Interrupt and Reset C…
[all …]
Dcore_cm0plus.h180 #define __IOM volatile /*! Defines 'read / write' structure member permissions */ macro
330 __IOM uint32_t ISER[1U]; /*!< Offset: 0x000 (R/W) Interrupt Set Enable Register */
332 …__IOM uint32_t ICER[1U]; /*!< Offset: 0x080 (R/W) Interrupt Clear Enable Register */
334 __IOM uint32_t ISPR[1U]; /*!< Offset: 0x100 (R/W) Interrupt Set Pending Register */
336 …__IOM uint32_t ICPR[1U]; /*!< Offset: 0x180 (R/W) Interrupt Clear Pending Register …
339 __IOM uint32_t IP[8U]; /*!< Offset: 0x300 (R/W) Interrupt Priority Register */
358 …__IOM uint32_t ICSR; /*!< Offset: 0x004 (R/W) Interrupt Control and State Regis…
360 __IOM uint32_t VTOR; /*!< Offset: 0x008 (R/W) Vector Table Offset Register */
364 …__IOM uint32_t AIRCR; /*!< Offset: 0x00C (R/W) Application Interrupt and Reset C…
365 __IOM uint32_t SCR; /*!< Offset: 0x010 (R/W) System Control Register */
[all …]
/hal_nxp-latest/mcux/mcux-sdk/CMSIS/Core_AArch64/Include/
Dgic_v3.h108 …__IOM uint32_t CTLR; /*!< \brief Offset: 0x000 (R/W) Distributor Control Register…
112 …__IOM uint32_t STATUSR; /*!< \brief Offset: 0x010 (R/W) Error Reporting Status Regis…
122 __IOM uint32_t IGROUPR[32]; /*!< \brief Offset: 0x080 (R/W) Interrupt Group Registers */
123 …__IOM uint32_t ISENABLER[32]; /*!< \brief Offset: 0x100 (R/W) Interrupt Set-Enable Registe…
124 …__IOM uint32_t ICENABLER[32]; /*!< \brief Offset: 0x180 (R/W) Interrupt Clear-Enable Regis…
125 …__IOM uint32_t ISPENDR[32]; /*!< \brief Offset: 0x200 (R/W) Interrupt Set-Pending Regist…
126 …__IOM uint32_t ICPENDR[32]; /*!< \brief Offset: 0x280 (R/W) Interrupt Clear-Pending Regi…
127 …__IOM uint32_t ISACTIVER[32]; /*!< \brief Offset: 0x300 (R/W) Interrupt Set-Active Registe…
128 …__IOM uint32_t ICACTIVER[32]; /*!< \brief Offset: 0x380 (R/W) Interrupt Clear-Active Regis…
129 …__IOM uint32_t IPRIORITYR[255]; /*!< \brief Offset: 0x400 (R/W) Interrupt Priority Registers…
[all …]
Dcmsis_compiler.h85 #define __IOM volatile /*! Defines 'read / write' structure member permissions */ macro
/hal_nxp-latest/mcux/mcux-sdk/devices/MIMXRT685S/
DMIMXRT685S_dsp.h67 #define __IOM volatile /*! Defines 'read / write' structure member permissions */ macro
/hal_nxp-latest/mcux/mcux-sdk/devices/MIMXRT595S/
DMIMXRT595S_dsp.h72 #define __IOM volatile /*! Defines 'read / write' structure member permissions */ macro
/hal_nxp-latest/mcux/mcux-sdk/devices/MIMXRT735S/
DMIMXRT735S_hifi1.h66 #define __IOM volatile /*! Defines 'read / write' structure member permissions */ macro
/hal_nxp-latest/mcux/mcux-sdk/devices/MIMXRT798S/
DMIMXRT798S_hifi1.h66 #define __IOM volatile /*! Defines 'read / write' structure member permissions */ macro

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