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Searched refs:__IM (Results 1 – 25 of 36) sorted by relevance

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/hal_nxp-latest/mcux/mcux-sdk/CMSIS/Core/Include/
Dcore_cm7.h245 #define __IM volatile const /*! Defines 'read only' structure member permissions */ macro
462 __IM uint32_t CPUID; /*!< Offset: 0x000 (R/ ) CPUID Base Register */
476 __IM uint32_t ID_PFR[2U]; /*!< Offset: 0x040 (R/ ) Processor Feature Register */
477 __IM uint32_t ID_DFR; /*!< Offset: 0x048 (R/ ) Debug Feature Register */
478 __IM uint32_t ID_AFR; /*!< Offset: 0x04C (R/ ) Auxiliary Feature Register */
479 __IM uint32_t ID_MFR[4U]; /*!< Offset: 0x050 (R/ ) Memory Model Feature Register */
480 …__IM uint32_t ID_ISAR[5U]; /*!< Offset: 0x060 (R/ ) Instruction Set Attributes Regist…
482 __IM uint32_t CLIDR; /*!< Offset: 0x078 (R/ ) Cache Level ID register */
483 __IM uint32_t CTR; /*!< Offset: 0x07C (R/ ) Cache Type register */
484 __IM uint32_t CCSIDR; /*!< Offset: 0x080 (R/ ) Cache Size ID Register */
[all …]
Dcore_cm4.h230 #define __IM volatile const /*! Defines 'read only' structure member permissions */ macro
447 __IM uint32_t CPUID; /*!< Offset: 0x000 (R/ ) CPUID Base Register */
461 __IM uint32_t PFR[2U]; /*!< Offset: 0x040 (R/ ) Processor Feature Register */
462 __IM uint32_t DFR; /*!< Offset: 0x048 (R/ ) Debug Feature Register */
463 __IM uint32_t ADR; /*!< Offset: 0x04C (R/ ) Auxiliary Feature Register */
464 __IM uint32_t MMFR[4U]; /*!< Offset: 0x050 (R/ ) Memory Model Feature Register */
465 …__IM uint32_t ISAR[5U]; /*!< Offset: 0x060 (R/ ) Instruction Set Attributes Regist…
727 …__IM uint32_t ICTR; /*!< Offset: 0x004 (R/ ) Interrupt Controller Type Registe…
769 __IM uint32_t CALIB; /*!< Offset: 0x00C (R/ ) SysTick Calibration Register */
833 __IM uint32_t LSR; /*!< Offset: 0xFB4 (R/ ) ITM Lock Status Register */
[all …]
Dcore_cm33.h286 #define __IM volatile const /*! Defines 'read only' structure member permissions */ macro
506 __IM uint32_t CPUID; /*!< Offset: 0x000 (R/ ) CPUID Base Register */
520 __IM uint32_t ID_PFR[2U]; /*!< Offset: 0x040 (R/ ) Processor Feature Register */
521 __IM uint32_t ID_DFR; /*!< Offset: 0x048 (R/ ) Debug Feature Register */
522 __IM uint32_t ID_ADR; /*!< Offset: 0x04C (R/ ) Auxiliary Feature Register */
523 __IM uint32_t ID_MMFR[4U]; /*!< Offset: 0x050 (R/ ) Memory Model Feature Register */
524 …__IM uint32_t ID_ISAR[6U]; /*!< Offset: 0x060 (R/ ) Instruction Set Attributes Regist…
525 __IM uint32_t CLIDR; /*!< Offset: 0x078 (R/ ) Cache Level ID register */
526 __IM uint32_t CTR; /*!< Offset: 0x07C (R/ ) Cache Type register */
527 __IM uint32_t CCSIDR; /*!< Offset: 0x080 (R/ ) Cache Size ID Register */
[all …]
Dcore_cm0plus.h178 #define __IM volatile const /*! Defines 'read only' structure member permissions */ macro
357 __IM uint32_t CPUID; /*!< Offset: 0x000 (R/ ) CPUID Base Register */
477 __IM uint32_t CALIB; /*!< Offset: 0x00C (R/ ) SysTick Calibration Register */
526 __IM uint32_t TYPE; /*!< Offset: 0x000 (R/ ) MPU Type Register */
/hal_nxp-latest/mcux/mcux-sdk/CMSIS/Include/
Dcore_cm4.h225 #define __IM volatile const /*! Defines 'read only' structure member permissions */ macro
442 __IM uint32_t CPUID; /*!< Offset: 0x000 (R/ ) CPUID Base Register */
456 __IM uint32_t PFR[2U]; /*!< Offset: 0x040 (R/ ) Processor Feature Register */
457 __IM uint32_t DFR; /*!< Offset: 0x048 (R/ ) Debug Feature Register */
458 __IM uint32_t ADR; /*!< Offset: 0x04C (R/ ) Auxiliary Feature Register */
459 __IM uint32_t MMFR[4U]; /*!< Offset: 0x050 (R/ ) Memory Model Feature Register */
460 …__IM uint32_t ISAR[5U]; /*!< Offset: 0x060 (R/ ) Instruction Set Attributes Regist…
722 …__IM uint32_t ICTR; /*!< Offset: 0x004 (R/ ) Interrupt Controller Type Registe…
764 __IM uint32_t CALIB; /*!< Offset: 0x00C (R/ ) SysTick Calibration Register */
828 __IM uint32_t LSR; /*!< Offset: 0xFB4 (R/ ) ITM Lock Status Register */
[all …]
Dcore_sc300.h173 #define __IM volatile const /*! Defines 'read only' structure member permissions */ macro
376 __IM uint32_t CPUID; /*!< Offset: 0x000 (R/ ) CPUID Base Register */
390 __IM uint32_t PFR[2U]; /*!< Offset: 0x040 (R/ ) Processor Feature Register */
391 __IM uint32_t DFR; /*!< Offset: 0x048 (R/ ) Debug Feature Register */
392 __IM uint32_t ADR; /*!< Offset: 0x04C (R/ ) Auxiliary Feature Register */
393 __IM uint32_t MMFR[4U]; /*!< Offset: 0x050 (R/ ) Memory Model Feature Register */
394 …__IM uint32_t ISAR[5U]; /*!< Offset: 0x060 (R/ ) Instruction Set Attributes Regist…
655 …__IM uint32_t ICTR; /*!< Offset: 0x004 (R/ ) Interrupt Controller Type Registe…
691 __IM uint32_t CALIB; /*!< Offset: 0x00C (R/ ) SysTick Calibration Register */
755 __IM uint32_t LSR; /*!< Offset: 0xFB4 (R/ ) ITM Lock Status Register */
[all …]
Dcore_cm3.h173 #define __IM volatile const /*! Defines 'read only' structure member permissions */ macro
376 __IM uint32_t CPUID; /*!< Offset: 0x000 (R/ ) CPUID Base Register */
390 __IM uint32_t PFR[2U]; /*!< Offset: 0x040 (R/ ) Processor Feature Register */
391 __IM uint32_t DFR; /*!< Offset: 0x048 (R/ ) Debug Feature Register */
392 __IM uint32_t ADR; /*!< Offset: 0x04C (R/ ) Auxiliary Feature Register */
393 __IM uint32_t MMFR[4U]; /*!< Offset: 0x050 (R/ ) Memory Model Feature Register */
394 …__IM uint32_t ISAR[5U]; /*!< Offset: 0x060 (R/ ) Instruction Set Attributes Regist…
658 …__IM uint32_t ICTR; /*!< Offset: 0x004 (R/ ) Interrupt Controller Type Registe…
706 __IM uint32_t CALIB; /*!< Offset: 0x00C (R/ ) SysTick Calibration Register */
770 __IM uint32_t LSR; /*!< Offset: 0xFB4 (R/ ) ITM Lock Status Register */
[all …]
Dcore_cm35p.h279 #define __IM volatile const /*! Defines 'read only' structure member permissions */ macro
499 __IM uint32_t CPUID; /*!< Offset: 0x000 (R/ ) CPUID Base Register */
513 __IM uint32_t ID_PFR[2U]; /*!< Offset: 0x040 (R/ ) Processor Feature Register */
514 __IM uint32_t ID_DFR; /*!< Offset: 0x048 (R/ ) Debug Feature Register */
515 __IM uint32_t ID_ADR; /*!< Offset: 0x04C (R/ ) Auxiliary Feature Register */
516 __IM uint32_t ID_MMFR[4U]; /*!< Offset: 0x050 (R/ ) Memory Model Feature Register */
517 …__IM uint32_t ID_ISAR[6U]; /*!< Offset: 0x060 (R/ ) Instruction Set Attributes Regist…
518 __IM uint32_t CLIDR; /*!< Offset: 0x078 (R/ ) Cache Level ID register */
519 __IM uint32_t CTR; /*!< Offset: 0x07C (R/ ) Cache Type register */
520 __IM uint32_t CCSIDR; /*!< Offset: 0x080 (R/ ) Cache Size ID Register */
[all …]
Dcore_cm7.h240 #define __IM volatile const /*! Defines 'read only' structure member permissions */ macro
457 __IM uint32_t CPUID; /*!< Offset: 0x000 (R/ ) CPUID Base Register */
471 __IM uint32_t ID_PFR[2U]; /*!< Offset: 0x040 (R/ ) Processor Feature Register */
472 __IM uint32_t ID_DFR; /*!< Offset: 0x048 (R/ ) Debug Feature Register */
473 __IM uint32_t ID_AFR; /*!< Offset: 0x04C (R/ ) Auxiliary Feature Register */
474 __IM uint32_t ID_MFR[4U]; /*!< Offset: 0x050 (R/ ) Memory Model Feature Register */
475 …__IM uint32_t ID_ISAR[5U]; /*!< Offset: 0x060 (R/ ) Instruction Set Attributes Regist…
477 __IM uint32_t CLIDR; /*!< Offset: 0x078 (R/ ) Cache Level ID register */
478 __IM uint32_t CTR; /*!< Offset: 0x07C (R/ ) Cache Type register */
479 __IM uint32_t CCSIDR; /*!< Offset: 0x080 (R/ ) Cache Size ID Register */
[all …]
Dcore_cm33.h279 #define __IM volatile const /*! Defines 'read only' structure member permissions */ macro
499 __IM uint32_t CPUID; /*!< Offset: 0x000 (R/ ) CPUID Base Register */
513 __IM uint32_t ID_PFR[2U]; /*!< Offset: 0x040 (R/ ) Processor Feature Register */
514 __IM uint32_t ID_DFR; /*!< Offset: 0x048 (R/ ) Debug Feature Register */
515 __IM uint32_t ID_ADR; /*!< Offset: 0x04C (R/ ) Auxiliary Feature Register */
516 __IM uint32_t ID_MMFR[4U]; /*!< Offset: 0x050 (R/ ) Memory Model Feature Register */
517 …__IM uint32_t ID_ISAR[6U]; /*!< Offset: 0x060 (R/ ) Instruction Set Attributes Regist…
518 __IM uint32_t CLIDR; /*!< Offset: 0x078 (R/ ) Cache Level ID register */
519 __IM uint32_t CTR; /*!< Offset: 0x07C (R/ ) Cache Type register */
520 __IM uint32_t CCSIDR; /*!< Offset: 0x080 (R/ ) Cache Size ID Register */
[all …]
Dcore_armv81mml.h280 #define __IM volatile const /*! Defines 'read only' structure member permissions */ macro
500 __IM uint32_t CPUID; /*!< Offset: 0x000 (R/ ) CPUID Base Register */
514 __IM uint32_t ID_PFR[2U]; /*!< Offset: 0x040 (R/ ) Processor Feature Register */
515 __IM uint32_t ID_DFR; /*!< Offset: 0x048 (R/ ) Debug Feature Register */
516 __IM uint32_t ID_ADR; /*!< Offset: 0x04C (R/ ) Auxiliary Feature Register */
517 __IM uint32_t ID_MMFR[4U]; /*!< Offset: 0x050 (R/ ) Memory Model Feature Register */
518 …__IM uint32_t ID_ISAR[6U]; /*!< Offset: 0x060 (R/ ) Instruction Set Attributes Regist…
519 __IM uint32_t CLIDR; /*!< Offset: 0x078 (R/ ) Cache Level ID register */
520 __IM uint32_t CTR; /*!< Offset: 0x07C (R/ ) Cache Type register */
521 __IM uint32_t CCSIDR; /*!< Offset: 0x080 (R/ ) Cache Size ID Register */
[all …]
Dcore_armv8mml.h279 #define __IM volatile const /*! Defines 'read only' structure member permissions */ macro
499 __IM uint32_t CPUID; /*!< Offset: 0x000 (R/ ) CPUID Base Register */
513 __IM uint32_t ID_PFR[2U]; /*!< Offset: 0x040 (R/ ) Processor Feature Register */
514 __IM uint32_t ID_DFR; /*!< Offset: 0x048 (R/ ) Debug Feature Register */
515 __IM uint32_t ID_ADR; /*!< Offset: 0x04C (R/ ) Auxiliary Feature Register */
516 __IM uint32_t ID_MMFR[4U]; /*!< Offset: 0x050 (R/ ) Memory Model Feature Register */
517 …__IM uint32_t ID_ISAR[6U]; /*!< Offset: 0x060 (R/ ) Instruction Set Attributes Regist…
518 __IM uint32_t CLIDR; /*!< Offset: 0x078 (R/ ) Cache Level ID register */
519 __IM uint32_t CTR; /*!< Offset: 0x07C (R/ ) Cache Type register */
520 __IM uint32_t CCSIDR; /*!< Offset: 0x080 (R/ ) Cache Size ID Register */
[all …]
Dcore_cm23.h199 #define __IM volatile const /*! Defines 'read only' structure member permissions */ macro
383 __IM uint32_t CPUID; /*!< Offset: 0x000 (R/ ) CPUID Base Register */
563 __IM uint32_t CALIB; /*!< Offset: 0x00C (R/ ) SysTick Calibration Register */
614 …__IM uint32_t PCSR; /*!< Offset: 0x01C (R/ ) Program Counter Sample Register */
727 …__IM uint32_t SSPSR; /*!< Offset: 0x000 (R/ ) Supported Parallel Port Size Regi…
734 …__IM uint32_t FFSR; /*!< Offset: 0x300 (R/ ) Formatter and Flush Status Regist…
738 __IM uint32_t TRIGGER; /*!< Offset: 0xEE8 (R/ ) TRIGGER Register */
739 …__IM uint32_t ITFTTD0; /*!< Offset: 0xEEC (R/ ) Integration Test FIFO Test Data 0…
742 …__IM uint32_t ITATBCTR0; /*!< Offset: 0xEF8 (R/ ) Integration Test ATB Control Regi…
743 …__IM uint32_t ITFTTD1; /*!< Offset: 0xEFC (R/ ) Integration Test FIFO Test Data 1…
[all …]
Dcore_armv8mbl.h199 #define __IM volatile const /*! Defines 'read only' structure member permissions */ macro
383 __IM uint32_t CPUID; /*!< Offset: 0x000 (R/ ) CPUID Base Register */
563 __IM uint32_t CALIB; /*!< Offset: 0x00C (R/ ) SysTick Calibration Register */
614 …__IM uint32_t PCSR; /*!< Offset: 0x01C (R/ ) Program Counter Sample Register */
727 …__IM uint32_t SSPSR; /*!< Offset: 0x000 (R/ ) Supported Parallel Port Sizes Reg…
734 …__IM uint32_t FFSR; /*!< Offset: 0x300 (R/ ) Formatter and Flush Status Regist…
739 __IM uint32_t LSR; /*!< Offset: 0xFB4 (R/ ) Software Lock Status Register */
741 __IM uint32_t TYPE; /*!< Offset: 0xFC8 (R/ ) Device Identifier Register */
742 __IM uint32_t DEVTYPE; /*!< Offset: 0xFCC (R/ ) Device Type Register */
826 __IM uint32_t TYPE; /*!< Offset: 0x000 (R/ ) MPU Type Register */
[all …]
Dcore_sc000.h173 #define __IM volatile const /*! Defines 'read only' structure member permissions */ macro
349 __IM uint32_t CPUID; /*!< Offset: 0x000 (R/ ) CPUID Base Register */
488 __IM uint32_t CALIB; /*!< Offset: 0x00C (R/ ) SysTick Calibration Register */
537 __IM uint32_t TYPE; /*!< Offset: 0x000 (R/ ) MPU Type Register */
Dcore_cm0plus.h178 #define __IM volatile const /*! Defines 'read only' structure member permissions */ macro
357 __IM uint32_t CPUID; /*!< Offset: 0x000 (R/ ) CPUID Base Register */
477 __IM uint32_t CALIB; /*!< Offset: 0x00C (R/ ) SysTick Calibration Register */
526 __IM uint32_t TYPE; /*!< Offset: 0x000 (R/ ) MPU Type Register */
Dcore_cm0.h168 #define __IM volatile const /*! Defines 'read only' structure member permissions */ macro
343 __IM uint32_t CPUID; /*!< Offset: 0x000 (R/ ) CPUID Base Register */
453 __IM uint32_t CALIB; /*!< Offset: 0x00C (R/ ) SysTick Calibration Register */
Dcore_cm1.h168 #define __IM volatile const /*! Defines 'read only' structure member permissions */ macro
343 __IM uint32_t CPUID; /*!< Offset: 0x000 (R/ ) CPUID Base Register */
479 __IM uint32_t CALIB; /*!< Offset: 0x00C (R/ ) SysTick Calibration Register */
Dcore_dsp.h51 #define __IM volatile const /*! Defines 'read only' structure member permissions */ macro
/hal_nxp-latest/mcux/mcux-sdk/CMSIS/Core_AArch64/Include/
Dgic_v3.h109 …__IM uint32_t TYPER; /*!< \brief Offset: 0x004 (R/ ) Interrupt Controller Type Re…
110 …__IM uint32_t IIDR; /*!< \brief Offset: 0x008 (R/ ) Distributor Implementer Iden…
152 …__IM uint32_t IIDR; /*!< \brief Offset: 0x004 (R/ ) Implementer Identification R…
153 …__IM uint64_t TYPER; /*!< \brief Offset: 0x008 (R/ ) Redistributor Type Register …
156 …__IM uint32_t MPAMIDR; /*!< \brief Offset: 0x018 (R/ ) Report maximum PARTID and PM…
171 …__IM uint32_t SYNCR; /*!< \brief Offset: 0x0C0 (R/ ) Redistributor Synchronize Re…
185 …__IM uint32_t IAR; /*!< \brief Offset: 0x00C (R/ ) Interrupt Acknowledge Regist…
187 __IM uint32_t RPR; /*!< \brief Offset: 0x014 (R/ ) Running Priority Register */
188 …__IM uint32_t HPPIR; /*!< \brief Offset: 0x018 (R/ ) Highest Priority Pending Int…
190 …__IM uint32_t AIAR; /*!< \brief Offset: 0x020 (R/ ) Aliased Interrupt Acknowledg…
[all …]
Dcmsis_compiler.h83 #define __IM volatile const /*! Defines 'read only' structure member permissions */ macro
/hal_nxp-latest/mcux/mcux-sdk/devices/MIMXRT685S/
DMIMXRT685S_dsp.h65 #define __IM volatile const /*! Defines 'read only' structure member permissions */ macro
/hal_nxp-latest/mcux/mcux-sdk/devices/MIMXRT595S/
DMIMXRT595S_dsp.h70 #define __IM volatile const /*! Defines 'read only' structure member permissions */ macro
/hal_nxp-latest/mcux/mcux-sdk/devices/MIMXRT735S/
DMIMXRT735S_hifi1.h64 #define __IM volatile const /*! Defines 'read only' structure member permissions */ macro
/hal_nxp-latest/mcux/mcux-sdk/devices/MIMXRT798S/
DMIMXRT798S_hifi1.h64 #define __IM volatile const /*! Defines 'read only' structure member permissions */ macro

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