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/hal_nxp-latest/s32/drivers/s32ze/BaseNXP/header/
DS32Z2_SW_ETH_MAC_PORT0.h75 …__I uint32_t PM0_MAC_ADDR_0; /**< Port MAC 0 MAC Address Register 0, offset: 0…
76 …__I uint32_t PM0_MAC_ADDR_1; /**< Port MAC 0 MAC Address Register 1, offset: 0…
87 …__I uint32_t PM0_RX_PAUSE_STATUS; /**< Port MAC 0 Receive Pause Status Register, of…
95 …__I uint64_t PM0_REOCTN; /**< Port MAC 0 Receive Ethernet Octets Counter(e…
96 …__I uint64_t PM0_ROCTN; /**< Port MAC 0 Receive Octets Counter(iflnOctets…
98 …__I uint64_t PM0_RXPFN; /**< Port MAC 0 Receive Valid Pause Frame Counter…
99 …__I uint64_t PM0_RFRMN; /**< Port MAC 0 Receive Frame Counter Register(aF…
100 …__I uint64_t PM0_RFCSN; /**< Port MAC 0 Receive Frame Check Sequence Erro…
101 …__I uint64_t PM0_RVLANN; /**< Port MAC 0 Receive VLAN Frame Counter Regist…
102 …__I uint64_t PM0_RERRN; /**< Port MAC 0 Receive Frame Error Counter Regis…
[all …]
DS32Z2_SW_ETH_MAC_PORT1.h75 …__I uint32_t PM0_MAC_ADDR_0; /**< Port MAC 0 MAC Address Register 0, offset: 0…
76 …__I uint32_t PM0_MAC_ADDR_1; /**< Port MAC 0 MAC Address Register 1, offset: 0…
87 …__I uint32_t PM0_RX_PAUSE_STATUS; /**< Port MAC 0 Receive Pause Status Register, of…
95 …__I uint64_t PM0_REOCTN; /**< Port MAC 0 Receive Ethernet Octets Counter(e…
96 …__I uint64_t PM0_ROCTN; /**< Port MAC 0 Receive Octets Counter(iflnOctets…
98 …__I uint64_t PM0_RXPFN; /**< Port MAC 0 Receive Valid Pause Frame Counter…
99 …__I uint64_t PM0_RFRMN; /**< Port MAC 0 Receive Frame Counter Register(aF…
100 …__I uint64_t PM0_RFCSN; /**< Port MAC 0 Receive Frame Check Sequence Erro…
101 …__I uint64_t PM0_RVLANN; /**< Port MAC 0 Receive VLAN Frame Counter Regist…
102 …__I uint64_t PM0_RERRN; /**< Port MAC 0 Receive Frame Error Counter Regis…
[all …]
DS32Z2_GIC.h88 …__I uint32_t GICD_TYPRE; /*!< \brief Offset: 0x004 (RO) Int…
89 …__I uint32_t GICD_IIDR; /*!< \brief Offset: 0x008 (RO) Dis…
111 …__I uint32_t GICD_PIDR4; /*!< \brief Offset: +0xFFD0 - RO -…
112 …__I uint32_t GICD_PIDR5; /*!< \brief Offset: +0xFFD4 - RO -…
113 …__I uint32_t GICD_PIDR6; /*!< \brief Offset: +0xFFD8 - RO -…
114 …__I uint32_t GICD_PIDR7; /*!< \brief Offset: +0xFFDC - RO -…
115 …__I uint32_t GICD_PIDR0; /*!< \brief Offset: +0xFFE0 - RO -…
116 …__I uint32_t GICD_PIDR1; /*!< \brief Offset: +0xFFE4 - RO -…
117 …__I uint32_t GICD_PIDR2; /*!< \brief Offset: +0xFFE8 - RO -…
118 …__I uint32_t GICD_PIDR3; /*!< \brief Offset: +0xFFEC - RO -…
[all …]
DS32Z2_NETC_F3_PCI_HDR_TYPE0.h77 …__I uint32_t PCI_CFH_DID_VID; /**< PCI device ID and vendor ID register, offset…
79 __I uint16_t PCI_CFH_STAT; /**< PCI status register, offset: 0x6 */
80 …__I uint32_t PCI_CFH_REVID_CLASSCODE; /**< PCI revision ID and classcode register, offs…
83 __I uint8_t PCI_CFH_HDR_TYPE; /**< PCI header type register, offset: 0xE */
85 __I uint32_t PCI_CFH_BAR0; /**< PCI base address register 0, offset: 0x10 */
86 __I uint32_t PCI_CFH_BAR1; /**< PCI base address register 1, offset: 0x14 */
87 __I uint32_t PCI_CFH_BAR2; /**< PCI base address register 2, offset: 0x18 */
88 __I uint32_t PCI_CFH_BAR3; /**< PCI base address register 3, offset: 0x1C */
89 __I uint32_t PCI_CFH_BAR4; /**< PCI base address register 4, offset: 0x20 */
90 __I uint32_t PCI_CFH_BAR5; /**< PCI base address register 5, offset: 0x24 */
[all …]
DS32Z2_MSCM.h76 __I uint32_t CPXTYPE; /**< Core Processor x Type, offset: 0x0 */
77 __I uint32_t CPXNUM; /**< Core Processor x Number, offset: 0x4 */
78 __I uint32_t CPXREV; /**< Core Processor x Revision, offset: 0x8 */
79 …__I uint32_t CPXCFG0; /**< Core Processor x Configuration 0, offset: 0x…
80 …__I uint32_t CPXCFG1; /**< Core or Cluster Processor x Configuration 1,…
81 …__I uint32_t CPXCFG2; /**< Core Processor x Configuration 2, offset: 0x…
82 …__I uint32_t CPXCFG3; /**< Core Processor x Configuration 3, offset: 0x…
84 __I uint32_t CP0TYPE; /**< Cluster Processor 0 Type, offset: 0x20 */
85 __I uint32_t CP0NUM; /**< Cluster Processor 0 Number, offset: 0x24 */
86 __I uint32_t CP0REV; /**< Core Processor 0 Revision, offset: 0x28 */
[all …]
DS32Z2_NETC_VF4_PCI_HDR_TYPE0.h73 …__I uint32_t PCI_CFH_DID_VID; /**< PCI device ID and vendor ID register, offset…
75 __I uint16_t PCI_CFH_STAT; /**< PCI status register, offset: 0x6 */
76 …__I uint32_t PCI_CFH_REVID_CLASSCODE; /**< PCI revision ID and classcode register, offs…
77 __I uint8_t PCI_CFH_CL_SIZE; /**< PCI cache line size register, offset: 0xC */
78 __I uint8_t PCI_CFH_LAT_TIMER; /**< PCI latency timer register, offset: 0xD */
79 __I uint8_t PCI_CFH_HDR_TYPE; /**< PCI header type register, offset: 0xE */
80 __I uint8_t PCI_CFH_BIST; /**< PCI BIST register, offset: 0xF */
81 __I uint32_t PCI_CFH_BAR0; /**< PCI base address register 0, offset: 0x10 */
82 __I uint32_t PCI_CFH_BAR1; /**< PCI base address register 1, offset: 0x14 */
83 __I uint32_t PCI_CFH_BAR2; /**< PCI base address register 2, offset: 0x18 */
[all …]
DS32Z2_NETC_VF1_PCI_HDR_TYPE0.h73 …__I uint32_t PCI_CFH_DID_VID; /**< PCI device ID and vendor ID register, offset…
75 __I uint16_t PCI_CFH_STAT; /**< PCI status register, offset: 0x6 */
76 …__I uint32_t PCI_CFH_REVID_CLASSCODE; /**< PCI revision ID and classcode register, offs…
77 __I uint8_t PCI_CFH_CL_SIZE; /**< PCI cache line size register, offset: 0xC */
78 __I uint8_t PCI_CFH_LAT_TIMER; /**< PCI latency timer register, offset: 0xD */
79 __I uint8_t PCI_CFH_HDR_TYPE; /**< PCI header type register, offset: 0xE */
80 __I uint8_t PCI_CFH_BIST; /**< PCI BIST register, offset: 0xF */
81 __I uint32_t PCI_CFH_BAR0; /**< PCI base address register 0, offset: 0x10 */
82 __I uint32_t PCI_CFH_BAR1; /**< PCI base address register 1, offset: 0x14 */
83 __I uint32_t PCI_CFH_BAR2; /**< PCI base address register 2, offset: 0x18 */
[all …]
DS32Z2_NETC_VF2_PCI_HDR_TYPE0.h73 …__I uint32_t PCI_CFH_DID_VID; /**< PCI device ID and vendor ID register, offset…
75 __I uint16_t PCI_CFH_STAT; /**< PCI status register, offset: 0x6 */
76 …__I uint32_t PCI_CFH_REVID_CLASSCODE; /**< PCI revision ID and classcode register, offs…
77 __I uint8_t PCI_CFH_CL_SIZE; /**< PCI cache line size register, offset: 0xC */
78 __I uint8_t PCI_CFH_LAT_TIMER; /**< PCI latency timer register, offset: 0xD */
79 __I uint8_t PCI_CFH_HDR_TYPE; /**< PCI header type register, offset: 0xE */
80 __I uint8_t PCI_CFH_BIST; /**< PCI BIST register, offset: 0xF */
81 __I uint32_t PCI_CFH_BAR0; /**< PCI base address register 0, offset: 0x10 */
82 __I uint32_t PCI_CFH_BAR1; /**< PCI base address register 1, offset: 0x14 */
83 __I uint32_t PCI_CFH_BAR2; /**< PCI base address register 2, offset: 0x18 */
[all …]
DS32Z2_NETC_VF5_PCI_HDR_TYPE0.h73 …__I uint32_t PCI_CFH_DID_VID; /**< PCI device ID and vendor ID register, offset…
75 __I uint16_t PCI_CFH_STAT; /**< PCI status register, offset: 0x6 */
76 …__I uint32_t PCI_CFH_REVID_CLASSCODE; /**< PCI revision ID and classcode register, offs…
77 __I uint8_t PCI_CFH_CL_SIZE; /**< PCI cache line size register, offset: 0xC */
78 __I uint8_t PCI_CFH_LAT_TIMER; /**< PCI latency timer register, offset: 0xD */
79 __I uint8_t PCI_CFH_HDR_TYPE; /**< PCI header type register, offset: 0xE */
80 __I uint8_t PCI_CFH_BIST; /**< PCI BIST register, offset: 0xF */
81 __I uint32_t PCI_CFH_BAR0; /**< PCI base address register 0, offset: 0x10 */
82 __I uint32_t PCI_CFH_BAR1; /**< PCI base address register 1, offset: 0x14 */
83 __I uint32_t PCI_CFH_BAR2; /**< PCI base address register 2, offset: 0x18 */
[all …]
DS32Z2_NETC_VF6_PCI_HDR_TYPE0.h73 …__I uint32_t PCI_CFH_DID_VID; /**< PCI device ID and vendor ID register, offset…
75 __I uint16_t PCI_CFH_STAT; /**< PCI status register, offset: 0x6 */
76 …__I uint32_t PCI_CFH_REVID_CLASSCODE; /**< PCI revision ID and classcode register, offs…
77 __I uint8_t PCI_CFH_CL_SIZE; /**< PCI cache line size register, offset: 0xC */
78 __I uint8_t PCI_CFH_LAT_TIMER; /**< PCI latency timer register, offset: 0xD */
79 __I uint8_t PCI_CFH_HDR_TYPE; /**< PCI header type register, offset: 0xE */
80 __I uint8_t PCI_CFH_BIST; /**< PCI BIST register, offset: 0xF */
81 __I uint32_t PCI_CFH_BAR0; /**< PCI base address register 0, offset: 0x10 */
82 __I uint32_t PCI_CFH_BAR1; /**< PCI base address register 1, offset: 0x14 */
83 __I uint32_t PCI_CFH_BAR2; /**< PCI base address register 2, offset: 0x18 */
[all …]
DS32Z2_NETC_VF7_PCI_HDR_TYPE0.h73 …__I uint32_t PCI_CFH_DID_VID; /**< PCI device ID and vendor ID register, offset…
75 __I uint16_t PCI_CFH_STAT; /**< PCI status register, offset: 0x6 */
76 …__I uint32_t PCI_CFH_REVID_CLASSCODE; /**< PCI revision ID and classcode register, offs…
77 __I uint8_t PCI_CFH_CL_SIZE; /**< PCI cache line size register, offset: 0xC */
78 __I uint8_t PCI_CFH_LAT_TIMER; /**< PCI latency timer register, offset: 0xD */
79 __I uint8_t PCI_CFH_HDR_TYPE; /**< PCI header type register, offset: 0xE */
80 __I uint8_t PCI_CFH_BIST; /**< PCI BIST register, offset: 0xF */
81 __I uint32_t PCI_CFH_BAR0; /**< PCI base address register 0, offset: 0x10 */
82 __I uint32_t PCI_CFH_BAR1; /**< PCI base address register 1, offset: 0x14 */
83 __I uint32_t PCI_CFH_BAR2; /**< PCI base address register 2, offset: 0x18 */
[all …]
DS32Z2_NETC_VF3_PCI_HDR_TYPE0.h73 …__I uint32_t PCI_CFH_DID_VID; /**< PCI device ID and vendor ID register, offset…
75 __I uint16_t PCI_CFH_STAT; /**< PCI status register, offset: 0x6 */
76 …__I uint32_t PCI_CFH_REVID_CLASSCODE; /**< PCI revision ID and classcode register, offs…
77 __I uint8_t PCI_CFH_CL_SIZE; /**< PCI cache line size register, offset: 0xC */
78 __I uint8_t PCI_CFH_LAT_TIMER; /**< PCI latency timer register, offset: 0xD */
79 __I uint8_t PCI_CFH_HDR_TYPE; /**< PCI header type register, offset: 0xE */
80 __I uint8_t PCI_CFH_BIST; /**< PCI BIST register, offset: 0xF */
81 __I uint32_t PCI_CFH_BAR0; /**< PCI base address register 0, offset: 0x10 */
82 __I uint32_t PCI_CFH_BAR1; /**< PCI base address register 1, offset: 0x14 */
83 __I uint32_t PCI_CFH_BAR2; /**< PCI base address register 2, offset: 0x18 */
[all …]
DS32Z2_NETC_F0_PCI_HDR_TYPE0.h76 …__I uint32_t PCI_CFH_DID_VID; /**< PCI device ID and vendor ID register, offset…
78 __I uint16_t PCI_CFH_STAT; /**< PCI status register, offset: 0x6 */
79 …__I uint32_t PCI_CFH_REVID_CLASSCODE; /**< PCI revision ID and classcode register, offs…
82 __I uint8_t PCI_CFH_HDR_TYPE; /**< PCI header type register, offset: 0xE */
84 __I uint32_t PCI_CFH_BAR0; /**< PCI base address register 0, offset: 0x10 */
85 __I uint32_t PCI_CFH_BAR1; /**< PCI base address register 1, offset: 0x14 */
86 __I uint32_t PCI_CFH_BAR2; /**< PCI base address register 2, offset: 0x18 */
87 __I uint32_t PCI_CFH_BAR3; /**< PCI base address register 3, offset: 0x1C */
88 __I uint32_t PCI_CFH_BAR4; /**< PCI base address register 4, offset: 0x20 */
89 __I uint32_t PCI_CFH_BAR5; /**< PCI base address register 5, offset: 0x24 */
[all …]
DS32Z2_NETC_F1_PCI_HDR_TYPE0.h76 …__I uint32_t PCI_CFH_DID_VID; /**< PCI device ID and vendor ID register, offset…
78 __I uint16_t PCI_CFH_STAT; /**< PCI status register, offset: 0x6 */
79 …__I uint32_t PCI_CFH_REVID_CLASSCODE; /**< PCI revision ID and classcode register, offs…
82 __I uint8_t PCI_CFH_HDR_TYPE; /**< PCI header type register, offset: 0xE */
84 __I uint32_t PCI_CFH_BAR0; /**< PCI base address register 0, offset: 0x10 */
85 __I uint32_t PCI_CFH_BAR1; /**< PCI base address register 1, offset: 0x14 */
86 __I uint32_t PCI_CFH_BAR2; /**< PCI base address register 2, offset: 0x18 */
87 __I uint32_t PCI_CFH_BAR3; /**< PCI base address register 3, offset: 0x1C */
88 __I uint32_t PCI_CFH_BAR4; /**< PCI base address register 4, offset: 0x20 */
89 __I uint32_t PCI_CFH_BAR5; /**< PCI base address register 5, offset: 0x24 */
[all …]
DS32Z2_NETC_F2_PCI_HDR_TYPE0.h76 …__I uint32_t PCI_CFH_DID_VID; /**< PCI device ID and vendor ID register, offset…
78 __I uint16_t PCI_CFH_STAT; /**< PCI status register, offset: 0x6 */
79 …__I uint32_t PCI_CFH_REVID_CLASSCODE; /**< PCI revision ID and classcode register, offs…
82 __I uint8_t PCI_CFH_HDR_TYPE; /**< PCI header type register, offset: 0xE */
84 __I uint32_t PCI_CFH_BAR0; /**< PCI base address register 0, offset: 0x10 */
85 __I uint32_t PCI_CFH_BAR1; /**< PCI base address register 1, offset: 0x14 */
86 __I uint32_t PCI_CFH_BAR2; /**< PCI base address register 2, offset: 0x18 */
87 __I uint32_t PCI_CFH_BAR3; /**< PCI base address register 3, offset: 0x1C */
88 __I uint32_t PCI_CFH_BAR4; /**< PCI base address register 4, offset: 0x20 */
89 __I uint32_t PCI_CFH_BAR5; /**< PCI base address register 5, offset: 0x24 */
[all …]
DS32Z2_NETC_F2_GLOBAL.h79 …__I uint32_t SMCAPR; /**< Shared memory capability register, offset: 0…
80 …__I uint32_t SMDTR; /**< Shared memory depletion threshold register, …
81 …__I uint32_t SMACR; /**< Shared memory available count register, offs…
83 …__I uint32_t SMCLWMR; /**< Shared memory count low watermark register, …
84 …__I uint32_t SMBUCR; /**< Shared memory buffer unassigned count regist…
85 …__I uint32_t SMBUCHWMR; /**< Shared memory buffer unassigned count high w…
86 …__I uint32_t SMLCR; /**< Shared memory loss count register, offset: 0…
87 …__I uint32_t HBTCAPR; /**< Hash bucket table capability register, offse…
88 …__I uint32_t HBTOR0; /**< Hash bucket table operational register 0, of…
90 …__I uint32_t HBTOR2; /**< Hash bucket table operational register 2, of…
[all …]
DS32Z2_NETC_F3_GLOBAL.h79 …__I uint32_t SMCAPR; /**< Shared memory capability register, offset: 0…
80 …__I uint32_t SMDTR; /**< Shared memory depletion threshold register, …
81 …__I uint32_t SMACR; /**< Shared memory available count register, offs…
83 …__I uint32_t SMCLWMR; /**< Shared memory count low watermark register, …
84 …__I uint32_t SMBUCR; /**< Shared memory buffer unassigned count regist…
85 …__I uint32_t SMBUCHWMR; /**< Shared memory buffer unassigned count high w…
86 …__I uint32_t SMLCR; /**< Shared memory loss count register, offset: 0…
87 …__I uint32_t HBTCAPR; /**< Hash bucket table capability register, offse…
88 …__I uint32_t HBTOR0; /**< Hash bucket table operational register 0, of…
90 …__I uint32_t HBTOR2; /**< Hash bucket table operational register 2, of…
[all …]
DS32Z2_NETC_F0_GLOBAL.h79 …__I uint32_t SMCAPR; /**< Shared memory capability register, offset: 0…
80 …__I uint32_t SMDTR; /**< Shared memory depletion threshold register, …
81 …__I uint32_t SMACR; /**< Shared memory available count register, offs…
83 …__I uint32_t SMCLWMR; /**< Shared memory count low watermark register, …
84 …__I uint32_t SMBUCR; /**< Shared memory buffer unassigned count regist…
85 …__I uint32_t SMBUCHWMR; /**< Shared memory buffer unassigned count high w…
86 …__I uint32_t SMLCR; /**< Shared memory loss count register, offset: 0…
87 …__I uint32_t HBTCAPR; /**< Hash bucket table capability register, offse…
88 …__I uint32_t HBTOR0; /**< Hash bucket table operational register 0, of…
90 …__I uint32_t HBTOR2; /**< Hash bucket table operational register 2, of…
[all …]
DS32Z2_NETC_F1_GLOBAL.h79 …__I uint32_t SMCAPR; /**< Shared memory capability register, offset: 0…
80 …__I uint32_t SMDTR; /**< Shared memory depletion threshold register, …
81 …__I uint32_t SMACR; /**< Shared memory available count register, offs…
83 …__I uint32_t SMCLWMR; /**< Shared memory count low watermark register, …
84 …__I uint32_t SMBUCR; /**< Shared memory buffer unassigned count regist…
85 …__I uint32_t SMBUCHWMR; /**< Shared memory buffer unassigned count high w…
86 …__I uint32_t SMLCR; /**< Shared memory loss count register, offset: 0…
87 …__I uint32_t HBTCAPR; /**< Hash bucket table capability register, offse…
88 …__I uint32_t HBTOR0; /**< Hash bucket table operational register 0, of…
90 …__I uint32_t HBTOR2; /**< Hash bucket table operational register 2, of…
[all …]
DS32Z2_SIUL2.h80 …__I uint32_t MIDR1; /**< SIUL2 MCU ID 1, offset: 0x4, available only …
81 …__I uint32_t MIDR2; /**< SIUL2 MCU ID 2, offset: 0x8, available only …
99 …__I uint32_t MIDR3; /**< SIUL2 MCU ID 3, offset: 0x200, available onl…
100 …__I uint32_t MIDR4; /**< SIUL2 MCU ID 4, offset: 0x204, available onl…
282 …__I uint8_t GPDI3; /**< SIUL2 GPIO Pad Data Input, offset: 0x1500, a…
283 …__I uint8_t GPDI2; /**< SIUL2 GPIO Pad Data Input, offset: 0x1501, a…
284 …__I uint8_t GPDI1; /**< SIUL2 GPIO Pad Data Input, offset: 0x1502, a…
285 …__I uint8_t GPDI0; /**< SIUL2 GPIO Pad Data Input, offset: 0x1503, a…
286 …__I uint8_t GPDI7; /**< SIUL2 GPIO Pad Data Input, offset: 0x1504, a…
287 …__I uint8_t GPDI6; /**< SIUL2 GPIO Pad Data Input, offset: 0x1505, a…
[all …]
DS32Z2_CAN_HUB.h73 …__I uint32_t CANNETW; /**< CAN Module Connected to Bus Flag, offset: 0x…
75 __I uint32_t CAN0ALWGRP; /**< CAN0 Allowable Groups, offset: 0x80 */
76 __I uint32_t CAN1ALWGRP; /**< CAN1 Allowable Groups, offset: 0x84 */
77 __I uint32_t CAN2ALWGRP; /**< CAN2 Allowable Groups, offset: 0x88 */
78 __I uint32_t CAN3ALWGRP; /**< CAN3 Allowable Groups, offset: 0x8C */
79 __I uint32_t CAN4ALWGRP; /**< CAN4 Allowable Groups, offset: 0x90 */
80 __I uint32_t CAN5ALWGRP; /**< CAN5 Allowable Groups, offset: 0x94 */
81 __I uint32_t CAN6ALWGRP; /**< CAN6 Allowable Groups, offset: 0x98 */
82 __I uint32_t CAN7ALWGRP; /**< CAN7 Allowable Groups, offset: 0x9C */
83 __I uint32_t CAN8ALWGRP; /**< CAN8 Allowable Groups, offset: 0xA0 */
[all …]
DS32Z2_ERM.h81 …__I uint32_t EAR0; /**< ERM Memory 0 Error Address Register, offset:…
82 …__I uint32_t SYN0; /**< ERM Memory 0 Syndrome Register, offset: 0x10…
85 …__I uint32_t EAR1; /**< ERM Memory 1 Error Address Register, offset:…
86 …__I uint32_t SYN1; /**< ERM Memory 1 Syndrome Register, offset: 0x11…
89 …__I uint32_t EAR2; /**< ERM Memory 2 Error Address Register, offset:…
90 …__I uint32_t SYN2; /**< ERM Memory 2 Syndrome Register, offset: 0x12…
93 …__I uint32_t EAR3; /**< ERM Memory 3 Error Address Register, offset:…
94 …__I uint32_t SYN3; /**< ERM Memory 3 Syndrome Register, offset: 0x13…
97 …__I uint32_t EAR4; /**< ERM Memory 4 Error Address Register, offset:…
101 …__I uint32_t EAR5; /**< ERM Memory 5 Error Address Register, offset:…
[all …]
DS32Z2_SDA_AP.h73 …__I uint32_t AUTHSTTS; /**< Authentication status register, offset: 0x0 …
76 __I uint32_t KEYCHAL0; /**< Key Challenge 0 register, offset: 0x10 */
77 __I uint32_t KEYCHAL1; /**< Key Challenge 1 register, offset: 0x14 */
78 __I uint32_t KEYCHAL2; /**< Key Challenge 2 register, offset: 0x18 */
79 __I uint32_t KEYCHAL3; /**< Key Challenge 3 register, offset: 0x1C */
80 __I uint32_t KEYCHAL4; /**< Key Challenge 4 register, offset: 0x20 */
81 __I uint32_t KEYCHAL5; /**< Key Challenge 5 register, offset: 0x24 */
82 __I uint32_t KEYCHAL6; /**< Key Challenge 6 register, offset: 0x28 */
83 __I uint32_t KEYCHAL7; /**< Key Challenge 7 register, offset: 0x2C */
93 __I uint32_t SDAUIDL; /**< UID Low Register, offset: 0x70 */
[all …]
/hal_nxp-latest/s32/drivers/s32k1/BaseNXP/header/
DS32K148_ENET.h123 …__I uint32_t RMON_T_PACKETS; /**< Tx Packet Count Statistic Register, offset: …
124 …__I uint32_t RMON_T_BC_PKT; /**< Tx Broadcast Packets Statistic Register, off…
125 …__I uint32_t RMON_T_MC_PKT; /**< Tx Multicast Packets Statistic Register, off…
126 …__I uint32_t RMON_T_CRC_ALIGN; /**< Tx Packets with CRC/Align Error Statistic Re…
127 …__I uint32_t RMON_T_UNDERSIZE; /**< Tx Packets Less Than Bytes and Good CRC Stat…
128 …__I uint32_t RMON_T_OVERSIZE; /**< Tx Packets GT MAX_FL bytes and Good CRC Stat…
129 …__I uint32_t RMON_T_FRAG; /**< Tx Packets Less Than 64 Bytes and Bad CRC St…
130 …__I uint32_t RMON_T_JAB; /**< Tx Packets Greater Than MAX_FL bytes and Bad…
131 …__I uint32_t RMON_T_COL; /**< Tx Collision Count Statistic Register, offse…
132 …__I uint32_t RMON_T_P64; /**< Tx 64-Byte Packets Statistic Register, offse…
[all …]
/hal_nxp-latest/s32/drivers/s32k3/BaseNXP/header/
DS32K344_SIUL2.h80 __I uint32_t MIDR1; /**< SIUL2 MCU ID Register #1, offset: 0x4 */
81 __I uint32_t MIDR2; /**< SIUL2 MCU ID Register #2, offset: 0x8 */
98 __I uint32_t MIDR3; /**< SIUL2 MCU ID Register #3, offset: 0x200 */
99 __I uint32_t MIDR4; /**< SIUL2 MCU ID Register #4, offset: 0x204 */
325 …__I uint8_t GPDI3; /**< SIUL2 GPIO Pad Data Input Register, offset: …
326 …__I uint8_t GPDI2; /**< SIUL2 GPIO Pad Data Input Register, offset: …
327 …__I uint8_t GPDI1; /**< SIUL2 GPIO Pad Data Input Register, offset: …
328 …__I uint8_t GPDI0; /**< SIUL2 GPIO Pad Data Input Register, offset: …
329 …__I uint8_t GPDI7; /**< SIUL2 GPIO Pad Data Input Register, offset: …
330 …__I uint8_t GPDI6; /**< SIUL2 GPIO Pad Data Input Register, offset: …
[all …]

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