| /hal_nxp-latest/imx/devices/MCIMX7D/ |
| D | MCIMX7D_M4.h | 10587 …__IO uint32_t ZQCTL1; /**< ZQ Control Register 1, offset: 0x184 */ member
10674 #define DDRC_ZQCTL1_REG(base) ((base)->ZQCTL1)
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| /hal_nxp-latest/mcux/mcux-sdk/devices/MIMX8MN5/ |
| D | MIMX8MN5_cm7.h | 9230 __IO uint32_t ZQCTL1; /**< ZQ Control Register 1, offset: 0x184 */ member
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| /hal_nxp-latest/mcux/mcux-sdk/devices/MIMX8MN2/ |
| D | MIMX8MN2_cm7.h | 9228 __IO uint32_t ZQCTL1; /**< ZQ Control Register 1, offset: 0x184 */ member
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| /hal_nxp-latest/mcux/mcux-sdk/devices/MIMX8MN4/ |
| D | MIMX8MN4_cm7.h | 9228 __IO uint32_t ZQCTL1; /**< ZQ Control Register 1, offset: 0x184 */ member
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| /hal_nxp-latest/mcux/mcux-sdk/devices/MIMX8MN3/ |
| D | MIMX8MN3_cm7.h | 9230 __IO uint32_t ZQCTL1; /**< ZQ Control Register 1, offset: 0x184 */ member
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| /hal_nxp-latest/mcux/mcux-sdk/devices/MIMX8MN1/ |
| D | MIMX8MN1_cm7.h | 9230 __IO uint32_t ZQCTL1; /**< ZQ Control Register 1, offset: 0x184 */ member
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| /hal_nxp-latest/mcux/mcux-sdk/devices/MIMX8MN6/ |
| D | MIMX8MN6_cm7.h | 9228 __IO uint32_t ZQCTL1; /**< ZQ Control Register 1, offset: 0x184 */ member
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| D | MIMX8MN6_ca53.h | 9257 __IO uint32_t ZQCTL1; /**< ZQ Control Register 1, offset: 0x184 */ member
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| /hal_nxp-latest/mcux/mcux-sdk/devices/MIMX8MQ5/ |
| D | MIMX8MQ5_cm4.h | 12471 __IO uint32_t ZQCTL1; /**< ZQ Control Register 1, offset: 0x184 */ member
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| /hal_nxp-latest/mcux/mcux-sdk/devices/MIMX8MD7/ |
| D | MIMX8MD7_cm4.h | 12471 __IO uint32_t ZQCTL1; /**< ZQ Control Register 1, offset: 0x184 */ member
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| /hal_nxp-latest/mcux/mcux-sdk/devices/MIMX8MD6/ |
| D | MIMX8MD6_cm4.h | 12471 __IO uint32_t ZQCTL1; /**< ZQ Control Register 1, offset: 0x184 */ member
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| /hal_nxp-latest/mcux/mcux-sdk/devices/MIMX8MQ6/ |
| D | MIMX8MQ6_cm4.h | 12471 __IO uint32_t ZQCTL1; /**< ZQ Control Register 1, offset: 0x184 */ member
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| /hal_nxp-latest/mcux/mcux-sdk/devices/MIMX8MQ7/ |
| D | MIMX8MQ7_cm4.h | 12471 __IO uint32_t ZQCTL1; /**< ZQ Control Register 1, offset: 0x184 */ member
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| /hal_nxp-latest/mcux/mcux-sdk/devices/MIMX8MM3/ |
| D | MIMX8MM3_cm4.h | 9051 __IO uint32_t ZQCTL1; /**< ZQ Control Register 1, offset: 0x184 */ member
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| /hal_nxp-latest/mcux/mcux-sdk/devices/MIMX8MM5/ |
| D | MIMX8MM5_cm4.h | 9051 __IO uint32_t ZQCTL1; /**< ZQ Control Register 1, offset: 0x184 */ member
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| /hal_nxp-latest/mcux/mcux-sdk/devices/MIMX8MM6/ |
| D | MIMX8MM6_cm4.h | 9051 __IO uint32_t ZQCTL1; /**< ZQ Control Register 1, offset: 0x184 */ member
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| D | MIMX8MM6_ca53.h | 9075 __IO uint32_t ZQCTL1; /**< ZQ Control Register 1, offset: 0x184 */ member
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| /hal_nxp-latest/mcux/mcux-sdk/devices/MIMX8MM1/ |
| D | MIMX8MM1_cm4.h | 9051 __IO uint32_t ZQCTL1; /**< ZQ Control Register 1, offset: 0x184 */ member
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| /hal_nxp-latest/mcux/mcux-sdk/devices/MIMX8MM2/ |
| D | MIMX8MM2_cm4.h | 9051 __IO uint32_t ZQCTL1; /**< ZQ Control Register 1, offset: 0x184 */ member
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| /hal_nxp-latest/mcux/mcux-sdk/devices/MIMX8MM4/ |
| D | MIMX8MM4_cm4.h | 9051 __IO uint32_t ZQCTL1; /**< ZQ Control Register 1, offset: 0x184 */ member
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| /hal_nxp-latest/mcux/mcux-sdk/devices/MIMX8ML6/ |
| D | MIMX8ML6_cm7.h | 12988 __IO uint32_t ZQCTL1; /**< ZQ Control Register 1, offset: 0x184 */ member
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| /hal_nxp-latest/mcux/mcux-sdk/devices/MIMX8ML4/ |
| D | MIMX8ML4_cm7.h | 12988 __IO uint32_t ZQCTL1; /**< ZQ Control Register 1, offset: 0x184 */ member
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| /hal_nxp-latest/mcux/mcux-sdk/devices/MIMX8ML3/ |
| D | MIMX8ML3_cm7.h | 12988 __IO uint32_t ZQCTL1; /**< ZQ Control Register 1, offset: 0x184 */ member
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| /hal_nxp-latest/mcux/mcux-sdk/devices/MIMX8ML8/ |
| D | MIMX8ML8_dsp.h | 12633 __IO uint32_t ZQCTL1; /**< ZQ Control Register 1, offset: 0x184 */ member
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| D | MIMX8ML8_cm7.h | 12988 __IO uint32_t ZQCTL1; /**< ZQ Control Register 1, offset: 0x184 */ member
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