Home
last modified time | relevance | path

Searched refs:ZLL_IRQSTS_SRCADDR_MASK (Results 1 – 10 of 10) sorted by relevance

/hal_nxp-latest/mcux/mcux-sdk/devices/MKW30Z4/
DMKW30Z4.h12944 #define ZLL_IRQSTS_SRCADDR_MASK 0x2000u macro
12947 … (((uint32_t)(((uint32_t)(x))<<ZLL_IRQSTS_SRCADDR_SHIFT))&ZLL_IRQSTS_SRCADDR_MASK)
/hal_nxp-latest/mcux/mcux-sdk/devices/MKW21Z4/
DMKW21Z4.h12271 #define ZLL_IRQSTS_SRCADDR_MASK (0x2000U) macro
12273 … (((uint32_t)(((uint32_t)(x)) << ZLL_IRQSTS_SRCADDR_SHIFT)) & ZLL_IRQSTS_SRCADDR_MASK)
/hal_nxp-latest/mcux/mcux-sdk/devices/MKW20Z4/
DMKW20Z4.h12944 #define ZLL_IRQSTS_SRCADDR_MASK 0x2000u macro
12947 … (((uint32_t)(((uint32_t)(x))<<ZLL_IRQSTS_SRCADDR_SHIFT))&ZLL_IRQSTS_SRCADDR_MASK)
/hal_nxp-latest/mcux/mcux-sdk/devices/MKW41Z4/
DMKW41Z4.h12342 #define ZLL_IRQSTS_SRCADDR_MASK (0x2000U) macro
12344 … (((uint32_t)(((uint32_t)(x)) << ZLL_IRQSTS_SRCADDR_SHIFT)) & ZLL_IRQSTS_SRCADDR_MASK)
/hal_nxp-latest/mcux/mcux-sdk/devices/MKW40Z4/
DMKW40Z4.h12944 #define ZLL_IRQSTS_SRCADDR_MASK 0x2000u macro
12947 … (((uint32_t)(((uint32_t)(x))<<ZLL_IRQSTS_SRCADDR_SHIFT))&ZLL_IRQSTS_SRCADDR_MASK)
DMKW40Z4_extension.h44522 #define ZLL_RD_IRQSTS_SRCADDR(base) ((ZLL_IRQSTS_REG(base) & ZLL_IRQSTS_SRCADDR_MASK) >> ZLL_IRQSTS…
/hal_nxp-latest/mcux/mcux-sdk/devices/MCXW716A/
DMCXW716A.h55518 #define ZLL_IRQSTS_SRCADDR_MASK (0x2000U) macro
55521 … (((uint32_t)(((uint32_t)(x)) << ZLL_IRQSTS_SRCADDR_SHIFT)) & ZLL_IRQSTS_SRCADDR_MASK)
/hal_nxp-latest/mcux/mcux-sdk/devices/MCXW716C/
DMCXW716C.h57687 #define ZLL_IRQSTS_SRCADDR_MASK (0x2000U) macro
57690 … (((uint32_t)(((uint32_t)(x)) << ZLL_IRQSTS_SRCADDR_SHIFT)) & ZLL_IRQSTS_SRCADDR_MASK)
/hal_nxp-latest/mcux/mcux-sdk/devices/MCXW727C/
DMCXW727C_cm33_core0.h64466 #define ZLL_IRQSTS_SRCADDR_MASK (0x2000U) macro
64469 … (((uint32_t)(((uint32_t)(x)) << ZLL_IRQSTS_SRCADDR_SHIFT)) & ZLL_IRQSTS_SRCADDR_MASK)
DMCXW727C_cm33_core1.h70254 #define ZLL_IRQSTS_SRCADDR_MASK (0x2000U) macro
70257 … (((uint32_t)(((uint32_t)(x)) << ZLL_IRQSTS_SRCADDR_SHIFT)) & ZLL_IRQSTS_SRCADDR_MASK)