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Searched refs:XSPI_SPTRCLR_ABRT_CLR_MASK (Results 1 – 17 of 17) sorted by relevance

/hal_nxp-latest/mcux/mcux-sdk/drivers/xspi/
Dfsl_xspi.h1811 base->SPTRCLR |= XSPI_SPTRCLR_ABRT_CLR_MASK; in XSPI_ClearAhbBuffer()
1812 while ((base->SPTRCLR & XSPI_SPTRCLR_ABRT_CLR_MASK) != 0UL) in XSPI_ClearAhbBuffer()
/hal_nxp-latest/mcux/mcux-sdk/devices/MIMXRT798S/drivers/
Dfsl_power.c806 base->SPTRCLR |= XSPI_SPTRCLR_ABRT_CLR_MASK; in AT_QUICKACCESS_SECTION_CODE()
807 while ((base->SPTRCLR & XSPI_SPTRCLR_ABRT_CLR_MASK) != 0UL) in AT_QUICKACCESS_SECTION_CODE()
/hal_nxp-latest/mcux/mcux-sdk/devices/MIMXRT735S/drivers/
Dfsl_power.c806 base->SPTRCLR |= XSPI_SPTRCLR_ABRT_CLR_MASK; in AT_QUICKACCESS_SECTION_CODE()
807 while ((base->SPTRCLR & XSPI_SPTRCLR_ABRT_CLR_MASK) != 0UL) in AT_QUICKACCESS_SECTION_CODE()
/hal_nxp-latest/mcux/mcux-sdk/devices/MIMXRT758S/drivers/
Dfsl_power.c806 base->SPTRCLR |= XSPI_SPTRCLR_ABRT_CLR_MASK; in AT_QUICKACCESS_SECTION_CODE()
807 while ((base->SPTRCLR & XSPI_SPTRCLR_ABRT_CLR_MASK) != 0UL) in AT_QUICKACCESS_SECTION_CODE()
/hal_nxp-latest/mcux/mcux-sdk/devices/MIMXRT735S/
DMIMXRT735S_hifi1.h64948 #define XSPI_SPTRCLR_ABRT_CLR_MASK (0x10000U) macro
64954 … (((uint32_t)(((uint32_t)(x)) << XSPI_SPTRCLR_ABRT_CLR_SHIFT)) & XSPI_SPTRCLR_ABRT_CLR_MASK)
DMIMXRT735S_cm33_core1.h65017 #define XSPI_SPTRCLR_ABRT_CLR_MASK (0x10000U) macro
65023 … (((uint32_t)(((uint32_t)(x)) << XSPI_SPTRCLR_ABRT_CLR_SHIFT)) & XSPI_SPTRCLR_ABRT_CLR_MASK)
DMIMXRT735S_ezhv.h93841 #define XSPI_SPTRCLR_ABRT_CLR_MASK (0x10000U) macro
93847 … (((uint32_t)(((uint32_t)(x)) << XSPI_SPTRCLR_ABRT_CLR_SHIFT)) & XSPI_SPTRCLR_ABRT_CLR_MASK)
DMIMXRT735S_cm33_core0.h89215 #define XSPI_SPTRCLR_ABRT_CLR_MASK (0x10000U) macro
89221 … (((uint32_t)(((uint32_t)(x)) << XSPI_SPTRCLR_ABRT_CLR_SHIFT)) & XSPI_SPTRCLR_ABRT_CLR_MASK)
/hal_nxp-latest/mcux/mcux-sdk/devices/MIMXRT758S/
DMIMXRT758S_cm33_core1.h68240 #define XSPI_SPTRCLR_ABRT_CLR_MASK (0x10000U) macro
68246 … (((uint32_t)(((uint32_t)(x)) << XSPI_SPTRCLR_ABRT_CLR_SHIFT)) & XSPI_SPTRCLR_ABRT_CLR_MASK)
DMIMXRT758S_hifi1.h68169 #define XSPI_SPTRCLR_ABRT_CLR_MASK (0x10000U) macro
68175 … (((uint32_t)(((uint32_t)(x)) << XSPI_SPTRCLR_ABRT_CLR_SHIFT)) & XSPI_SPTRCLR_ABRT_CLR_MASK)
DMIMXRT758S_cm33_core0.h92440 #define XSPI_SPTRCLR_ABRT_CLR_MASK (0x10000U) macro
92446 … (((uint32_t)(((uint32_t)(x)) << XSPI_SPTRCLR_ABRT_CLR_SHIFT)) & XSPI_SPTRCLR_ABRT_CLR_MASK)
DMIMXRT758S_ezhv.h97613 #define XSPI_SPTRCLR_ABRT_CLR_MASK (0x10000U) macro
97619 … (((uint32_t)(((uint32_t)(x)) << XSPI_SPTRCLR_ABRT_CLR_SHIFT)) & XSPI_SPTRCLR_ABRT_CLR_MASK)
/hal_nxp-latest/mcux/mcux-sdk/devices/MIMXRT798S/
DMIMXRT798S_hifi1.h68169 #define XSPI_SPTRCLR_ABRT_CLR_MASK (0x10000U) macro
68175 … (((uint32_t)(((uint32_t)(x)) << XSPI_SPTRCLR_ABRT_CLR_SHIFT)) & XSPI_SPTRCLR_ABRT_CLR_MASK)
DMIMXRT798S_cm33_core1.h68240 #define XSPI_SPTRCLR_ABRT_CLR_MASK (0x10000U) macro
68246 … (((uint32_t)(((uint32_t)(x)) << XSPI_SPTRCLR_ABRT_CLR_SHIFT)) & XSPI_SPTRCLR_ABRT_CLR_MASK)
DMIMXRT798S_hifi4.h92339 #define XSPI_SPTRCLR_ABRT_CLR_MASK (0x10000U) macro
92345 … (((uint32_t)(((uint32_t)(x)) << XSPI_SPTRCLR_ABRT_CLR_SHIFT)) & XSPI_SPTRCLR_ABRT_CLR_MASK)
DMIMXRT798S_cm33_core0.h92440 #define XSPI_SPTRCLR_ABRT_CLR_MASK (0x10000U) macro
92446 … (((uint32_t)(((uint32_t)(x)) << XSPI_SPTRCLR_ABRT_CLR_SHIFT)) & XSPI_SPTRCLR_ABRT_CLR_MASK)
DMIMXRT798S_ezhv.h97637 #define XSPI_SPTRCLR_ABRT_CLR_MASK (0x10000U) macro
97643 … (((uint32_t)(((uint32_t)(x)) << XSPI_SPTRCLR_ABRT_CLR_SHIFT)) & XSPI_SPTRCLR_ABRT_CLR_MASK)