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Searched refs:XSPI_DLLCR_SLV_FINE_OFFSET_MASK (Results 1 – 15 of 15) sorted by relevance

/hal_nxp-latest/mcux/mcux-sdk/boards/mimxrt700evk/project_template/
Dboard.c223XSPI_DLLCR_SLV_FINE_OFFSET_MASK | XSPI_DLLCR_DLLRES_MASK | XSPI_DLLCR_DLL_REFCNTR_MASK | in BOARD_InitXspi()
/hal_nxp-latest/mcux/mcux-sdk/drivers/xspi/
Dfsl_xspi.c584 XSPI_DLLCR_SLV_FINE_OFFSET_MASK | XSPI_DLLCR_DLL_CDL8_MASK); in XSPI_UpdateDllValue()
628XSPI_DLLCR_SLV_FINE_OFFSET_MASK | XSPI_DLLCR_DLLRES_MASK | XSPI_DLLCR_DLL_REFCNTR_MASK | in XSPI_UpdateDllValue()
/hal_nxp-latest/mcux/mcux-sdk/devices/MIMXRT735S/
DMIMXRT735S_hifi1.h64094 #define XSPI_DLLCR_SLV_FINE_OFFSET_MASK (0xF0000U) macro
64097 …(uint32_t)(((uint32_t)(x)) << XSPI_DLLCR_SLV_FINE_OFFSET_SHIFT)) & XSPI_DLLCR_SLV_FINE_OFFSET_MASK)
DMIMXRT735S_cm33_core1.h64163 #define XSPI_DLLCR_SLV_FINE_OFFSET_MASK (0xF0000U) macro
64166 …(uint32_t)(((uint32_t)(x)) << XSPI_DLLCR_SLV_FINE_OFFSET_SHIFT)) & XSPI_DLLCR_SLV_FINE_OFFSET_MASK)
DMIMXRT735S_ezhv.h92969 #define XSPI_DLLCR_SLV_FINE_OFFSET_MASK (0xF0000U) macro
92972 …(uint32_t)(((uint32_t)(x)) << XSPI_DLLCR_SLV_FINE_OFFSET_SHIFT)) & XSPI_DLLCR_SLV_FINE_OFFSET_MASK)
DMIMXRT735S_cm33_core0.h88343 #define XSPI_DLLCR_SLV_FINE_OFFSET_MASK (0xF0000U) macro
88346 …(uint32_t)(((uint32_t)(x)) << XSPI_DLLCR_SLV_FINE_OFFSET_SHIFT)) & XSPI_DLLCR_SLV_FINE_OFFSET_MASK)
/hal_nxp-latest/mcux/mcux-sdk/devices/MIMXRT758S/
DMIMXRT758S_cm33_core1.h67386 #define XSPI_DLLCR_SLV_FINE_OFFSET_MASK (0xF0000U) macro
67389 …(uint32_t)(((uint32_t)(x)) << XSPI_DLLCR_SLV_FINE_OFFSET_SHIFT)) & XSPI_DLLCR_SLV_FINE_OFFSET_MASK)
DMIMXRT758S_hifi1.h67315 #define XSPI_DLLCR_SLV_FINE_OFFSET_MASK (0xF0000U) macro
67318 …(uint32_t)(((uint32_t)(x)) << XSPI_DLLCR_SLV_FINE_OFFSET_SHIFT)) & XSPI_DLLCR_SLV_FINE_OFFSET_MASK)
DMIMXRT758S_cm33_core0.h91568 #define XSPI_DLLCR_SLV_FINE_OFFSET_MASK (0xF0000U) macro
91571 …(uint32_t)(((uint32_t)(x)) << XSPI_DLLCR_SLV_FINE_OFFSET_SHIFT)) & XSPI_DLLCR_SLV_FINE_OFFSET_MASK)
DMIMXRT758S_ezhv.h96741 #define XSPI_DLLCR_SLV_FINE_OFFSET_MASK (0xF0000U) macro
96744 …(uint32_t)(((uint32_t)(x)) << XSPI_DLLCR_SLV_FINE_OFFSET_SHIFT)) & XSPI_DLLCR_SLV_FINE_OFFSET_MASK)
/hal_nxp-latest/mcux/mcux-sdk/devices/MIMXRT798S/
DMIMXRT798S_hifi1.h67315 #define XSPI_DLLCR_SLV_FINE_OFFSET_MASK (0xF0000U) macro
67318 …(uint32_t)(((uint32_t)(x)) << XSPI_DLLCR_SLV_FINE_OFFSET_SHIFT)) & XSPI_DLLCR_SLV_FINE_OFFSET_MASK)
DMIMXRT798S_cm33_core1.h67386 #define XSPI_DLLCR_SLV_FINE_OFFSET_MASK (0xF0000U) macro
67389 …(uint32_t)(((uint32_t)(x)) << XSPI_DLLCR_SLV_FINE_OFFSET_SHIFT)) & XSPI_DLLCR_SLV_FINE_OFFSET_MASK)
DMIMXRT798S_hifi4.h91467 #define XSPI_DLLCR_SLV_FINE_OFFSET_MASK (0xF0000U) macro
91470 …(uint32_t)(((uint32_t)(x)) << XSPI_DLLCR_SLV_FINE_OFFSET_SHIFT)) & XSPI_DLLCR_SLV_FINE_OFFSET_MASK)
DMIMXRT798S_cm33_core0.h91568 #define XSPI_DLLCR_SLV_FINE_OFFSET_MASK (0xF0000U) macro
91571 …(uint32_t)(((uint32_t)(x)) << XSPI_DLLCR_SLV_FINE_OFFSET_SHIFT)) & XSPI_DLLCR_SLV_FINE_OFFSET_MASK)
DMIMXRT798S_ezhv.h96765 #define XSPI_DLLCR_SLV_FINE_OFFSET_MASK (0xF0000U) macro
96768 …(uint32_t)(((uint32_t)(x)) << XSPI_DLLCR_SLV_FINE_OFFSET_SHIFT)) & XSPI_DLLCR_SLV_FINE_OFFSET_MASK)