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Searched refs:XSPI2_BASE (Results 1 – 13 of 13) sorted by relevance

/hal_nxp-latest/mcux/mcux-sdk/devices/MIMXRT735S/
DMIMXRT735S_hifi1.h67753 #define XSPI2_BASE (0x50411000u) macro
67757 #define XSPI2 ((XSPI_Type *)XSPI2_BASE)
67761 #define XSPI_BASE_ADDRS { 0u, 0u, XSPI2_BASE }
67770 #define XSPI2_BASE (0x40411000u) macro
67772 #define XSPI2 ((XSPI_Type *)XSPI2_BASE)
67774 #define XSPI_BASE_ADDRS { 0u, 0u, XSPI2_BASE }
DMIMXRT735S_cm33_core1.h67822 #define XSPI2_BASE (0x50411000u) macro
67826 #define XSPI2 ((XSPI_Type *)XSPI2_BASE)
67830 #define XSPI_BASE_ADDRS { 0u, 0u, XSPI2_BASE }
67839 #define XSPI2_BASE (0x40411000u) macro
67841 #define XSPI2 ((XSPI_Type *)XSPI2_BASE)
67843 #define XSPI_BASE_ADDRS { 0u, 0u, XSPI2_BASE }
DMIMXRT735S_cm33_core0.h92285 #define XSPI2_BASE (0x50411000u) macro
92289 #define XSPI2 ((XSPI_Type *)XSPI2_BASE)
92293 #define XSPI_BASE_ADDRS { XSPI0_BASE, XSPI1_BASE, XSPI2_BASE }
92310 #define XSPI2_BASE (0x40411000u) macro
92312 #define XSPI2 ((XSPI_Type *)XSPI2_BASE)
92314 #define XSPI_BASE_ADDRS { XSPI0_BASE, XSPI1_BASE, XSPI2_BASE }
DMIMXRT735S_ezhv.h96902 #define XSPI2_BASE (0x40411000u) macro
96904 #define XSPI2 ((XSPI_Type *)XSPI2_BASE)
96906 #define XSPI_BASE_ADDRS { XSPI0_BASE, XSPI1_BASE, XSPI2_BASE }
/hal_nxp-latest/mcux/mcux-sdk/devices/MIMXRT758S/
DMIMXRT758S_cm33_core1.h71045 #define XSPI2_BASE (0x50411000u) macro
71049 #define XSPI2 ((XSPI_Type *)XSPI2_BASE)
71053 #define XSPI_BASE_ADDRS { 0u, 0u, XSPI2_BASE }
71062 #define XSPI2_BASE (0x40411000u) macro
71064 #define XSPI2 ((XSPI_Type *)XSPI2_BASE)
71066 #define XSPI_BASE_ADDRS { 0u, 0u, XSPI2_BASE }
DMIMXRT758S_hifi1.h70974 #define XSPI2_BASE (0x50411000u) macro
70978 #define XSPI2 ((XSPI_Type *)XSPI2_BASE)
70982 #define XSPI_BASE_ADDRS { 0u, 0u, XSPI2_BASE }
70991 #define XSPI2_BASE (0x40411000u) macro
70993 #define XSPI2 ((XSPI_Type *)XSPI2_BASE)
70995 #define XSPI_BASE_ADDRS { 0u, 0u, XSPI2_BASE }
DMIMXRT758S_cm33_core0.h95510 #define XSPI2_BASE (0x50411000u) macro
95514 #define XSPI2 ((XSPI_Type *)XSPI2_BASE)
95518 #define XSPI_BASE_ADDRS { XSPI0_BASE, XSPI1_BASE, XSPI2_BASE }
95535 #define XSPI2_BASE (0x40411000u) macro
95537 #define XSPI2 ((XSPI_Type *)XSPI2_BASE)
95539 #define XSPI_BASE_ADDRS { XSPI0_BASE, XSPI1_BASE, XSPI2_BASE }
DMIMXRT758S_ezhv.h100674 #define XSPI2_BASE (0x40411000u) macro
100676 #define XSPI2 ((XSPI_Type *)XSPI2_BASE)
100678 #define XSPI_BASE_ADDRS { XSPI0_BASE, XSPI1_BASE, XSPI2_BASE }
/hal_nxp-latest/mcux/mcux-sdk/devices/MIMXRT798S/
DMIMXRT798S_hifi1.h70974 #define XSPI2_BASE (0x50411000u) macro
70978 #define XSPI2 ((XSPI_Type *)XSPI2_BASE)
70982 #define XSPI_BASE_ADDRS { 0u, 0u, XSPI2_BASE }
70991 #define XSPI2_BASE (0x40411000u) macro
70993 #define XSPI2 ((XSPI_Type *)XSPI2_BASE)
70995 #define XSPI_BASE_ADDRS { 0u, 0u, XSPI2_BASE }
DMIMXRT798S_cm33_core1.h71045 #define XSPI2_BASE (0x50411000u) macro
71049 #define XSPI2 ((XSPI_Type *)XSPI2_BASE)
71053 #define XSPI_BASE_ADDRS { 0u, 0u, XSPI2_BASE }
71062 #define XSPI2_BASE (0x40411000u) macro
71064 #define XSPI2 ((XSPI_Type *)XSPI2_BASE)
71066 #define XSPI_BASE_ADDRS { 0u, 0u, XSPI2_BASE }
DMIMXRT798S_hifi4.h95409 #define XSPI2_BASE (0x50411000u) macro
95413 #define XSPI2 ((XSPI_Type *)XSPI2_BASE)
95417 #define XSPI_BASE_ADDRS { XSPI0_BASE, XSPI1_BASE, XSPI2_BASE }
95434 #define XSPI2_BASE (0x40411000u) macro
95436 #define XSPI2 ((XSPI_Type *)XSPI2_BASE)
95438 #define XSPI_BASE_ADDRS { XSPI0_BASE, XSPI1_BASE, XSPI2_BASE }
DMIMXRT798S_cm33_core0.h95510 #define XSPI2_BASE (0x50411000u) macro
95514 #define XSPI2 ((XSPI_Type *)XSPI2_BASE)
95518 #define XSPI_BASE_ADDRS { XSPI0_BASE, XSPI1_BASE, XSPI2_BASE }
95535 #define XSPI2_BASE (0x40411000u) macro
95537 #define XSPI2 ((XSPI_Type *)XSPI2_BASE)
95539 #define XSPI_BASE_ADDRS { XSPI0_BASE, XSPI1_BASE, XSPI2_BASE }
DMIMXRT798S_ezhv.h100698 #define XSPI2_BASE (0x40411000u) macro
100700 #define XSPI2 ((XSPI_Type *)XSPI2_BASE)
100702 #define XSPI_BASE_ADDRS { XSPI0_BASE, XSPI1_BASE, XSPI2_BASE }