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Searched refs:XSPI1FCLKDIV_OFFSET (Results 1 – 3 of 3) sorted by relevance

/hal_nxp-latest/mcux/mcux-sdk/devices/MIMXRT735S/drivers/
Dfsl_clock.h808 #define XSPI1FCLKDIV_OFFSET 0x624 macro
1702 … kCLOCK_DivXspi1Clk = CLKCTL0_TUPLE_MUXA(XSPI1FCLKDIV_OFFSET, 0), /*!< XSPI1 Clk Divider. */
/hal_nxp-latest/mcux/mcux-sdk/devices/MIMXRT798S/drivers/
Dfsl_clock.h808 #define XSPI1FCLKDIV_OFFSET 0x624 macro
1702 … kCLOCK_DivXspi1Clk = CLKCTL0_TUPLE_MUXA(XSPI1FCLKDIV_OFFSET, 0), /*!< XSPI1 Clk Divider. */
/hal_nxp-latest/mcux/mcux-sdk/devices/MIMXRT758S/drivers/
Dfsl_clock.h808 #define XSPI1FCLKDIV_OFFSET 0x624 macro
1702 … kCLOCK_DivXspi1Clk = CLKCTL0_TUPLE_MUXA(XSPI1FCLKDIV_OFFSET, 0), /*!< XSPI1 Clk Divider. */