1 /* 2 * Copyright 1997-2016 Freescale Semiconductor, Inc. 3 * Copyright 2016-2024 NXP 4 * 5 * SPDX-License-Identifier: BSD-3-Clause 6 */ 7 8 /*! 9 * @file S32Z2_XRDC.h 10 * @version 2.3 11 * @date 2024-05-03 12 * @brief Peripheral Access Layer for S32Z2_XRDC 13 * 14 * This file contains register definitions and macros for easy access to their 15 * bit fields. 16 * 17 * This file assumes LITTLE endian system. 18 */ 19 20 /** 21 * @page misra_violations MISRA-C:2012 violations 22 * 23 * @section [global] 24 * Violates MISRA 2012 Advisory Rule 2.3, local typedef not referenced 25 * The SoC header defines typedef for all modules. 26 * 27 * @section [global] 28 * Violates MISRA 2012 Advisory Rule 2.5, local macro not referenced 29 * The SoC header defines macros for all modules and registers. 30 * 31 * @section [global] 32 * Violates MISRA 2012 Advisory Directive 4.9, Function-like macro 33 * These are generated macros used for accessing the bit-fields from registers. 34 * 35 * @section [global] 36 * Violates MISRA 2012 Required Rule 5.1, identifier clash 37 * The supported compilers use more than 31 significant characters for identifiers. 38 * 39 * @section [global] 40 * Violates MISRA 2012 Required Rule 5.2, identifier clash 41 * The supported compilers use more than 31 significant characters for identifiers. 42 * 43 * @section [global] 44 * Violates MISRA 2012 Required Rule 5.4, identifier clash 45 * The supported compilers use more than 31 significant characters for identifiers. 46 * 47 * @section [global] 48 * Violates MISRA 2012 Required Rule 5.5, identifier clash 49 * The supported compilers use more than 31 significant characters for identifiers. 50 * 51 * @section [global] 52 * Violates MISRA 2012 Required Rule 21.1, defined macro '__I' is reserved to the compiler 53 * This type qualifier is needed to ensure correct I/O access and addressing. 54 */ 55 56 /* Prevention from multiple including the same memory map */ 57 #if !defined(S32Z2_XRDC_H_) /* Check if memory map has not been already included */ 58 #define S32Z2_XRDC_H_ 59 60 #include "S32Z2_COMMON.h" 61 62 /* ---------------------------------------------------------------------------- 63 -- XRDC Peripheral Access Layer 64 ---------------------------------------------------------------------------- */ 65 66 /*! 67 * @addtogroup XRDC_Peripheral_Access_Layer XRDC Peripheral Access Layer 68 * @{ 69 */ 70 71 /** XRDC - Size of Registers Arrays */ 72 #define XRDC_MDAC_COUNT 5u 73 #define XRDC_MRC_COUNT 3u 74 #define XRDC_DERRLOC_COUNT 16u 75 #define XRDC_DERRW0_COUNT 20u 76 #define XRDC_PDAC_SLOT_PDACN_COUNT 127u 77 #define XRDC_PDAC_SLOT_COUNT 4u 78 #define XRDC_MRCN_COUNT 3u 79 #define XRDC_MRCN_MRGDN_COUNT 16u 80 81 /** XRDC - Register Layout Typedef */ 82 typedef struct { 83 __IO uint32_t CR; /**< Control, offset: 0x0 */ 84 uint8_t RESERVED_0[236]; 85 __I uint32_t HWCFG0; /**< Hardware Configuration 0, offset: 0xF0 */ 86 __I uint32_t HWCFG1; /**< Hardware Configuration 1, offset: 0xF4 */ 87 uint8_t RESERVED_1[8]; 88 __I uint8_t MDACFG[XRDC_MDAC_COUNT]; /**< Master Domain Assignment Configuration, array offset: 0x100, array step: 0x1, irregular array, not all indices are valid */ 89 uint8_t RESERVED_2[59]; 90 __I uint8_t MRCFG[XRDC_MRC_COUNT]; /**< Memory Region Configuration, array offset: 0x140, array step: 0x1, irregular array, not all indices are valid */ 91 uint8_t RESERVED_3[189]; 92 __I uint32_t DERRLOC[XRDC_DERRLOC_COUNT]; /**< Domain Error Location, array offset: 0x200, array step: 0x4 */ 93 uint8_t RESERVED_4[448]; 94 struct XRDC_DERRW0 { /* offset: 0x400, array step: 0x10 */ 95 __I uint32_t DERR_W0; /**< Domain Error Word 0, array offset: 0x400, array step: 0x10, irregular array, not all indices are valid */ 96 __I uint32_t DERR_W1; /**< Domain Error Word 1, array offset: 0x404, array step: 0x10, irregular array, not all indices are valid */ 97 uint8_t RESERVED_0[4]; 98 __O uint32_t DERR_W3; /**< Domain Error Word 3, array offset: 0x40C, array step: 0x10, irregular array, not all indices are valid */ 99 } DERRW0[XRDC_DERRW0_COUNT]; 100 uint8_t RESERVED_5[704]; 101 __IO uint32_t MDA_W0_0_DFMT1; /**< Master Domain Assignment, offset: 0x800, available only on: CE_XRDC, XRDC_0, XRDC_1, XRDC_2, XRDC_3A, XRDC_4, XRDC_5 (missing on XRDC_3B) */ 102 __IO uint32_t MDA_W1_0_DFMT1; /**< Master Domain Assignment, offset: 0x804, available only on: CE_XRDC (missing on XRDC_0, XRDC_1, XRDC_2, XRDC_3A, XRDC_3B, XRDC_4, XRDC_5) */ 103 __IO uint32_t MDA_W2_0_DFMT1; /**< Master Domain Assignment, offset: 0x808, available only on: CE_XRDC (missing on XRDC_0, XRDC_1, XRDC_2, XRDC_3A, XRDC_3B, XRDC_4, XRDC_5) */ 104 __IO uint32_t MDA_W3_0_DFMT1; /**< Master Domain Assignment, offset: 0x80C, available only on: CE_XRDC (missing on XRDC_0, XRDC_1, XRDC_2, XRDC_3A, XRDC_3B, XRDC_4, XRDC_5) */ 105 __IO uint32_t MDA_W4_0_DFMT1; /**< Master Domain Assignment, offset: 0x810, available only on: CE_XRDC (missing on XRDC_0, XRDC_1, XRDC_2, XRDC_3A, XRDC_3B, XRDC_4, XRDC_5) */ 106 __IO uint32_t MDA_W5_0_DFMT1; /**< Master Domain Assignment, offset: 0x814, available only on: CE_XRDC (missing on XRDC_0, XRDC_1, XRDC_2, XRDC_3A, XRDC_3B, XRDC_4, XRDC_5) */ 107 __IO uint32_t MDA_W6_0_DFMT1; /**< Master Domain Assignment, offset: 0x818, available only on: CE_XRDC (missing on XRDC_0, XRDC_1, XRDC_2, XRDC_3A, XRDC_3B, XRDC_4, XRDC_5) */ 108 __IO uint32_t MDA_W7_0_DFMT1; /**< Master Domain Assignment, offset: 0x81C, available only on: CE_XRDC (missing on XRDC_0, XRDC_1, XRDC_2, XRDC_3A, XRDC_3B, XRDC_4, XRDC_5) */ 109 __IO uint32_t MDA_W0_1_DFMT1; /**< Master Domain Assignment, offset: 0x820, available only on: CE_XRDC, XRDC_0, XRDC_1, XRDC_2, XRDC_3A, XRDC_4, XRDC_5 (missing on XRDC_3B) */ 110 __IO uint32_t MDA_W1_1_DFMT1; /**< Master Domain Assignment, offset: 0x824, available only on: XRDC_1, XRDC_3A (missing on CE_XRDC, XRDC_0, XRDC_2, XRDC_3B, XRDC_4, XRDC_5) */ 111 __IO uint32_t MDA_W2_1_DFMT1; /**< Master Domain Assignment, offset: 0x828, available only on: XRDC_1, XRDC_3A (missing on CE_XRDC, XRDC_0, XRDC_2, XRDC_3B, XRDC_4, XRDC_5) */ 112 __IO uint32_t MDA_W3_1_DFMT1; /**< Master Domain Assignment, offset: 0x82C, available only on: XRDC_1, XRDC_3A (missing on CE_XRDC, XRDC_0, XRDC_2, XRDC_3B, XRDC_4, XRDC_5) */ 113 __IO uint32_t MDA_W4_1_DFMT1; /**< Master Domain Assignment, offset: 0x830, available only on: XRDC_1, XRDC_3A (missing on CE_XRDC, XRDC_0, XRDC_2, XRDC_3B, XRDC_4, XRDC_5) */ 114 __IO uint32_t MDA_W5_1_DFMT1; /**< Master Domain Assignment, offset: 0x834, available only on: XRDC_1, XRDC_3A (missing on CE_XRDC, XRDC_0, XRDC_2, XRDC_3B, XRDC_4, XRDC_5) */ 115 __IO uint32_t MDA_W6_1_DFMT1; /**< Master Domain Assignment, offset: 0x838, available only on: XRDC_1, XRDC_3A (missing on CE_XRDC, XRDC_0, XRDC_2, XRDC_3B, XRDC_4, XRDC_5) */ 116 __IO uint32_t MDA_W7_1_DFMT1; /**< Master Domain Assignment, offset: 0x83C, available only on: XRDC_1, XRDC_3A (missing on CE_XRDC, XRDC_0, XRDC_2, XRDC_3B, XRDC_4, XRDC_5) */ 117 __IO uint32_t MDA_W0_2_DFMT1; /**< Master Domain Assignment, offset: 0x840, available only on: CE_XRDC, XRDC_0, XRDC_1, XRDC_2, XRDC_3A, XRDC_4, XRDC_5 (missing on XRDC_3B) */ 118 __IO uint32_t MDA_W1_2_DFMT1; /**< Master Domain Assignment, offset: 0x844, available only on: CE_XRDC, XRDC_0, XRDC_3A, XRDC_4 (missing on XRDC_1, XRDC_2, XRDC_3B, XRDC_5) */ 119 __IO uint32_t MDA_W2_2_DFMT1; /**< Master Domain Assignment, offset: 0x848, available only on: CE_XRDC, XRDC_0, XRDC_3A, XRDC_4 (missing on XRDC_1, XRDC_2, XRDC_3B, XRDC_5) */ 120 __IO uint32_t MDA_W3_2_DFMT1; /**< Master Domain Assignment, offset: 0x84C, available only on: CE_XRDC, XRDC_0, XRDC_3A, XRDC_4 (missing on XRDC_1, XRDC_2, XRDC_3B, XRDC_5) */ 121 __IO uint32_t MDA_W4_2_DFMT1; /**< Master Domain Assignment, offset: 0x850, available only on: CE_XRDC, XRDC_3A, XRDC_4 (missing on XRDC_0, XRDC_1, XRDC_2, XRDC_3B, XRDC_5) */ 122 __IO uint32_t MDA_W5_2_DFMT1; /**< Master Domain Assignment, offset: 0x854, available only on: CE_XRDC, XRDC_3A, XRDC_4 (missing on XRDC_0, XRDC_1, XRDC_2, XRDC_3B, XRDC_5) */ 123 __IO uint32_t MDA_W6_2_DFMT1; /**< Master Domain Assignment, offset: 0x858, available only on: CE_XRDC, XRDC_3A, XRDC_4 (missing on XRDC_0, XRDC_1, XRDC_2, XRDC_3B, XRDC_5) */ 124 __IO uint32_t MDA_W7_2_DFMT1; /**< Master Domain Assignment, offset: 0x85C, available only on: CE_XRDC, XRDC_3A, XRDC_4 (missing on XRDC_0, XRDC_1, XRDC_2, XRDC_3B, XRDC_5) */ 125 __IO uint32_t MDA_W0_3_DFMT1; /**< Master Domain Assignment, offset: 0x860, available only on: XRDC_0, XRDC_1 (missing on CE_XRDC, XRDC_2, XRDC_3A, XRDC_3B, XRDC_4, XRDC_5) */ 126 uint8_t RESERVED_6[28]; 127 __IO uint32_t MDA_W0_4_DFMT1; /**< Master Domain Assignment, offset: 0x880, available only on: XRDC_0, XRDC_1 (missing on CE_XRDC, XRDC_2, XRDC_3A, XRDC_3B, XRDC_4, XRDC_5) */ 128 uint8_t RESERVED_7[1916]; 129 struct XRDC_PDAC_SLOT { /* offset: 0x1000, array step: 0x400 */ 130 struct XRDC_PDAC_SLOT_PDACN { /* offset: 0x1000, array step: index*0x400, index2*0x8 */ 131 __IO uint32_t PDAC_W0; /**< Peripheral Domain Access Control Word 0, array offset: 0x1000, array step: index*0x400, index2*0x8, irregular array, not all indices are valid */ 132 __IO uint32_t PDAC_W1; /**< Peripheral Domain Access Control Word 1, array offset: 0x1004, array step: index*0x400, index2*0x8, irregular array, not all indices are valid */ 133 } PDACN[XRDC_PDAC_SLOT_PDACN_COUNT]; 134 uint8_t RESERVED_0[8]; 135 } PDAC_SLOT[XRDC_PDAC_SLOT_COUNT]; 136 struct XRDC_MRGDN { /* offset: 0x2000, array step: index*0x200, index2*0x20 */ 137 __IO uint32_t XRDC_MRGD_W0; /**< Memory Region Descriptor Word 0, array offset: 0x2000, array step: index*0x200, index2*0x20, irregular array, not all indices are valid */ 138 __IO uint32_t XRDC_MRGD_W1; /**< Memory Region Descriptor Word 1, array offset: 0x2004, array step: index*0x200, index2*0x20, irregular array, not all indices are valid */ 139 __IO uint32_t XRDC_MRGD_W2; /**< Memory Region Descriptor Word 2, array offset: 0x2008, array step: index*0x200, index2*0x20, irregular array, not all indices are valid */ 140 __IO uint32_t XRDC_MRGD_W3; /**< Memory Region Descriptor Word 3, array offset: 0x200C, array step: index*0x200, index2*0x20, irregular array, not all indices are valid */ 141 uint8_t RESERVED_0[16]; 142 } MRGDN[XRDC_MRCN_COUNT][XRDC_MRCN_MRGDN_COUNT]; 143 } XRDC_Type, *XRDC_MemMapPtr; 144 145 /** Number of instances of the XRDC module. */ 146 #define XRDC_INSTANCE_COUNT (8u) 147 148 /* XRDC - Peripheral instance base addresses */ 149 /** Peripheral CE_XRDC base address */ 150 #define IP_CE_XRDC_BASE (0x44800000u) 151 /** Peripheral CE_XRDC base pointer */ 152 #define IP_CE_XRDC ((XRDC_Type *)IP_CE_XRDC_BASE) 153 /** Peripheral XRDC_0 base address */ 154 #define IP_XRDC_0_BASE (0x40000000u) 155 /** Peripheral XRDC_0 base pointer */ 156 #define IP_XRDC_0 ((XRDC_Type *)IP_XRDC_0_BASE) 157 /** Peripheral XRDC_1 base address */ 158 #define IP_XRDC_1_BASE (0x40800000u) 159 /** Peripheral XRDC_1 base pointer */ 160 #define IP_XRDC_1 ((XRDC_Type *)IP_XRDC_1_BASE) 161 /** Peripheral XRDC_2 base address */ 162 #define IP_XRDC_2_BASE (0x41000000u) 163 /** Peripheral XRDC_2 base pointer */ 164 #define IP_XRDC_2 ((XRDC_Type *)IP_XRDC_2_BASE) 165 /** Peripheral XRDC_3A base address */ 166 #define IP_XRDC_3A_BASE (0x41800000u) 167 /** Peripheral XRDC_3A base pointer */ 168 #define IP_XRDC_3A ((XRDC_Type *)IP_XRDC_3A_BASE) 169 /** Peripheral XRDC_3B base address */ 170 #define IP_XRDC_3B_BASE (0x419D0000u) 171 /** Peripheral XRDC_3B base pointer */ 172 #define IP_XRDC_3B ((XRDC_Type *)IP_XRDC_3B_BASE) 173 /** Peripheral XRDC_4 base address */ 174 #define IP_XRDC_4_BASE (0x42000000u) 175 /** Peripheral XRDC_4 base pointer */ 176 #define IP_XRDC_4 ((XRDC_Type *)IP_XRDC_4_BASE) 177 /** Peripheral XRDC_5 base address */ 178 #define IP_XRDC_5_BASE (0x42800000u) 179 /** Peripheral XRDC_5 base pointer */ 180 #define IP_XRDC_5 ((XRDC_Type *)IP_XRDC_5_BASE) 181 /** Array initializer of XRDC peripheral base addresses */ 182 #define IP_XRDC_BASE_ADDRS { IP_CE_XRDC_BASE, IP_XRDC_0_BASE, IP_XRDC_1_BASE, IP_XRDC_2_BASE, IP_XRDC_3A_BASE, IP_XRDC_3B_BASE, IP_XRDC_4_BASE, IP_XRDC_5_BASE } 183 /** Array initializer of XRDC peripheral base pointers */ 184 #define IP_XRDC_BASE_PTRS { IP_CE_XRDC, IP_XRDC_0, IP_XRDC_1, IP_XRDC_2, IP_XRDC_3A, IP_XRDC_3B, IP_XRDC_4, IP_XRDC_5 } 185 186 /* ---------------------------------------------------------------------------- 187 -- XRDC Register Masks 188 ---------------------------------------------------------------------------- */ 189 190 /*! 191 * @addtogroup XRDC_Register_Masks XRDC Register Masks 192 * @{ 193 */ 194 195 /*! @name CR - Control */ 196 /*! @{ */ 197 198 #define XRDC_CR_GVLD_MASK (0x1U) 199 #define XRDC_CR_GVLD_SHIFT (0U) 200 #define XRDC_CR_GVLD_WIDTH (1U) 201 #define XRDC_CR_GVLD(x) (((uint32_t)(((uint32_t)(x)) << XRDC_CR_GVLD_SHIFT)) & XRDC_CR_GVLD_MASK) 202 203 #define XRDC_CR_HRL_MASK (0x1EU) 204 #define XRDC_CR_HRL_SHIFT (1U) 205 #define XRDC_CR_HRL_WIDTH (4U) 206 #define XRDC_CR_HRL(x) (((uint32_t)(((uint32_t)(x)) << XRDC_CR_HRL_SHIFT)) & XRDC_CR_HRL_MASK) 207 208 #define XRDC_CR_MRF_MASK (0x80U) 209 #define XRDC_CR_MRF_SHIFT (7U) 210 #define XRDC_CR_MRF_WIDTH (1U) 211 #define XRDC_CR_MRF(x) (((uint32_t)(((uint32_t)(x)) << XRDC_CR_MRF_SHIFT)) & XRDC_CR_MRF_MASK) 212 213 #define XRDC_CR_VAW_MASK (0x100U) 214 #define XRDC_CR_VAW_SHIFT (8U) 215 #define XRDC_CR_VAW_WIDTH (1U) 216 #define XRDC_CR_VAW(x) (((uint32_t)(((uint32_t)(x)) << XRDC_CR_VAW_SHIFT)) & XRDC_CR_VAW_MASK) 217 218 #define XRDC_CR_LK1_MASK (0x40000000U) 219 #define XRDC_CR_LK1_SHIFT (30U) 220 #define XRDC_CR_LK1_WIDTH (1U) 221 #define XRDC_CR_LK1(x) (((uint32_t)(((uint32_t)(x)) << XRDC_CR_LK1_SHIFT)) & XRDC_CR_LK1_MASK) 222 /*! @} */ 223 224 /*! @name HWCFG0 - Hardware Configuration 0 */ 225 /*! @{ */ 226 227 #define XRDC_HWCFG0_NDID_MASK (0xFFU) 228 #define XRDC_HWCFG0_NDID_SHIFT (0U) 229 #define XRDC_HWCFG0_NDID_WIDTH (8U) 230 #define XRDC_HWCFG0_NDID(x) (((uint32_t)(((uint32_t)(x)) << XRDC_HWCFG0_NDID_SHIFT)) & XRDC_HWCFG0_NDID_MASK) 231 232 #define XRDC_HWCFG0_NMSTR_MASK (0xFF00U) 233 #define XRDC_HWCFG0_NMSTR_SHIFT (8U) 234 #define XRDC_HWCFG0_NMSTR_WIDTH (8U) 235 #define XRDC_HWCFG0_NMSTR(x) (((uint32_t)(((uint32_t)(x)) << XRDC_HWCFG0_NMSTR_SHIFT)) & XRDC_HWCFG0_NMSTR_MASK) 236 237 #define XRDC_HWCFG0_NMRC_MASK (0xFF0000U) 238 #define XRDC_HWCFG0_NMRC_SHIFT (16U) 239 #define XRDC_HWCFG0_NMRC_WIDTH (8U) 240 #define XRDC_HWCFG0_NMRC(x) (((uint32_t)(((uint32_t)(x)) << XRDC_HWCFG0_NMRC_SHIFT)) & XRDC_HWCFG0_NMRC_MASK) 241 242 #define XRDC_HWCFG0_NPAC_MASK (0xF000000U) 243 #define XRDC_HWCFG0_NPAC_SHIFT (24U) 244 #define XRDC_HWCFG0_NPAC_WIDTH (4U) 245 #define XRDC_HWCFG0_NPAC(x) (((uint32_t)(((uint32_t)(x)) << XRDC_HWCFG0_NPAC_SHIFT)) & XRDC_HWCFG0_NPAC_MASK) 246 247 #define XRDC_HWCFG0_MID_MASK (0xF0000000U) 248 #define XRDC_HWCFG0_MID_SHIFT (28U) 249 #define XRDC_HWCFG0_MID_WIDTH (4U) 250 #define XRDC_HWCFG0_MID(x) (((uint32_t)(((uint32_t)(x)) << XRDC_HWCFG0_MID_SHIFT)) & XRDC_HWCFG0_MID_MASK) 251 /*! @} */ 252 253 /*! @name HWCFG1 - Hardware Configuration 1 */ 254 /*! @{ */ 255 256 #define XRDC_HWCFG1_DID_MASK (0xFU) 257 #define XRDC_HWCFG1_DID_SHIFT (0U) 258 #define XRDC_HWCFG1_DID_WIDTH (4U) 259 #define XRDC_HWCFG1_DID(x) (((uint32_t)(((uint32_t)(x)) << XRDC_HWCFG1_DID_SHIFT)) & XRDC_HWCFG1_DID_MASK) 260 /*! @} */ 261 262 /*! @name MDACFG - Master Domain Assignment Configuration */ 263 /*! @{ */ 264 265 #define XRDC_MDACFG_NMDAR_MASK (0xFU) 266 #define XRDC_MDACFG_NMDAR_SHIFT (0U) 267 #define XRDC_MDACFG_NMDAR_WIDTH (4U) 268 #define XRDC_MDACFG_NMDAR(x) (((uint8_t)(((uint8_t)(x)) << XRDC_MDACFG_NMDAR_SHIFT)) & XRDC_MDACFG_NMDAR_MASK) 269 270 #define XRDC_MDACFG_NCM_MASK (0x80U) 271 #define XRDC_MDACFG_NCM_SHIFT (7U) 272 #define XRDC_MDACFG_NCM_WIDTH (1U) 273 #define XRDC_MDACFG_NCM(x) (((uint8_t)(((uint8_t)(x)) << XRDC_MDACFG_NCM_SHIFT)) & XRDC_MDACFG_NCM_MASK) 274 /*! @} */ 275 276 /*! @name MRCFG - Memory Region Configuration */ 277 /*! @{ */ 278 279 #define XRDC_MRCFG_NMRGD_MASK (0x1FU) 280 #define XRDC_MRCFG_NMRGD_SHIFT (0U) 281 #define XRDC_MRCFG_NMRGD_WIDTH (5U) 282 #define XRDC_MRCFG_NMRGD(x) (((uint8_t)(((uint8_t)(x)) << XRDC_MRCFG_NMRGD_SHIFT)) & XRDC_MRCFG_NMRGD_MASK) 283 /*! @} */ 284 285 /*! @name DERRLOC - Domain Error Location */ 286 /*! @{ */ 287 288 #define XRDC_DERRLOC_MRCINST_MASK (0xFFFFU) 289 #define XRDC_DERRLOC_MRCINST_SHIFT (0U) 290 #define XRDC_DERRLOC_MRCINST_WIDTH (16U) 291 #define XRDC_DERRLOC_MRCINST(x) (((uint32_t)(((uint32_t)(x)) << XRDC_DERRLOC_MRCINST_SHIFT)) & XRDC_DERRLOC_MRCINST_MASK) 292 293 #define XRDC_DERRLOC_PACINST_MASK (0xF0000U) 294 #define XRDC_DERRLOC_PACINST_SHIFT (16U) 295 #define XRDC_DERRLOC_PACINST_WIDTH (4U) 296 #define XRDC_DERRLOC_PACINST(x) (((uint32_t)(((uint32_t)(x)) << XRDC_DERRLOC_PACINST_SHIFT)) & XRDC_DERRLOC_PACINST_MASK) 297 /*! @} */ 298 299 /*! @name DERR_W0 - Domain Error Word 0 */ 300 /*! @{ */ 301 302 #define XRDC_DERR_W0_EADDR_MASK (0xFFFFFFFFU) 303 #define XRDC_DERR_W0_EADDR_SHIFT (0U) 304 #define XRDC_DERR_W0_EADDR_WIDTH (32U) 305 #define XRDC_DERR_W0_EADDR(x) (((uint32_t)(((uint32_t)(x)) << XRDC_DERR_W0_EADDR_SHIFT)) & XRDC_DERR_W0_EADDR_MASK) 306 /*! @} */ 307 308 /*! @name DERR_W1 - Domain Error Word 1 */ 309 /*! @{ */ 310 311 #define XRDC_DERR_W1_EDID_MASK (0xFU) 312 #define XRDC_DERR_W1_EDID_SHIFT (0U) 313 #define XRDC_DERR_W1_EDID_WIDTH (4U) 314 #define XRDC_DERR_W1_EDID(x) (((uint32_t)(((uint32_t)(x)) << XRDC_DERR_W1_EDID_SHIFT)) & XRDC_DERR_W1_EDID_MASK) 315 316 #define XRDC_DERR_W1_EATR_MASK (0x700U) 317 #define XRDC_DERR_W1_EATR_SHIFT (8U) 318 #define XRDC_DERR_W1_EATR_WIDTH (3U) 319 #define XRDC_DERR_W1_EATR(x) (((uint32_t)(((uint32_t)(x)) << XRDC_DERR_W1_EATR_SHIFT)) & XRDC_DERR_W1_EATR_MASK) 320 321 #define XRDC_DERR_W1_ERW_MASK (0x800U) 322 #define XRDC_DERR_W1_ERW_SHIFT (11U) 323 #define XRDC_DERR_W1_ERW_WIDTH (1U) 324 #define XRDC_DERR_W1_ERW(x) (((uint32_t)(((uint32_t)(x)) << XRDC_DERR_W1_ERW_SHIFT)) & XRDC_DERR_W1_ERW_MASK) 325 326 #define XRDC_DERR_W1_EPORT_MASK (0x7000000U) 327 #define XRDC_DERR_W1_EPORT_SHIFT (24U) 328 #define XRDC_DERR_W1_EPORT_WIDTH (3U) 329 #define XRDC_DERR_W1_EPORT(x) (((uint32_t)(((uint32_t)(x)) << XRDC_DERR_W1_EPORT_SHIFT)) & XRDC_DERR_W1_EPORT_MASK) 330 331 #define XRDC_DERR_W1_EST_MASK (0xC0000000U) 332 #define XRDC_DERR_W1_EST_SHIFT (30U) 333 #define XRDC_DERR_W1_EST_WIDTH (2U) 334 #define XRDC_DERR_W1_EST(x) (((uint32_t)(((uint32_t)(x)) << XRDC_DERR_W1_EST_SHIFT)) & XRDC_DERR_W1_EST_MASK) 335 /*! @} */ 336 337 /*! @name DERR_W3 - Domain Error Word 3 */ 338 /*! @{ */ 339 340 #define XRDC_DERR_W3_RECR_MASK (0xC0000000U) 341 #define XRDC_DERR_W3_RECR_SHIFT (30U) 342 #define XRDC_DERR_W3_RECR_WIDTH (2U) 343 #define XRDC_DERR_W3_RECR(x) (((uint32_t)(((uint32_t)(x)) << XRDC_DERR_W3_RECR_SHIFT)) & XRDC_DERR_W3_RECR_MASK) 344 /*! @} */ 345 346 /*! @name MDA_W0_0_DFMT1 - Master Domain Assignment */ 347 /*! @{ */ 348 349 #define XRDC_MDA_W0_0_DFMT1_DID_MASK (0xFU) 350 #define XRDC_MDA_W0_0_DFMT1_DID_SHIFT (0U) 351 #define XRDC_MDA_W0_0_DFMT1_DID_WIDTH (4U) 352 #define XRDC_MDA_W0_0_DFMT1_DID(x) (((uint32_t)(((uint32_t)(x)) << XRDC_MDA_W0_0_DFMT1_DID_SHIFT)) & XRDC_MDA_W0_0_DFMT1_DID_MASK) 353 354 #define XRDC_MDA_W0_0_DFMT1_PA_MASK (0x30U) 355 #define XRDC_MDA_W0_0_DFMT1_PA_SHIFT (4U) 356 #define XRDC_MDA_W0_0_DFMT1_PA_WIDTH (2U) 357 #define XRDC_MDA_W0_0_DFMT1_PA(x) (((uint32_t)(((uint32_t)(x)) << XRDC_MDA_W0_0_DFMT1_PA_SHIFT)) & XRDC_MDA_W0_0_DFMT1_PA_MASK) 358 359 #define XRDC_MDA_W0_0_DFMT1_SA_MASK (0xC0U) 360 #define XRDC_MDA_W0_0_DFMT1_SA_SHIFT (6U) 361 #define XRDC_MDA_W0_0_DFMT1_SA_WIDTH (2U) 362 #define XRDC_MDA_W0_0_DFMT1_SA(x) (((uint32_t)(((uint32_t)(x)) << XRDC_MDA_W0_0_DFMT1_SA_SHIFT)) & XRDC_MDA_W0_0_DFMT1_SA_MASK) 363 364 #define XRDC_MDA_W0_0_DFMT1_DIDB_MASK (0x100U) 365 #define XRDC_MDA_W0_0_DFMT1_DIDB_SHIFT (8U) 366 #define XRDC_MDA_W0_0_DFMT1_DIDB_WIDTH (1U) 367 #define XRDC_MDA_W0_0_DFMT1_DIDB(x) (((uint32_t)(((uint32_t)(x)) << XRDC_MDA_W0_0_DFMT1_DIDB_SHIFT)) & XRDC_MDA_W0_0_DFMT1_DIDB_MASK) 368 369 #define XRDC_MDA_W0_0_DFMT1_LPID_MASK (0xF000000U) 370 #define XRDC_MDA_W0_0_DFMT1_LPID_SHIFT (24U) 371 #define XRDC_MDA_W0_0_DFMT1_LPID_WIDTH (4U) 372 #define XRDC_MDA_W0_0_DFMT1_LPID(x) (((uint32_t)(((uint32_t)(x)) << XRDC_MDA_W0_0_DFMT1_LPID_SHIFT)) & XRDC_MDA_W0_0_DFMT1_LPID_MASK) 373 374 #define XRDC_MDA_W0_0_DFMT1_LPE_MASK (0x10000000U) 375 #define XRDC_MDA_W0_0_DFMT1_LPE_SHIFT (28U) 376 #define XRDC_MDA_W0_0_DFMT1_LPE_WIDTH (1U) 377 #define XRDC_MDA_W0_0_DFMT1_LPE(x) (((uint32_t)(((uint32_t)(x)) << XRDC_MDA_W0_0_DFMT1_LPE_SHIFT)) & XRDC_MDA_W0_0_DFMT1_LPE_MASK) 378 379 #define XRDC_MDA_W0_0_DFMT1_DFMT_MASK (0x20000000U) 380 #define XRDC_MDA_W0_0_DFMT1_DFMT_SHIFT (29U) 381 #define XRDC_MDA_W0_0_DFMT1_DFMT_WIDTH (1U) 382 #define XRDC_MDA_W0_0_DFMT1_DFMT(x) (((uint32_t)(((uint32_t)(x)) << XRDC_MDA_W0_0_DFMT1_DFMT_SHIFT)) & XRDC_MDA_W0_0_DFMT1_DFMT_MASK) 383 384 #define XRDC_MDA_W0_0_DFMT1_LK1_MASK (0x40000000U) 385 #define XRDC_MDA_W0_0_DFMT1_LK1_SHIFT (30U) 386 #define XRDC_MDA_W0_0_DFMT1_LK1_WIDTH (1U) 387 #define XRDC_MDA_W0_0_DFMT1_LK1(x) (((uint32_t)(((uint32_t)(x)) << XRDC_MDA_W0_0_DFMT1_LK1_SHIFT)) & XRDC_MDA_W0_0_DFMT1_LK1_MASK) 388 389 #define XRDC_MDA_W0_0_DFMT1_VLD_MASK (0x80000000U) 390 #define XRDC_MDA_W0_0_DFMT1_VLD_SHIFT (31U) 391 #define XRDC_MDA_W0_0_DFMT1_VLD_WIDTH (1U) 392 #define XRDC_MDA_W0_0_DFMT1_VLD(x) (((uint32_t)(((uint32_t)(x)) << XRDC_MDA_W0_0_DFMT1_VLD_SHIFT)) & XRDC_MDA_W0_0_DFMT1_VLD_MASK) 393 /*! @} */ 394 395 /*! @name MDA_W1_0_DFMT1 - Master Domain Assignment */ 396 /*! @{ */ 397 398 #define XRDC_MDA_W1_0_DFMT1_DID_MASK (0xFU) 399 #define XRDC_MDA_W1_0_DFMT1_DID_SHIFT (0U) 400 #define XRDC_MDA_W1_0_DFMT1_DID_WIDTH (4U) 401 #define XRDC_MDA_W1_0_DFMT1_DID(x) (((uint32_t)(((uint32_t)(x)) << XRDC_MDA_W1_0_DFMT1_DID_SHIFT)) & XRDC_MDA_W1_0_DFMT1_DID_MASK) 402 403 #define XRDC_MDA_W1_0_DFMT1_PA_MASK (0x30U) 404 #define XRDC_MDA_W1_0_DFMT1_PA_SHIFT (4U) 405 #define XRDC_MDA_W1_0_DFMT1_PA_WIDTH (2U) 406 #define XRDC_MDA_W1_0_DFMT1_PA(x) (((uint32_t)(((uint32_t)(x)) << XRDC_MDA_W1_0_DFMT1_PA_SHIFT)) & XRDC_MDA_W1_0_DFMT1_PA_MASK) 407 408 #define XRDC_MDA_W1_0_DFMT1_SA_MASK (0xC0U) 409 #define XRDC_MDA_W1_0_DFMT1_SA_SHIFT (6U) 410 #define XRDC_MDA_W1_0_DFMT1_SA_WIDTH (2U) 411 #define XRDC_MDA_W1_0_DFMT1_SA(x) (((uint32_t)(((uint32_t)(x)) << XRDC_MDA_W1_0_DFMT1_SA_SHIFT)) & XRDC_MDA_W1_0_DFMT1_SA_MASK) 412 413 #define XRDC_MDA_W1_0_DFMT1_DIDB_MASK (0x100U) 414 #define XRDC_MDA_W1_0_DFMT1_DIDB_SHIFT (8U) 415 #define XRDC_MDA_W1_0_DFMT1_DIDB_WIDTH (1U) 416 #define XRDC_MDA_W1_0_DFMT1_DIDB(x) (((uint32_t)(((uint32_t)(x)) << XRDC_MDA_W1_0_DFMT1_DIDB_SHIFT)) & XRDC_MDA_W1_0_DFMT1_DIDB_MASK) 417 418 #define XRDC_MDA_W1_0_DFMT1_LPID_MASK (0xF000000U) 419 #define XRDC_MDA_W1_0_DFMT1_LPID_SHIFT (24U) 420 #define XRDC_MDA_W1_0_DFMT1_LPID_WIDTH (4U) 421 #define XRDC_MDA_W1_0_DFMT1_LPID(x) (((uint32_t)(((uint32_t)(x)) << XRDC_MDA_W1_0_DFMT1_LPID_SHIFT)) & XRDC_MDA_W1_0_DFMT1_LPID_MASK) 422 423 #define XRDC_MDA_W1_0_DFMT1_LPE_MASK (0x10000000U) 424 #define XRDC_MDA_W1_0_DFMT1_LPE_SHIFT (28U) 425 #define XRDC_MDA_W1_0_DFMT1_LPE_WIDTH (1U) 426 #define XRDC_MDA_W1_0_DFMT1_LPE(x) (((uint32_t)(((uint32_t)(x)) << XRDC_MDA_W1_0_DFMT1_LPE_SHIFT)) & XRDC_MDA_W1_0_DFMT1_LPE_MASK) 427 428 #define XRDC_MDA_W1_0_DFMT1_DFMT_MASK (0x20000000U) 429 #define XRDC_MDA_W1_0_DFMT1_DFMT_SHIFT (29U) 430 #define XRDC_MDA_W1_0_DFMT1_DFMT_WIDTH (1U) 431 #define XRDC_MDA_W1_0_DFMT1_DFMT(x) (((uint32_t)(((uint32_t)(x)) << XRDC_MDA_W1_0_DFMT1_DFMT_SHIFT)) & XRDC_MDA_W1_0_DFMT1_DFMT_MASK) 432 433 #define XRDC_MDA_W1_0_DFMT1_LK1_MASK (0x40000000U) 434 #define XRDC_MDA_W1_0_DFMT1_LK1_SHIFT (30U) 435 #define XRDC_MDA_W1_0_DFMT1_LK1_WIDTH (1U) 436 #define XRDC_MDA_W1_0_DFMT1_LK1(x) (((uint32_t)(((uint32_t)(x)) << XRDC_MDA_W1_0_DFMT1_LK1_SHIFT)) & XRDC_MDA_W1_0_DFMT1_LK1_MASK) 437 438 #define XRDC_MDA_W1_0_DFMT1_VLD_MASK (0x80000000U) 439 #define XRDC_MDA_W1_0_DFMT1_VLD_SHIFT (31U) 440 #define XRDC_MDA_W1_0_DFMT1_VLD_WIDTH (1U) 441 #define XRDC_MDA_W1_0_DFMT1_VLD(x) (((uint32_t)(((uint32_t)(x)) << XRDC_MDA_W1_0_DFMT1_VLD_SHIFT)) & XRDC_MDA_W1_0_DFMT1_VLD_MASK) 442 /*! @} */ 443 444 /*! @name MDA_W2_0_DFMT1 - Master Domain Assignment */ 445 /*! @{ */ 446 447 #define XRDC_MDA_W2_0_DFMT1_DID_MASK (0xFU) 448 #define XRDC_MDA_W2_0_DFMT1_DID_SHIFT (0U) 449 #define XRDC_MDA_W2_0_DFMT1_DID_WIDTH (4U) 450 #define XRDC_MDA_W2_0_DFMT1_DID(x) (((uint32_t)(((uint32_t)(x)) << XRDC_MDA_W2_0_DFMT1_DID_SHIFT)) & XRDC_MDA_W2_0_DFMT1_DID_MASK) 451 452 #define XRDC_MDA_W2_0_DFMT1_PA_MASK (0x30U) 453 #define XRDC_MDA_W2_0_DFMT1_PA_SHIFT (4U) 454 #define XRDC_MDA_W2_0_DFMT1_PA_WIDTH (2U) 455 #define XRDC_MDA_W2_0_DFMT1_PA(x) (((uint32_t)(((uint32_t)(x)) << XRDC_MDA_W2_0_DFMT1_PA_SHIFT)) & XRDC_MDA_W2_0_DFMT1_PA_MASK) 456 457 #define XRDC_MDA_W2_0_DFMT1_SA_MASK (0xC0U) 458 #define XRDC_MDA_W2_0_DFMT1_SA_SHIFT (6U) 459 #define XRDC_MDA_W2_0_DFMT1_SA_WIDTH (2U) 460 #define XRDC_MDA_W2_0_DFMT1_SA(x) (((uint32_t)(((uint32_t)(x)) << XRDC_MDA_W2_0_DFMT1_SA_SHIFT)) & XRDC_MDA_W2_0_DFMT1_SA_MASK) 461 462 #define XRDC_MDA_W2_0_DFMT1_DIDB_MASK (0x100U) 463 #define XRDC_MDA_W2_0_DFMT1_DIDB_SHIFT (8U) 464 #define XRDC_MDA_W2_0_DFMT1_DIDB_WIDTH (1U) 465 #define XRDC_MDA_W2_0_DFMT1_DIDB(x) (((uint32_t)(((uint32_t)(x)) << XRDC_MDA_W2_0_DFMT1_DIDB_SHIFT)) & XRDC_MDA_W2_0_DFMT1_DIDB_MASK) 466 467 #define XRDC_MDA_W2_0_DFMT1_LPID_MASK (0xF000000U) 468 #define XRDC_MDA_W2_0_DFMT1_LPID_SHIFT (24U) 469 #define XRDC_MDA_W2_0_DFMT1_LPID_WIDTH (4U) 470 #define XRDC_MDA_W2_0_DFMT1_LPID(x) (((uint32_t)(((uint32_t)(x)) << XRDC_MDA_W2_0_DFMT1_LPID_SHIFT)) & XRDC_MDA_W2_0_DFMT1_LPID_MASK) 471 472 #define XRDC_MDA_W2_0_DFMT1_LPE_MASK (0x10000000U) 473 #define XRDC_MDA_W2_0_DFMT1_LPE_SHIFT (28U) 474 #define XRDC_MDA_W2_0_DFMT1_LPE_WIDTH (1U) 475 #define XRDC_MDA_W2_0_DFMT1_LPE(x) (((uint32_t)(((uint32_t)(x)) << XRDC_MDA_W2_0_DFMT1_LPE_SHIFT)) & XRDC_MDA_W2_0_DFMT1_LPE_MASK) 476 477 #define XRDC_MDA_W2_0_DFMT1_DFMT_MASK (0x20000000U) 478 #define XRDC_MDA_W2_0_DFMT1_DFMT_SHIFT (29U) 479 #define XRDC_MDA_W2_0_DFMT1_DFMT_WIDTH (1U) 480 #define XRDC_MDA_W2_0_DFMT1_DFMT(x) (((uint32_t)(((uint32_t)(x)) << XRDC_MDA_W2_0_DFMT1_DFMT_SHIFT)) & XRDC_MDA_W2_0_DFMT1_DFMT_MASK) 481 482 #define XRDC_MDA_W2_0_DFMT1_LK1_MASK (0x40000000U) 483 #define XRDC_MDA_W2_0_DFMT1_LK1_SHIFT (30U) 484 #define XRDC_MDA_W2_0_DFMT1_LK1_WIDTH (1U) 485 #define XRDC_MDA_W2_0_DFMT1_LK1(x) (((uint32_t)(((uint32_t)(x)) << XRDC_MDA_W2_0_DFMT1_LK1_SHIFT)) & XRDC_MDA_W2_0_DFMT1_LK1_MASK) 486 487 #define XRDC_MDA_W2_0_DFMT1_VLD_MASK (0x80000000U) 488 #define XRDC_MDA_W2_0_DFMT1_VLD_SHIFT (31U) 489 #define XRDC_MDA_W2_0_DFMT1_VLD_WIDTH (1U) 490 #define XRDC_MDA_W2_0_DFMT1_VLD(x) (((uint32_t)(((uint32_t)(x)) << XRDC_MDA_W2_0_DFMT1_VLD_SHIFT)) & XRDC_MDA_W2_0_DFMT1_VLD_MASK) 491 /*! @} */ 492 493 /*! @name MDA_W3_0_DFMT1 - Master Domain Assignment */ 494 /*! @{ */ 495 496 #define XRDC_MDA_W3_0_DFMT1_DID_MASK (0xFU) 497 #define XRDC_MDA_W3_0_DFMT1_DID_SHIFT (0U) 498 #define XRDC_MDA_W3_0_DFMT1_DID_WIDTH (4U) 499 #define XRDC_MDA_W3_0_DFMT1_DID(x) (((uint32_t)(((uint32_t)(x)) << XRDC_MDA_W3_0_DFMT1_DID_SHIFT)) & XRDC_MDA_W3_0_DFMT1_DID_MASK) 500 501 #define XRDC_MDA_W3_0_DFMT1_PA_MASK (0x30U) 502 #define XRDC_MDA_W3_0_DFMT1_PA_SHIFT (4U) 503 #define XRDC_MDA_W3_0_DFMT1_PA_WIDTH (2U) 504 #define XRDC_MDA_W3_0_DFMT1_PA(x) (((uint32_t)(((uint32_t)(x)) << XRDC_MDA_W3_0_DFMT1_PA_SHIFT)) & XRDC_MDA_W3_0_DFMT1_PA_MASK) 505 506 #define XRDC_MDA_W3_0_DFMT1_SA_MASK (0xC0U) 507 #define XRDC_MDA_W3_0_DFMT1_SA_SHIFT (6U) 508 #define XRDC_MDA_W3_0_DFMT1_SA_WIDTH (2U) 509 #define XRDC_MDA_W3_0_DFMT1_SA(x) (((uint32_t)(((uint32_t)(x)) << XRDC_MDA_W3_0_DFMT1_SA_SHIFT)) & XRDC_MDA_W3_0_DFMT1_SA_MASK) 510 511 #define XRDC_MDA_W3_0_DFMT1_DIDB_MASK (0x100U) 512 #define XRDC_MDA_W3_0_DFMT1_DIDB_SHIFT (8U) 513 #define XRDC_MDA_W3_0_DFMT1_DIDB_WIDTH (1U) 514 #define XRDC_MDA_W3_0_DFMT1_DIDB(x) (((uint32_t)(((uint32_t)(x)) << XRDC_MDA_W3_0_DFMT1_DIDB_SHIFT)) & XRDC_MDA_W3_0_DFMT1_DIDB_MASK) 515 516 #define XRDC_MDA_W3_0_DFMT1_LPID_MASK (0xF000000U) 517 #define XRDC_MDA_W3_0_DFMT1_LPID_SHIFT (24U) 518 #define XRDC_MDA_W3_0_DFMT1_LPID_WIDTH (4U) 519 #define XRDC_MDA_W3_0_DFMT1_LPID(x) (((uint32_t)(((uint32_t)(x)) << XRDC_MDA_W3_0_DFMT1_LPID_SHIFT)) & XRDC_MDA_W3_0_DFMT1_LPID_MASK) 520 521 #define XRDC_MDA_W3_0_DFMT1_LPE_MASK (0x10000000U) 522 #define XRDC_MDA_W3_0_DFMT1_LPE_SHIFT (28U) 523 #define XRDC_MDA_W3_0_DFMT1_LPE_WIDTH (1U) 524 #define XRDC_MDA_W3_0_DFMT1_LPE(x) (((uint32_t)(((uint32_t)(x)) << XRDC_MDA_W3_0_DFMT1_LPE_SHIFT)) & XRDC_MDA_W3_0_DFMT1_LPE_MASK) 525 526 #define XRDC_MDA_W3_0_DFMT1_DFMT_MASK (0x20000000U) 527 #define XRDC_MDA_W3_0_DFMT1_DFMT_SHIFT (29U) 528 #define XRDC_MDA_W3_0_DFMT1_DFMT_WIDTH (1U) 529 #define XRDC_MDA_W3_0_DFMT1_DFMT(x) (((uint32_t)(((uint32_t)(x)) << XRDC_MDA_W3_0_DFMT1_DFMT_SHIFT)) & XRDC_MDA_W3_0_DFMT1_DFMT_MASK) 530 531 #define XRDC_MDA_W3_0_DFMT1_LK1_MASK (0x40000000U) 532 #define XRDC_MDA_W3_0_DFMT1_LK1_SHIFT (30U) 533 #define XRDC_MDA_W3_0_DFMT1_LK1_WIDTH (1U) 534 #define XRDC_MDA_W3_0_DFMT1_LK1(x) (((uint32_t)(((uint32_t)(x)) << XRDC_MDA_W3_0_DFMT1_LK1_SHIFT)) & XRDC_MDA_W3_0_DFMT1_LK1_MASK) 535 536 #define XRDC_MDA_W3_0_DFMT1_VLD_MASK (0x80000000U) 537 #define XRDC_MDA_W3_0_DFMT1_VLD_SHIFT (31U) 538 #define XRDC_MDA_W3_0_DFMT1_VLD_WIDTH (1U) 539 #define XRDC_MDA_W3_0_DFMT1_VLD(x) (((uint32_t)(((uint32_t)(x)) << XRDC_MDA_W3_0_DFMT1_VLD_SHIFT)) & XRDC_MDA_W3_0_DFMT1_VLD_MASK) 540 /*! @} */ 541 542 /*! @name MDA_W4_0_DFMT1 - Master Domain Assignment */ 543 /*! @{ */ 544 545 #define XRDC_MDA_W4_0_DFMT1_DID_MASK (0xFU) 546 #define XRDC_MDA_W4_0_DFMT1_DID_SHIFT (0U) 547 #define XRDC_MDA_W4_0_DFMT1_DID_WIDTH (4U) 548 #define XRDC_MDA_W4_0_DFMT1_DID(x) (((uint32_t)(((uint32_t)(x)) << XRDC_MDA_W4_0_DFMT1_DID_SHIFT)) & XRDC_MDA_W4_0_DFMT1_DID_MASK) 549 550 #define XRDC_MDA_W4_0_DFMT1_PA_MASK (0x30U) 551 #define XRDC_MDA_W4_0_DFMT1_PA_SHIFT (4U) 552 #define XRDC_MDA_W4_0_DFMT1_PA_WIDTH (2U) 553 #define XRDC_MDA_W4_0_DFMT1_PA(x) (((uint32_t)(((uint32_t)(x)) << XRDC_MDA_W4_0_DFMT1_PA_SHIFT)) & XRDC_MDA_W4_0_DFMT1_PA_MASK) 554 555 #define XRDC_MDA_W4_0_DFMT1_SA_MASK (0xC0U) 556 #define XRDC_MDA_W4_0_DFMT1_SA_SHIFT (6U) 557 #define XRDC_MDA_W4_0_DFMT1_SA_WIDTH (2U) 558 #define XRDC_MDA_W4_0_DFMT1_SA(x) (((uint32_t)(((uint32_t)(x)) << XRDC_MDA_W4_0_DFMT1_SA_SHIFT)) & XRDC_MDA_W4_0_DFMT1_SA_MASK) 559 560 #define XRDC_MDA_W4_0_DFMT1_DIDB_MASK (0x100U) 561 #define XRDC_MDA_W4_0_DFMT1_DIDB_SHIFT (8U) 562 #define XRDC_MDA_W4_0_DFMT1_DIDB_WIDTH (1U) 563 #define XRDC_MDA_W4_0_DFMT1_DIDB(x) (((uint32_t)(((uint32_t)(x)) << XRDC_MDA_W4_0_DFMT1_DIDB_SHIFT)) & XRDC_MDA_W4_0_DFMT1_DIDB_MASK) 564 565 #define XRDC_MDA_W4_0_DFMT1_LPID_MASK (0xF000000U) 566 #define XRDC_MDA_W4_0_DFMT1_LPID_SHIFT (24U) 567 #define XRDC_MDA_W4_0_DFMT1_LPID_WIDTH (4U) 568 #define XRDC_MDA_W4_0_DFMT1_LPID(x) (((uint32_t)(((uint32_t)(x)) << XRDC_MDA_W4_0_DFMT1_LPID_SHIFT)) & XRDC_MDA_W4_0_DFMT1_LPID_MASK) 569 570 #define XRDC_MDA_W4_0_DFMT1_LPE_MASK (0x10000000U) 571 #define XRDC_MDA_W4_0_DFMT1_LPE_SHIFT (28U) 572 #define XRDC_MDA_W4_0_DFMT1_LPE_WIDTH (1U) 573 #define XRDC_MDA_W4_0_DFMT1_LPE(x) (((uint32_t)(((uint32_t)(x)) << XRDC_MDA_W4_0_DFMT1_LPE_SHIFT)) & XRDC_MDA_W4_0_DFMT1_LPE_MASK) 574 575 #define XRDC_MDA_W4_0_DFMT1_DFMT_MASK (0x20000000U) 576 #define XRDC_MDA_W4_0_DFMT1_DFMT_SHIFT (29U) 577 #define XRDC_MDA_W4_0_DFMT1_DFMT_WIDTH (1U) 578 #define XRDC_MDA_W4_0_DFMT1_DFMT(x) (((uint32_t)(((uint32_t)(x)) << XRDC_MDA_W4_0_DFMT1_DFMT_SHIFT)) & XRDC_MDA_W4_0_DFMT1_DFMT_MASK) 579 580 #define XRDC_MDA_W4_0_DFMT1_LK1_MASK (0x40000000U) 581 #define XRDC_MDA_W4_0_DFMT1_LK1_SHIFT (30U) 582 #define XRDC_MDA_W4_0_DFMT1_LK1_WIDTH (1U) 583 #define XRDC_MDA_W4_0_DFMT1_LK1(x) (((uint32_t)(((uint32_t)(x)) << XRDC_MDA_W4_0_DFMT1_LK1_SHIFT)) & XRDC_MDA_W4_0_DFMT1_LK1_MASK) 584 585 #define XRDC_MDA_W4_0_DFMT1_VLD_MASK (0x80000000U) 586 #define XRDC_MDA_W4_0_DFMT1_VLD_SHIFT (31U) 587 #define XRDC_MDA_W4_0_DFMT1_VLD_WIDTH (1U) 588 #define XRDC_MDA_W4_0_DFMT1_VLD(x) (((uint32_t)(((uint32_t)(x)) << XRDC_MDA_W4_0_DFMT1_VLD_SHIFT)) & XRDC_MDA_W4_0_DFMT1_VLD_MASK) 589 /*! @} */ 590 591 /*! @name MDA_W5_0_DFMT1 - Master Domain Assignment */ 592 /*! @{ */ 593 594 #define XRDC_MDA_W5_0_DFMT1_DID_MASK (0xFU) 595 #define XRDC_MDA_W5_0_DFMT1_DID_SHIFT (0U) 596 #define XRDC_MDA_W5_0_DFMT1_DID_WIDTH (4U) 597 #define XRDC_MDA_W5_0_DFMT1_DID(x) (((uint32_t)(((uint32_t)(x)) << XRDC_MDA_W5_0_DFMT1_DID_SHIFT)) & XRDC_MDA_W5_0_DFMT1_DID_MASK) 598 599 #define XRDC_MDA_W5_0_DFMT1_PA_MASK (0x30U) 600 #define XRDC_MDA_W5_0_DFMT1_PA_SHIFT (4U) 601 #define XRDC_MDA_W5_0_DFMT1_PA_WIDTH (2U) 602 #define XRDC_MDA_W5_0_DFMT1_PA(x) (((uint32_t)(((uint32_t)(x)) << XRDC_MDA_W5_0_DFMT1_PA_SHIFT)) & XRDC_MDA_W5_0_DFMT1_PA_MASK) 603 604 #define XRDC_MDA_W5_0_DFMT1_SA_MASK (0xC0U) 605 #define XRDC_MDA_W5_0_DFMT1_SA_SHIFT (6U) 606 #define XRDC_MDA_W5_0_DFMT1_SA_WIDTH (2U) 607 #define XRDC_MDA_W5_0_DFMT1_SA(x) (((uint32_t)(((uint32_t)(x)) << XRDC_MDA_W5_0_DFMT1_SA_SHIFT)) & XRDC_MDA_W5_0_DFMT1_SA_MASK) 608 609 #define XRDC_MDA_W5_0_DFMT1_DIDB_MASK (0x100U) 610 #define XRDC_MDA_W5_0_DFMT1_DIDB_SHIFT (8U) 611 #define XRDC_MDA_W5_0_DFMT1_DIDB_WIDTH (1U) 612 #define XRDC_MDA_W5_0_DFMT1_DIDB(x) (((uint32_t)(((uint32_t)(x)) << XRDC_MDA_W5_0_DFMT1_DIDB_SHIFT)) & XRDC_MDA_W5_0_DFMT1_DIDB_MASK) 613 614 #define XRDC_MDA_W5_0_DFMT1_LPID_MASK (0xF000000U) 615 #define XRDC_MDA_W5_0_DFMT1_LPID_SHIFT (24U) 616 #define XRDC_MDA_W5_0_DFMT1_LPID_WIDTH (4U) 617 #define XRDC_MDA_W5_0_DFMT1_LPID(x) (((uint32_t)(((uint32_t)(x)) << XRDC_MDA_W5_0_DFMT1_LPID_SHIFT)) & XRDC_MDA_W5_0_DFMT1_LPID_MASK) 618 619 #define XRDC_MDA_W5_0_DFMT1_LPE_MASK (0x10000000U) 620 #define XRDC_MDA_W5_0_DFMT1_LPE_SHIFT (28U) 621 #define XRDC_MDA_W5_0_DFMT1_LPE_WIDTH (1U) 622 #define XRDC_MDA_W5_0_DFMT1_LPE(x) (((uint32_t)(((uint32_t)(x)) << XRDC_MDA_W5_0_DFMT1_LPE_SHIFT)) & XRDC_MDA_W5_0_DFMT1_LPE_MASK) 623 624 #define XRDC_MDA_W5_0_DFMT1_DFMT_MASK (0x20000000U) 625 #define XRDC_MDA_W5_0_DFMT1_DFMT_SHIFT (29U) 626 #define XRDC_MDA_W5_0_DFMT1_DFMT_WIDTH (1U) 627 #define XRDC_MDA_W5_0_DFMT1_DFMT(x) (((uint32_t)(((uint32_t)(x)) << XRDC_MDA_W5_0_DFMT1_DFMT_SHIFT)) & XRDC_MDA_W5_0_DFMT1_DFMT_MASK) 628 629 #define XRDC_MDA_W5_0_DFMT1_LK1_MASK (0x40000000U) 630 #define XRDC_MDA_W5_0_DFMT1_LK1_SHIFT (30U) 631 #define XRDC_MDA_W5_0_DFMT1_LK1_WIDTH (1U) 632 #define XRDC_MDA_W5_0_DFMT1_LK1(x) (((uint32_t)(((uint32_t)(x)) << XRDC_MDA_W5_0_DFMT1_LK1_SHIFT)) & XRDC_MDA_W5_0_DFMT1_LK1_MASK) 633 634 #define XRDC_MDA_W5_0_DFMT1_VLD_MASK (0x80000000U) 635 #define XRDC_MDA_W5_0_DFMT1_VLD_SHIFT (31U) 636 #define XRDC_MDA_W5_0_DFMT1_VLD_WIDTH (1U) 637 #define XRDC_MDA_W5_0_DFMT1_VLD(x) (((uint32_t)(((uint32_t)(x)) << XRDC_MDA_W5_0_DFMT1_VLD_SHIFT)) & XRDC_MDA_W5_0_DFMT1_VLD_MASK) 638 /*! @} */ 639 640 /*! @name MDA_W6_0_DFMT1 - Master Domain Assignment */ 641 /*! @{ */ 642 643 #define XRDC_MDA_W6_0_DFMT1_DID_MASK (0xFU) 644 #define XRDC_MDA_W6_0_DFMT1_DID_SHIFT (0U) 645 #define XRDC_MDA_W6_0_DFMT1_DID_WIDTH (4U) 646 #define XRDC_MDA_W6_0_DFMT1_DID(x) (((uint32_t)(((uint32_t)(x)) << XRDC_MDA_W6_0_DFMT1_DID_SHIFT)) & XRDC_MDA_W6_0_DFMT1_DID_MASK) 647 648 #define XRDC_MDA_W6_0_DFMT1_PA_MASK (0x30U) 649 #define XRDC_MDA_W6_0_DFMT1_PA_SHIFT (4U) 650 #define XRDC_MDA_W6_0_DFMT1_PA_WIDTH (2U) 651 #define XRDC_MDA_W6_0_DFMT1_PA(x) (((uint32_t)(((uint32_t)(x)) << XRDC_MDA_W6_0_DFMT1_PA_SHIFT)) & XRDC_MDA_W6_0_DFMT1_PA_MASK) 652 653 #define XRDC_MDA_W6_0_DFMT1_SA_MASK (0xC0U) 654 #define XRDC_MDA_W6_0_DFMT1_SA_SHIFT (6U) 655 #define XRDC_MDA_W6_0_DFMT1_SA_WIDTH (2U) 656 #define XRDC_MDA_W6_0_DFMT1_SA(x) (((uint32_t)(((uint32_t)(x)) << XRDC_MDA_W6_0_DFMT1_SA_SHIFT)) & XRDC_MDA_W6_0_DFMT1_SA_MASK) 657 658 #define XRDC_MDA_W6_0_DFMT1_DIDB_MASK (0x100U) 659 #define XRDC_MDA_W6_0_DFMT1_DIDB_SHIFT (8U) 660 #define XRDC_MDA_W6_0_DFMT1_DIDB_WIDTH (1U) 661 #define XRDC_MDA_W6_0_DFMT1_DIDB(x) (((uint32_t)(((uint32_t)(x)) << XRDC_MDA_W6_0_DFMT1_DIDB_SHIFT)) & XRDC_MDA_W6_0_DFMT1_DIDB_MASK) 662 663 #define XRDC_MDA_W6_0_DFMT1_LPID_MASK (0xF000000U) 664 #define XRDC_MDA_W6_0_DFMT1_LPID_SHIFT (24U) 665 #define XRDC_MDA_W6_0_DFMT1_LPID_WIDTH (4U) 666 #define XRDC_MDA_W6_0_DFMT1_LPID(x) (((uint32_t)(((uint32_t)(x)) << XRDC_MDA_W6_0_DFMT1_LPID_SHIFT)) & XRDC_MDA_W6_0_DFMT1_LPID_MASK) 667 668 #define XRDC_MDA_W6_0_DFMT1_LPE_MASK (0x10000000U) 669 #define XRDC_MDA_W6_0_DFMT1_LPE_SHIFT (28U) 670 #define XRDC_MDA_W6_0_DFMT1_LPE_WIDTH (1U) 671 #define XRDC_MDA_W6_0_DFMT1_LPE(x) (((uint32_t)(((uint32_t)(x)) << XRDC_MDA_W6_0_DFMT1_LPE_SHIFT)) & XRDC_MDA_W6_0_DFMT1_LPE_MASK) 672 673 #define XRDC_MDA_W6_0_DFMT1_DFMT_MASK (0x20000000U) 674 #define XRDC_MDA_W6_0_DFMT1_DFMT_SHIFT (29U) 675 #define XRDC_MDA_W6_0_DFMT1_DFMT_WIDTH (1U) 676 #define XRDC_MDA_W6_0_DFMT1_DFMT(x) (((uint32_t)(((uint32_t)(x)) << XRDC_MDA_W6_0_DFMT1_DFMT_SHIFT)) & XRDC_MDA_W6_0_DFMT1_DFMT_MASK) 677 678 #define XRDC_MDA_W6_0_DFMT1_LK1_MASK (0x40000000U) 679 #define XRDC_MDA_W6_0_DFMT1_LK1_SHIFT (30U) 680 #define XRDC_MDA_W6_0_DFMT1_LK1_WIDTH (1U) 681 #define XRDC_MDA_W6_0_DFMT1_LK1(x) (((uint32_t)(((uint32_t)(x)) << XRDC_MDA_W6_0_DFMT1_LK1_SHIFT)) & XRDC_MDA_W6_0_DFMT1_LK1_MASK) 682 683 #define XRDC_MDA_W6_0_DFMT1_VLD_MASK (0x80000000U) 684 #define XRDC_MDA_W6_0_DFMT1_VLD_SHIFT (31U) 685 #define XRDC_MDA_W6_0_DFMT1_VLD_WIDTH (1U) 686 #define XRDC_MDA_W6_0_DFMT1_VLD(x) (((uint32_t)(((uint32_t)(x)) << XRDC_MDA_W6_0_DFMT1_VLD_SHIFT)) & XRDC_MDA_W6_0_DFMT1_VLD_MASK) 687 /*! @} */ 688 689 /*! @name MDA_W7_0_DFMT1 - Master Domain Assignment */ 690 /*! @{ */ 691 692 #define XRDC_MDA_W7_0_DFMT1_DID_MASK (0xFU) 693 #define XRDC_MDA_W7_0_DFMT1_DID_SHIFT (0U) 694 #define XRDC_MDA_W7_0_DFMT1_DID_WIDTH (4U) 695 #define XRDC_MDA_W7_0_DFMT1_DID(x) (((uint32_t)(((uint32_t)(x)) << XRDC_MDA_W7_0_DFMT1_DID_SHIFT)) & XRDC_MDA_W7_0_DFMT1_DID_MASK) 696 697 #define XRDC_MDA_W7_0_DFMT1_PA_MASK (0x30U) 698 #define XRDC_MDA_W7_0_DFMT1_PA_SHIFT (4U) 699 #define XRDC_MDA_W7_0_DFMT1_PA_WIDTH (2U) 700 #define XRDC_MDA_W7_0_DFMT1_PA(x) (((uint32_t)(((uint32_t)(x)) << XRDC_MDA_W7_0_DFMT1_PA_SHIFT)) & XRDC_MDA_W7_0_DFMT1_PA_MASK) 701 702 #define XRDC_MDA_W7_0_DFMT1_SA_MASK (0xC0U) 703 #define XRDC_MDA_W7_0_DFMT1_SA_SHIFT (6U) 704 #define XRDC_MDA_W7_0_DFMT1_SA_WIDTH (2U) 705 #define XRDC_MDA_W7_0_DFMT1_SA(x) (((uint32_t)(((uint32_t)(x)) << XRDC_MDA_W7_0_DFMT1_SA_SHIFT)) & XRDC_MDA_W7_0_DFMT1_SA_MASK) 706 707 #define XRDC_MDA_W7_0_DFMT1_DIDB_MASK (0x100U) 708 #define XRDC_MDA_W7_0_DFMT1_DIDB_SHIFT (8U) 709 #define XRDC_MDA_W7_0_DFMT1_DIDB_WIDTH (1U) 710 #define XRDC_MDA_W7_0_DFMT1_DIDB(x) (((uint32_t)(((uint32_t)(x)) << XRDC_MDA_W7_0_DFMT1_DIDB_SHIFT)) & XRDC_MDA_W7_0_DFMT1_DIDB_MASK) 711 712 #define XRDC_MDA_W7_0_DFMT1_LPID_MASK (0xF000000U) 713 #define XRDC_MDA_W7_0_DFMT1_LPID_SHIFT (24U) 714 #define XRDC_MDA_W7_0_DFMT1_LPID_WIDTH (4U) 715 #define XRDC_MDA_W7_0_DFMT1_LPID(x) (((uint32_t)(((uint32_t)(x)) << XRDC_MDA_W7_0_DFMT1_LPID_SHIFT)) & XRDC_MDA_W7_0_DFMT1_LPID_MASK) 716 717 #define XRDC_MDA_W7_0_DFMT1_LPE_MASK (0x10000000U) 718 #define XRDC_MDA_W7_0_DFMT1_LPE_SHIFT (28U) 719 #define XRDC_MDA_W7_0_DFMT1_LPE_WIDTH (1U) 720 #define XRDC_MDA_W7_0_DFMT1_LPE(x) (((uint32_t)(((uint32_t)(x)) << XRDC_MDA_W7_0_DFMT1_LPE_SHIFT)) & XRDC_MDA_W7_0_DFMT1_LPE_MASK) 721 722 #define XRDC_MDA_W7_0_DFMT1_DFMT_MASK (0x20000000U) 723 #define XRDC_MDA_W7_0_DFMT1_DFMT_SHIFT (29U) 724 #define XRDC_MDA_W7_0_DFMT1_DFMT_WIDTH (1U) 725 #define XRDC_MDA_W7_0_DFMT1_DFMT(x) (((uint32_t)(((uint32_t)(x)) << XRDC_MDA_W7_0_DFMT1_DFMT_SHIFT)) & XRDC_MDA_W7_0_DFMT1_DFMT_MASK) 726 727 #define XRDC_MDA_W7_0_DFMT1_LK1_MASK (0x40000000U) 728 #define XRDC_MDA_W7_0_DFMT1_LK1_SHIFT (30U) 729 #define XRDC_MDA_W7_0_DFMT1_LK1_WIDTH (1U) 730 #define XRDC_MDA_W7_0_DFMT1_LK1(x) (((uint32_t)(((uint32_t)(x)) << XRDC_MDA_W7_0_DFMT1_LK1_SHIFT)) & XRDC_MDA_W7_0_DFMT1_LK1_MASK) 731 732 #define XRDC_MDA_W7_0_DFMT1_VLD_MASK (0x80000000U) 733 #define XRDC_MDA_W7_0_DFMT1_VLD_SHIFT (31U) 734 #define XRDC_MDA_W7_0_DFMT1_VLD_WIDTH (1U) 735 #define XRDC_MDA_W7_0_DFMT1_VLD(x) (((uint32_t)(((uint32_t)(x)) << XRDC_MDA_W7_0_DFMT1_VLD_SHIFT)) & XRDC_MDA_W7_0_DFMT1_VLD_MASK) 736 /*! @} */ 737 738 /*! @name MDA_W0_1_DFMT1 - Master Domain Assignment */ 739 /*! @{ */ 740 741 #define XRDC_MDA_W0_1_DFMT1_DID_MASK (0xFU) 742 #define XRDC_MDA_W0_1_DFMT1_DID_SHIFT (0U) 743 #define XRDC_MDA_W0_1_DFMT1_DID_WIDTH (4U) 744 #define XRDC_MDA_W0_1_DFMT1_DID(x) (((uint32_t)(((uint32_t)(x)) << XRDC_MDA_W0_1_DFMT1_DID_SHIFT)) & XRDC_MDA_W0_1_DFMT1_DID_MASK) 745 746 #define XRDC_MDA_W0_1_DFMT1_PA_MASK (0x30U) 747 #define XRDC_MDA_W0_1_DFMT1_PA_SHIFT (4U) 748 #define XRDC_MDA_W0_1_DFMT1_PA_WIDTH (2U) 749 #define XRDC_MDA_W0_1_DFMT1_PA(x) (((uint32_t)(((uint32_t)(x)) << XRDC_MDA_W0_1_DFMT1_PA_SHIFT)) & XRDC_MDA_W0_1_DFMT1_PA_MASK) 750 751 #define XRDC_MDA_W0_1_DFMT1_SA_MASK (0xC0U) 752 #define XRDC_MDA_W0_1_DFMT1_SA_SHIFT (6U) 753 #define XRDC_MDA_W0_1_DFMT1_SA_WIDTH (2U) 754 #define XRDC_MDA_W0_1_DFMT1_SA(x) (((uint32_t)(((uint32_t)(x)) << XRDC_MDA_W0_1_DFMT1_SA_SHIFT)) & XRDC_MDA_W0_1_DFMT1_SA_MASK) 755 756 #define XRDC_MDA_W0_1_DFMT1_DIDB_MASK (0x100U) 757 #define XRDC_MDA_W0_1_DFMT1_DIDB_SHIFT (8U) 758 #define XRDC_MDA_W0_1_DFMT1_DIDB_WIDTH (1U) 759 #define XRDC_MDA_W0_1_DFMT1_DIDB(x) (((uint32_t)(((uint32_t)(x)) << XRDC_MDA_W0_1_DFMT1_DIDB_SHIFT)) & XRDC_MDA_W0_1_DFMT1_DIDB_MASK) 760 761 #define XRDC_MDA_W0_1_DFMT1_LPID_MASK (0xF000000U) 762 #define XRDC_MDA_W0_1_DFMT1_LPID_SHIFT (24U) 763 #define XRDC_MDA_W0_1_DFMT1_LPID_WIDTH (4U) 764 #define XRDC_MDA_W0_1_DFMT1_LPID(x) (((uint32_t)(((uint32_t)(x)) << XRDC_MDA_W0_1_DFMT1_LPID_SHIFT)) & XRDC_MDA_W0_1_DFMT1_LPID_MASK) 765 766 #define XRDC_MDA_W0_1_DFMT1_LPE_MASK (0x10000000U) 767 #define XRDC_MDA_W0_1_DFMT1_LPE_SHIFT (28U) 768 #define XRDC_MDA_W0_1_DFMT1_LPE_WIDTH (1U) 769 #define XRDC_MDA_W0_1_DFMT1_LPE(x) (((uint32_t)(((uint32_t)(x)) << XRDC_MDA_W0_1_DFMT1_LPE_SHIFT)) & XRDC_MDA_W0_1_DFMT1_LPE_MASK) 770 771 #define XRDC_MDA_W0_1_DFMT1_DFMT_MASK (0x20000000U) 772 #define XRDC_MDA_W0_1_DFMT1_DFMT_SHIFT (29U) 773 #define XRDC_MDA_W0_1_DFMT1_DFMT_WIDTH (1U) 774 #define XRDC_MDA_W0_1_DFMT1_DFMT(x) (((uint32_t)(((uint32_t)(x)) << XRDC_MDA_W0_1_DFMT1_DFMT_SHIFT)) & XRDC_MDA_W0_1_DFMT1_DFMT_MASK) 775 776 #define XRDC_MDA_W0_1_DFMT1_LK1_MASK (0x40000000U) 777 #define XRDC_MDA_W0_1_DFMT1_LK1_SHIFT (30U) 778 #define XRDC_MDA_W0_1_DFMT1_LK1_WIDTH (1U) 779 #define XRDC_MDA_W0_1_DFMT1_LK1(x) (((uint32_t)(((uint32_t)(x)) << XRDC_MDA_W0_1_DFMT1_LK1_SHIFT)) & XRDC_MDA_W0_1_DFMT1_LK1_MASK) 780 781 #define XRDC_MDA_W0_1_DFMT1_VLD_MASK (0x80000000U) 782 #define XRDC_MDA_W0_1_DFMT1_VLD_SHIFT (31U) 783 #define XRDC_MDA_W0_1_DFMT1_VLD_WIDTH (1U) 784 #define XRDC_MDA_W0_1_DFMT1_VLD(x) (((uint32_t)(((uint32_t)(x)) << XRDC_MDA_W0_1_DFMT1_VLD_SHIFT)) & XRDC_MDA_W0_1_DFMT1_VLD_MASK) 785 /*! @} */ 786 787 /*! @name MDA_W1_1_DFMT1 - Master Domain Assignment */ 788 /*! @{ */ 789 790 #define XRDC_MDA_W1_1_DFMT1_DID_MASK (0xFU) 791 #define XRDC_MDA_W1_1_DFMT1_DID_SHIFT (0U) 792 #define XRDC_MDA_W1_1_DFMT1_DID_WIDTH (4U) 793 #define XRDC_MDA_W1_1_DFMT1_DID(x) (((uint32_t)(((uint32_t)(x)) << XRDC_MDA_W1_1_DFMT1_DID_SHIFT)) & XRDC_MDA_W1_1_DFMT1_DID_MASK) 794 795 #define XRDC_MDA_W1_1_DFMT1_PA_MASK (0x30U) 796 #define XRDC_MDA_W1_1_DFMT1_PA_SHIFT (4U) 797 #define XRDC_MDA_W1_1_DFMT1_PA_WIDTH (2U) 798 #define XRDC_MDA_W1_1_DFMT1_PA(x) (((uint32_t)(((uint32_t)(x)) << XRDC_MDA_W1_1_DFMT1_PA_SHIFT)) & XRDC_MDA_W1_1_DFMT1_PA_MASK) 799 800 #define XRDC_MDA_W1_1_DFMT1_SA_MASK (0xC0U) 801 #define XRDC_MDA_W1_1_DFMT1_SA_SHIFT (6U) 802 #define XRDC_MDA_W1_1_DFMT1_SA_WIDTH (2U) 803 #define XRDC_MDA_W1_1_DFMT1_SA(x) (((uint32_t)(((uint32_t)(x)) << XRDC_MDA_W1_1_DFMT1_SA_SHIFT)) & XRDC_MDA_W1_1_DFMT1_SA_MASK) 804 805 #define XRDC_MDA_W1_1_DFMT1_DIDB_MASK (0x100U) 806 #define XRDC_MDA_W1_1_DFMT1_DIDB_SHIFT (8U) 807 #define XRDC_MDA_W1_1_DFMT1_DIDB_WIDTH (1U) 808 #define XRDC_MDA_W1_1_DFMT1_DIDB(x) (((uint32_t)(((uint32_t)(x)) << XRDC_MDA_W1_1_DFMT1_DIDB_SHIFT)) & XRDC_MDA_W1_1_DFMT1_DIDB_MASK) 809 810 #define XRDC_MDA_W1_1_DFMT1_LPID_MASK (0xF000000U) 811 #define XRDC_MDA_W1_1_DFMT1_LPID_SHIFT (24U) 812 #define XRDC_MDA_W1_1_DFMT1_LPID_WIDTH (4U) 813 #define XRDC_MDA_W1_1_DFMT1_LPID(x) (((uint32_t)(((uint32_t)(x)) << XRDC_MDA_W1_1_DFMT1_LPID_SHIFT)) & XRDC_MDA_W1_1_DFMT1_LPID_MASK) 814 815 #define XRDC_MDA_W1_1_DFMT1_LPE_MASK (0x10000000U) 816 #define XRDC_MDA_W1_1_DFMT1_LPE_SHIFT (28U) 817 #define XRDC_MDA_W1_1_DFMT1_LPE_WIDTH (1U) 818 #define XRDC_MDA_W1_1_DFMT1_LPE(x) (((uint32_t)(((uint32_t)(x)) << XRDC_MDA_W1_1_DFMT1_LPE_SHIFT)) & XRDC_MDA_W1_1_DFMT1_LPE_MASK) 819 820 #define XRDC_MDA_W1_1_DFMT1_DFMT_MASK (0x20000000U) 821 #define XRDC_MDA_W1_1_DFMT1_DFMT_SHIFT (29U) 822 #define XRDC_MDA_W1_1_DFMT1_DFMT_WIDTH (1U) 823 #define XRDC_MDA_W1_1_DFMT1_DFMT(x) (((uint32_t)(((uint32_t)(x)) << XRDC_MDA_W1_1_DFMT1_DFMT_SHIFT)) & XRDC_MDA_W1_1_DFMT1_DFMT_MASK) 824 825 #define XRDC_MDA_W1_1_DFMT1_LK1_MASK (0x40000000U) 826 #define XRDC_MDA_W1_1_DFMT1_LK1_SHIFT (30U) 827 #define XRDC_MDA_W1_1_DFMT1_LK1_WIDTH (1U) 828 #define XRDC_MDA_W1_1_DFMT1_LK1(x) (((uint32_t)(((uint32_t)(x)) << XRDC_MDA_W1_1_DFMT1_LK1_SHIFT)) & XRDC_MDA_W1_1_DFMT1_LK1_MASK) 829 830 #define XRDC_MDA_W1_1_DFMT1_VLD_MASK (0x80000000U) 831 #define XRDC_MDA_W1_1_DFMT1_VLD_SHIFT (31U) 832 #define XRDC_MDA_W1_1_DFMT1_VLD_WIDTH (1U) 833 #define XRDC_MDA_W1_1_DFMT1_VLD(x) (((uint32_t)(((uint32_t)(x)) << XRDC_MDA_W1_1_DFMT1_VLD_SHIFT)) & XRDC_MDA_W1_1_DFMT1_VLD_MASK) 834 /*! @} */ 835 836 /*! @name MDA_W2_1_DFMT1 - Master Domain Assignment */ 837 /*! @{ */ 838 839 #define XRDC_MDA_W2_1_DFMT1_DID_MASK (0xFU) 840 #define XRDC_MDA_W2_1_DFMT1_DID_SHIFT (0U) 841 #define XRDC_MDA_W2_1_DFMT1_DID_WIDTH (4U) 842 #define XRDC_MDA_W2_1_DFMT1_DID(x) (((uint32_t)(((uint32_t)(x)) << XRDC_MDA_W2_1_DFMT1_DID_SHIFT)) & XRDC_MDA_W2_1_DFMT1_DID_MASK) 843 844 #define XRDC_MDA_W2_1_DFMT1_PA_MASK (0x30U) 845 #define XRDC_MDA_W2_1_DFMT1_PA_SHIFT (4U) 846 #define XRDC_MDA_W2_1_DFMT1_PA_WIDTH (2U) 847 #define XRDC_MDA_W2_1_DFMT1_PA(x) (((uint32_t)(((uint32_t)(x)) << XRDC_MDA_W2_1_DFMT1_PA_SHIFT)) & XRDC_MDA_W2_1_DFMT1_PA_MASK) 848 849 #define XRDC_MDA_W2_1_DFMT1_SA_MASK (0xC0U) 850 #define XRDC_MDA_W2_1_DFMT1_SA_SHIFT (6U) 851 #define XRDC_MDA_W2_1_DFMT1_SA_WIDTH (2U) 852 #define XRDC_MDA_W2_1_DFMT1_SA(x) (((uint32_t)(((uint32_t)(x)) << XRDC_MDA_W2_1_DFMT1_SA_SHIFT)) & XRDC_MDA_W2_1_DFMT1_SA_MASK) 853 854 #define XRDC_MDA_W2_1_DFMT1_DIDB_MASK (0x100U) 855 #define XRDC_MDA_W2_1_DFMT1_DIDB_SHIFT (8U) 856 #define XRDC_MDA_W2_1_DFMT1_DIDB_WIDTH (1U) 857 #define XRDC_MDA_W2_1_DFMT1_DIDB(x) (((uint32_t)(((uint32_t)(x)) << XRDC_MDA_W2_1_DFMT1_DIDB_SHIFT)) & XRDC_MDA_W2_1_DFMT1_DIDB_MASK) 858 859 #define XRDC_MDA_W2_1_DFMT1_LPID_MASK (0xF000000U) 860 #define XRDC_MDA_W2_1_DFMT1_LPID_SHIFT (24U) 861 #define XRDC_MDA_W2_1_DFMT1_LPID_WIDTH (4U) 862 #define XRDC_MDA_W2_1_DFMT1_LPID(x) (((uint32_t)(((uint32_t)(x)) << XRDC_MDA_W2_1_DFMT1_LPID_SHIFT)) & XRDC_MDA_W2_1_DFMT1_LPID_MASK) 863 864 #define XRDC_MDA_W2_1_DFMT1_LPE_MASK (0x10000000U) 865 #define XRDC_MDA_W2_1_DFMT1_LPE_SHIFT (28U) 866 #define XRDC_MDA_W2_1_DFMT1_LPE_WIDTH (1U) 867 #define XRDC_MDA_W2_1_DFMT1_LPE(x) (((uint32_t)(((uint32_t)(x)) << XRDC_MDA_W2_1_DFMT1_LPE_SHIFT)) & XRDC_MDA_W2_1_DFMT1_LPE_MASK) 868 869 #define XRDC_MDA_W2_1_DFMT1_DFMT_MASK (0x20000000U) 870 #define XRDC_MDA_W2_1_DFMT1_DFMT_SHIFT (29U) 871 #define XRDC_MDA_W2_1_DFMT1_DFMT_WIDTH (1U) 872 #define XRDC_MDA_W2_1_DFMT1_DFMT(x) (((uint32_t)(((uint32_t)(x)) << XRDC_MDA_W2_1_DFMT1_DFMT_SHIFT)) & XRDC_MDA_W2_1_DFMT1_DFMT_MASK) 873 874 #define XRDC_MDA_W2_1_DFMT1_LK1_MASK (0x40000000U) 875 #define XRDC_MDA_W2_1_DFMT1_LK1_SHIFT (30U) 876 #define XRDC_MDA_W2_1_DFMT1_LK1_WIDTH (1U) 877 #define XRDC_MDA_W2_1_DFMT1_LK1(x) (((uint32_t)(((uint32_t)(x)) << XRDC_MDA_W2_1_DFMT1_LK1_SHIFT)) & XRDC_MDA_W2_1_DFMT1_LK1_MASK) 878 879 #define XRDC_MDA_W2_1_DFMT1_VLD_MASK (0x80000000U) 880 #define XRDC_MDA_W2_1_DFMT1_VLD_SHIFT (31U) 881 #define XRDC_MDA_W2_1_DFMT1_VLD_WIDTH (1U) 882 #define XRDC_MDA_W2_1_DFMT1_VLD(x) (((uint32_t)(((uint32_t)(x)) << XRDC_MDA_W2_1_DFMT1_VLD_SHIFT)) & XRDC_MDA_W2_1_DFMT1_VLD_MASK) 883 /*! @} */ 884 885 /*! @name MDA_W3_1_DFMT1 - Master Domain Assignment */ 886 /*! @{ */ 887 888 #define XRDC_MDA_W3_1_DFMT1_DID_MASK (0xFU) 889 #define XRDC_MDA_W3_1_DFMT1_DID_SHIFT (0U) 890 #define XRDC_MDA_W3_1_DFMT1_DID_WIDTH (4U) 891 #define XRDC_MDA_W3_1_DFMT1_DID(x) (((uint32_t)(((uint32_t)(x)) << XRDC_MDA_W3_1_DFMT1_DID_SHIFT)) & XRDC_MDA_W3_1_DFMT1_DID_MASK) 892 893 #define XRDC_MDA_W3_1_DFMT1_PA_MASK (0x30U) 894 #define XRDC_MDA_W3_1_DFMT1_PA_SHIFT (4U) 895 #define XRDC_MDA_W3_1_DFMT1_PA_WIDTH (2U) 896 #define XRDC_MDA_W3_1_DFMT1_PA(x) (((uint32_t)(((uint32_t)(x)) << XRDC_MDA_W3_1_DFMT1_PA_SHIFT)) & XRDC_MDA_W3_1_DFMT1_PA_MASK) 897 898 #define XRDC_MDA_W3_1_DFMT1_SA_MASK (0xC0U) 899 #define XRDC_MDA_W3_1_DFMT1_SA_SHIFT (6U) 900 #define XRDC_MDA_W3_1_DFMT1_SA_WIDTH (2U) 901 #define XRDC_MDA_W3_1_DFMT1_SA(x) (((uint32_t)(((uint32_t)(x)) << XRDC_MDA_W3_1_DFMT1_SA_SHIFT)) & XRDC_MDA_W3_1_DFMT1_SA_MASK) 902 903 #define XRDC_MDA_W3_1_DFMT1_DIDB_MASK (0x100U) 904 #define XRDC_MDA_W3_1_DFMT1_DIDB_SHIFT (8U) 905 #define XRDC_MDA_W3_1_DFMT1_DIDB_WIDTH (1U) 906 #define XRDC_MDA_W3_1_DFMT1_DIDB(x) (((uint32_t)(((uint32_t)(x)) << XRDC_MDA_W3_1_DFMT1_DIDB_SHIFT)) & XRDC_MDA_W3_1_DFMT1_DIDB_MASK) 907 908 #define XRDC_MDA_W3_1_DFMT1_LPID_MASK (0xF000000U) 909 #define XRDC_MDA_W3_1_DFMT1_LPID_SHIFT (24U) 910 #define XRDC_MDA_W3_1_DFMT1_LPID_WIDTH (4U) 911 #define XRDC_MDA_W3_1_DFMT1_LPID(x) (((uint32_t)(((uint32_t)(x)) << XRDC_MDA_W3_1_DFMT1_LPID_SHIFT)) & XRDC_MDA_W3_1_DFMT1_LPID_MASK) 912 913 #define XRDC_MDA_W3_1_DFMT1_LPE_MASK (0x10000000U) 914 #define XRDC_MDA_W3_1_DFMT1_LPE_SHIFT (28U) 915 #define XRDC_MDA_W3_1_DFMT1_LPE_WIDTH (1U) 916 #define XRDC_MDA_W3_1_DFMT1_LPE(x) (((uint32_t)(((uint32_t)(x)) << XRDC_MDA_W3_1_DFMT1_LPE_SHIFT)) & XRDC_MDA_W3_1_DFMT1_LPE_MASK) 917 918 #define XRDC_MDA_W3_1_DFMT1_DFMT_MASK (0x20000000U) 919 #define XRDC_MDA_W3_1_DFMT1_DFMT_SHIFT (29U) 920 #define XRDC_MDA_W3_1_DFMT1_DFMT_WIDTH (1U) 921 #define XRDC_MDA_W3_1_DFMT1_DFMT(x) (((uint32_t)(((uint32_t)(x)) << XRDC_MDA_W3_1_DFMT1_DFMT_SHIFT)) & XRDC_MDA_W3_1_DFMT1_DFMT_MASK) 922 923 #define XRDC_MDA_W3_1_DFMT1_LK1_MASK (0x40000000U) 924 #define XRDC_MDA_W3_1_DFMT1_LK1_SHIFT (30U) 925 #define XRDC_MDA_W3_1_DFMT1_LK1_WIDTH (1U) 926 #define XRDC_MDA_W3_1_DFMT1_LK1(x) (((uint32_t)(((uint32_t)(x)) << XRDC_MDA_W3_1_DFMT1_LK1_SHIFT)) & XRDC_MDA_W3_1_DFMT1_LK1_MASK) 927 928 #define XRDC_MDA_W3_1_DFMT1_VLD_MASK (0x80000000U) 929 #define XRDC_MDA_W3_1_DFMT1_VLD_SHIFT (31U) 930 #define XRDC_MDA_W3_1_DFMT1_VLD_WIDTH (1U) 931 #define XRDC_MDA_W3_1_DFMT1_VLD(x) (((uint32_t)(((uint32_t)(x)) << XRDC_MDA_W3_1_DFMT1_VLD_SHIFT)) & XRDC_MDA_W3_1_DFMT1_VLD_MASK) 932 /*! @} */ 933 934 /*! @name MDA_W4_1_DFMT1 - Master Domain Assignment */ 935 /*! @{ */ 936 937 #define XRDC_MDA_W4_1_DFMT1_DID_MASK (0xFU) 938 #define XRDC_MDA_W4_1_DFMT1_DID_SHIFT (0U) 939 #define XRDC_MDA_W4_1_DFMT1_DID_WIDTH (4U) 940 #define XRDC_MDA_W4_1_DFMT1_DID(x) (((uint32_t)(((uint32_t)(x)) << XRDC_MDA_W4_1_DFMT1_DID_SHIFT)) & XRDC_MDA_W4_1_DFMT1_DID_MASK) 941 942 #define XRDC_MDA_W4_1_DFMT1_PA_MASK (0x30U) 943 #define XRDC_MDA_W4_1_DFMT1_PA_SHIFT (4U) 944 #define XRDC_MDA_W4_1_DFMT1_PA_WIDTH (2U) 945 #define XRDC_MDA_W4_1_DFMT1_PA(x) (((uint32_t)(((uint32_t)(x)) << XRDC_MDA_W4_1_DFMT1_PA_SHIFT)) & XRDC_MDA_W4_1_DFMT1_PA_MASK) 946 947 #define XRDC_MDA_W4_1_DFMT1_SA_MASK (0xC0U) 948 #define XRDC_MDA_W4_1_DFMT1_SA_SHIFT (6U) 949 #define XRDC_MDA_W4_1_DFMT1_SA_WIDTH (2U) 950 #define XRDC_MDA_W4_1_DFMT1_SA(x) (((uint32_t)(((uint32_t)(x)) << XRDC_MDA_W4_1_DFMT1_SA_SHIFT)) & XRDC_MDA_W4_1_DFMT1_SA_MASK) 951 952 #define XRDC_MDA_W4_1_DFMT1_DIDB_MASK (0x100U) 953 #define XRDC_MDA_W4_1_DFMT1_DIDB_SHIFT (8U) 954 #define XRDC_MDA_W4_1_DFMT1_DIDB_WIDTH (1U) 955 #define XRDC_MDA_W4_1_DFMT1_DIDB(x) (((uint32_t)(((uint32_t)(x)) << XRDC_MDA_W4_1_DFMT1_DIDB_SHIFT)) & XRDC_MDA_W4_1_DFMT1_DIDB_MASK) 956 957 #define XRDC_MDA_W4_1_DFMT1_LPID_MASK (0xF000000U) 958 #define XRDC_MDA_W4_1_DFMT1_LPID_SHIFT (24U) 959 #define XRDC_MDA_W4_1_DFMT1_LPID_WIDTH (4U) 960 #define XRDC_MDA_W4_1_DFMT1_LPID(x) (((uint32_t)(((uint32_t)(x)) << XRDC_MDA_W4_1_DFMT1_LPID_SHIFT)) & XRDC_MDA_W4_1_DFMT1_LPID_MASK) 961 962 #define XRDC_MDA_W4_1_DFMT1_LPE_MASK (0x10000000U) 963 #define XRDC_MDA_W4_1_DFMT1_LPE_SHIFT (28U) 964 #define XRDC_MDA_W4_1_DFMT1_LPE_WIDTH (1U) 965 #define XRDC_MDA_W4_1_DFMT1_LPE(x) (((uint32_t)(((uint32_t)(x)) << XRDC_MDA_W4_1_DFMT1_LPE_SHIFT)) & XRDC_MDA_W4_1_DFMT1_LPE_MASK) 966 967 #define XRDC_MDA_W4_1_DFMT1_DFMT_MASK (0x20000000U) 968 #define XRDC_MDA_W4_1_DFMT1_DFMT_SHIFT (29U) 969 #define XRDC_MDA_W4_1_DFMT1_DFMT_WIDTH (1U) 970 #define XRDC_MDA_W4_1_DFMT1_DFMT(x) (((uint32_t)(((uint32_t)(x)) << XRDC_MDA_W4_1_DFMT1_DFMT_SHIFT)) & XRDC_MDA_W4_1_DFMT1_DFMT_MASK) 971 972 #define XRDC_MDA_W4_1_DFMT1_LK1_MASK (0x40000000U) 973 #define XRDC_MDA_W4_1_DFMT1_LK1_SHIFT (30U) 974 #define XRDC_MDA_W4_1_DFMT1_LK1_WIDTH (1U) 975 #define XRDC_MDA_W4_1_DFMT1_LK1(x) (((uint32_t)(((uint32_t)(x)) << XRDC_MDA_W4_1_DFMT1_LK1_SHIFT)) & XRDC_MDA_W4_1_DFMT1_LK1_MASK) 976 977 #define XRDC_MDA_W4_1_DFMT1_VLD_MASK (0x80000000U) 978 #define XRDC_MDA_W4_1_DFMT1_VLD_SHIFT (31U) 979 #define XRDC_MDA_W4_1_DFMT1_VLD_WIDTH (1U) 980 #define XRDC_MDA_W4_1_DFMT1_VLD(x) (((uint32_t)(((uint32_t)(x)) << XRDC_MDA_W4_1_DFMT1_VLD_SHIFT)) & XRDC_MDA_W4_1_DFMT1_VLD_MASK) 981 /*! @} */ 982 983 /*! @name MDA_W5_1_DFMT1 - Master Domain Assignment */ 984 /*! @{ */ 985 986 #define XRDC_MDA_W5_1_DFMT1_DID_MASK (0xFU) 987 #define XRDC_MDA_W5_1_DFMT1_DID_SHIFT (0U) 988 #define XRDC_MDA_W5_1_DFMT1_DID_WIDTH (4U) 989 #define XRDC_MDA_W5_1_DFMT1_DID(x) (((uint32_t)(((uint32_t)(x)) << XRDC_MDA_W5_1_DFMT1_DID_SHIFT)) & XRDC_MDA_W5_1_DFMT1_DID_MASK) 990 991 #define XRDC_MDA_W5_1_DFMT1_PA_MASK (0x30U) 992 #define XRDC_MDA_W5_1_DFMT1_PA_SHIFT (4U) 993 #define XRDC_MDA_W5_1_DFMT1_PA_WIDTH (2U) 994 #define XRDC_MDA_W5_1_DFMT1_PA(x) (((uint32_t)(((uint32_t)(x)) << XRDC_MDA_W5_1_DFMT1_PA_SHIFT)) & XRDC_MDA_W5_1_DFMT1_PA_MASK) 995 996 #define XRDC_MDA_W5_1_DFMT1_SA_MASK (0xC0U) 997 #define XRDC_MDA_W5_1_DFMT1_SA_SHIFT (6U) 998 #define XRDC_MDA_W5_1_DFMT1_SA_WIDTH (2U) 999 #define XRDC_MDA_W5_1_DFMT1_SA(x) (((uint32_t)(((uint32_t)(x)) << XRDC_MDA_W5_1_DFMT1_SA_SHIFT)) & XRDC_MDA_W5_1_DFMT1_SA_MASK) 1000 1001 #define XRDC_MDA_W5_1_DFMT1_DIDB_MASK (0x100U) 1002 #define XRDC_MDA_W5_1_DFMT1_DIDB_SHIFT (8U) 1003 #define XRDC_MDA_W5_1_DFMT1_DIDB_WIDTH (1U) 1004 #define XRDC_MDA_W5_1_DFMT1_DIDB(x) (((uint32_t)(((uint32_t)(x)) << XRDC_MDA_W5_1_DFMT1_DIDB_SHIFT)) & XRDC_MDA_W5_1_DFMT1_DIDB_MASK) 1005 1006 #define XRDC_MDA_W5_1_DFMT1_LPID_MASK (0xF000000U) 1007 #define XRDC_MDA_W5_1_DFMT1_LPID_SHIFT (24U) 1008 #define XRDC_MDA_W5_1_DFMT1_LPID_WIDTH (4U) 1009 #define XRDC_MDA_W5_1_DFMT1_LPID(x) (((uint32_t)(((uint32_t)(x)) << XRDC_MDA_W5_1_DFMT1_LPID_SHIFT)) & XRDC_MDA_W5_1_DFMT1_LPID_MASK) 1010 1011 #define XRDC_MDA_W5_1_DFMT1_LPE_MASK (0x10000000U) 1012 #define XRDC_MDA_W5_1_DFMT1_LPE_SHIFT (28U) 1013 #define XRDC_MDA_W5_1_DFMT1_LPE_WIDTH (1U) 1014 #define XRDC_MDA_W5_1_DFMT1_LPE(x) (((uint32_t)(((uint32_t)(x)) << XRDC_MDA_W5_1_DFMT1_LPE_SHIFT)) & XRDC_MDA_W5_1_DFMT1_LPE_MASK) 1015 1016 #define XRDC_MDA_W5_1_DFMT1_DFMT_MASK (0x20000000U) 1017 #define XRDC_MDA_W5_1_DFMT1_DFMT_SHIFT (29U) 1018 #define XRDC_MDA_W5_1_DFMT1_DFMT_WIDTH (1U) 1019 #define XRDC_MDA_W5_1_DFMT1_DFMT(x) (((uint32_t)(((uint32_t)(x)) << XRDC_MDA_W5_1_DFMT1_DFMT_SHIFT)) & XRDC_MDA_W5_1_DFMT1_DFMT_MASK) 1020 1021 #define XRDC_MDA_W5_1_DFMT1_LK1_MASK (0x40000000U) 1022 #define XRDC_MDA_W5_1_DFMT1_LK1_SHIFT (30U) 1023 #define XRDC_MDA_W5_1_DFMT1_LK1_WIDTH (1U) 1024 #define XRDC_MDA_W5_1_DFMT1_LK1(x) (((uint32_t)(((uint32_t)(x)) << XRDC_MDA_W5_1_DFMT1_LK1_SHIFT)) & XRDC_MDA_W5_1_DFMT1_LK1_MASK) 1025 1026 #define XRDC_MDA_W5_1_DFMT1_VLD_MASK (0x80000000U) 1027 #define XRDC_MDA_W5_1_DFMT1_VLD_SHIFT (31U) 1028 #define XRDC_MDA_W5_1_DFMT1_VLD_WIDTH (1U) 1029 #define XRDC_MDA_W5_1_DFMT1_VLD(x) (((uint32_t)(((uint32_t)(x)) << XRDC_MDA_W5_1_DFMT1_VLD_SHIFT)) & XRDC_MDA_W5_1_DFMT1_VLD_MASK) 1030 /*! @} */ 1031 1032 /*! @name MDA_W6_1_DFMT1 - Master Domain Assignment */ 1033 /*! @{ */ 1034 1035 #define XRDC_MDA_W6_1_DFMT1_DID_MASK (0xFU) 1036 #define XRDC_MDA_W6_1_DFMT1_DID_SHIFT (0U) 1037 #define XRDC_MDA_W6_1_DFMT1_DID_WIDTH (4U) 1038 #define XRDC_MDA_W6_1_DFMT1_DID(x) (((uint32_t)(((uint32_t)(x)) << XRDC_MDA_W6_1_DFMT1_DID_SHIFT)) & XRDC_MDA_W6_1_DFMT1_DID_MASK) 1039 1040 #define XRDC_MDA_W6_1_DFMT1_PA_MASK (0x30U) 1041 #define XRDC_MDA_W6_1_DFMT1_PA_SHIFT (4U) 1042 #define XRDC_MDA_W6_1_DFMT1_PA_WIDTH (2U) 1043 #define XRDC_MDA_W6_1_DFMT1_PA(x) (((uint32_t)(((uint32_t)(x)) << XRDC_MDA_W6_1_DFMT1_PA_SHIFT)) & XRDC_MDA_W6_1_DFMT1_PA_MASK) 1044 1045 #define XRDC_MDA_W6_1_DFMT1_SA_MASK (0xC0U) 1046 #define XRDC_MDA_W6_1_DFMT1_SA_SHIFT (6U) 1047 #define XRDC_MDA_W6_1_DFMT1_SA_WIDTH (2U) 1048 #define XRDC_MDA_W6_1_DFMT1_SA(x) (((uint32_t)(((uint32_t)(x)) << XRDC_MDA_W6_1_DFMT1_SA_SHIFT)) & XRDC_MDA_W6_1_DFMT1_SA_MASK) 1049 1050 #define XRDC_MDA_W6_1_DFMT1_DIDB_MASK (0x100U) 1051 #define XRDC_MDA_W6_1_DFMT1_DIDB_SHIFT (8U) 1052 #define XRDC_MDA_W6_1_DFMT1_DIDB_WIDTH (1U) 1053 #define XRDC_MDA_W6_1_DFMT1_DIDB(x) (((uint32_t)(((uint32_t)(x)) << XRDC_MDA_W6_1_DFMT1_DIDB_SHIFT)) & XRDC_MDA_W6_1_DFMT1_DIDB_MASK) 1054 1055 #define XRDC_MDA_W6_1_DFMT1_LPID_MASK (0xF000000U) 1056 #define XRDC_MDA_W6_1_DFMT1_LPID_SHIFT (24U) 1057 #define XRDC_MDA_W6_1_DFMT1_LPID_WIDTH (4U) 1058 #define XRDC_MDA_W6_1_DFMT1_LPID(x) (((uint32_t)(((uint32_t)(x)) << XRDC_MDA_W6_1_DFMT1_LPID_SHIFT)) & XRDC_MDA_W6_1_DFMT1_LPID_MASK) 1059 1060 #define XRDC_MDA_W6_1_DFMT1_LPE_MASK (0x10000000U) 1061 #define XRDC_MDA_W6_1_DFMT1_LPE_SHIFT (28U) 1062 #define XRDC_MDA_W6_1_DFMT1_LPE_WIDTH (1U) 1063 #define XRDC_MDA_W6_1_DFMT1_LPE(x) (((uint32_t)(((uint32_t)(x)) << XRDC_MDA_W6_1_DFMT1_LPE_SHIFT)) & XRDC_MDA_W6_1_DFMT1_LPE_MASK) 1064 1065 #define XRDC_MDA_W6_1_DFMT1_DFMT_MASK (0x20000000U) 1066 #define XRDC_MDA_W6_1_DFMT1_DFMT_SHIFT (29U) 1067 #define XRDC_MDA_W6_1_DFMT1_DFMT_WIDTH (1U) 1068 #define XRDC_MDA_W6_1_DFMT1_DFMT(x) (((uint32_t)(((uint32_t)(x)) << XRDC_MDA_W6_1_DFMT1_DFMT_SHIFT)) & XRDC_MDA_W6_1_DFMT1_DFMT_MASK) 1069 1070 #define XRDC_MDA_W6_1_DFMT1_LK1_MASK (0x40000000U) 1071 #define XRDC_MDA_W6_1_DFMT1_LK1_SHIFT (30U) 1072 #define XRDC_MDA_W6_1_DFMT1_LK1_WIDTH (1U) 1073 #define XRDC_MDA_W6_1_DFMT1_LK1(x) (((uint32_t)(((uint32_t)(x)) << XRDC_MDA_W6_1_DFMT1_LK1_SHIFT)) & XRDC_MDA_W6_1_DFMT1_LK1_MASK) 1074 1075 #define XRDC_MDA_W6_1_DFMT1_VLD_MASK (0x80000000U) 1076 #define XRDC_MDA_W6_1_DFMT1_VLD_SHIFT (31U) 1077 #define XRDC_MDA_W6_1_DFMT1_VLD_WIDTH (1U) 1078 #define XRDC_MDA_W6_1_DFMT1_VLD(x) (((uint32_t)(((uint32_t)(x)) << XRDC_MDA_W6_1_DFMT1_VLD_SHIFT)) & XRDC_MDA_W6_1_DFMT1_VLD_MASK) 1079 /*! @} */ 1080 1081 /*! @name MDA_W7_1_DFMT1 - Master Domain Assignment */ 1082 /*! @{ */ 1083 1084 #define XRDC_MDA_W7_1_DFMT1_DID_MASK (0xFU) 1085 #define XRDC_MDA_W7_1_DFMT1_DID_SHIFT (0U) 1086 #define XRDC_MDA_W7_1_DFMT1_DID_WIDTH (4U) 1087 #define XRDC_MDA_W7_1_DFMT1_DID(x) (((uint32_t)(((uint32_t)(x)) << XRDC_MDA_W7_1_DFMT1_DID_SHIFT)) & XRDC_MDA_W7_1_DFMT1_DID_MASK) 1088 1089 #define XRDC_MDA_W7_1_DFMT1_PA_MASK (0x30U) 1090 #define XRDC_MDA_W7_1_DFMT1_PA_SHIFT (4U) 1091 #define XRDC_MDA_W7_1_DFMT1_PA_WIDTH (2U) 1092 #define XRDC_MDA_W7_1_DFMT1_PA(x) (((uint32_t)(((uint32_t)(x)) << XRDC_MDA_W7_1_DFMT1_PA_SHIFT)) & XRDC_MDA_W7_1_DFMT1_PA_MASK) 1093 1094 #define XRDC_MDA_W7_1_DFMT1_SA_MASK (0xC0U) 1095 #define XRDC_MDA_W7_1_DFMT1_SA_SHIFT (6U) 1096 #define XRDC_MDA_W7_1_DFMT1_SA_WIDTH (2U) 1097 #define XRDC_MDA_W7_1_DFMT1_SA(x) (((uint32_t)(((uint32_t)(x)) << XRDC_MDA_W7_1_DFMT1_SA_SHIFT)) & XRDC_MDA_W7_1_DFMT1_SA_MASK) 1098 1099 #define XRDC_MDA_W7_1_DFMT1_DIDB_MASK (0x100U) 1100 #define XRDC_MDA_W7_1_DFMT1_DIDB_SHIFT (8U) 1101 #define XRDC_MDA_W7_1_DFMT1_DIDB_WIDTH (1U) 1102 #define XRDC_MDA_W7_1_DFMT1_DIDB(x) (((uint32_t)(((uint32_t)(x)) << XRDC_MDA_W7_1_DFMT1_DIDB_SHIFT)) & XRDC_MDA_W7_1_DFMT1_DIDB_MASK) 1103 1104 #define XRDC_MDA_W7_1_DFMT1_LPID_MASK (0xF000000U) 1105 #define XRDC_MDA_W7_1_DFMT1_LPID_SHIFT (24U) 1106 #define XRDC_MDA_W7_1_DFMT1_LPID_WIDTH (4U) 1107 #define XRDC_MDA_W7_1_DFMT1_LPID(x) (((uint32_t)(((uint32_t)(x)) << XRDC_MDA_W7_1_DFMT1_LPID_SHIFT)) & XRDC_MDA_W7_1_DFMT1_LPID_MASK) 1108 1109 #define XRDC_MDA_W7_1_DFMT1_LPE_MASK (0x10000000U) 1110 #define XRDC_MDA_W7_1_DFMT1_LPE_SHIFT (28U) 1111 #define XRDC_MDA_W7_1_DFMT1_LPE_WIDTH (1U) 1112 #define XRDC_MDA_W7_1_DFMT1_LPE(x) (((uint32_t)(((uint32_t)(x)) << XRDC_MDA_W7_1_DFMT1_LPE_SHIFT)) & XRDC_MDA_W7_1_DFMT1_LPE_MASK) 1113 1114 #define XRDC_MDA_W7_1_DFMT1_DFMT_MASK (0x20000000U) 1115 #define XRDC_MDA_W7_1_DFMT1_DFMT_SHIFT (29U) 1116 #define XRDC_MDA_W7_1_DFMT1_DFMT_WIDTH (1U) 1117 #define XRDC_MDA_W7_1_DFMT1_DFMT(x) (((uint32_t)(((uint32_t)(x)) << XRDC_MDA_W7_1_DFMT1_DFMT_SHIFT)) & XRDC_MDA_W7_1_DFMT1_DFMT_MASK) 1118 1119 #define XRDC_MDA_W7_1_DFMT1_LK1_MASK (0x40000000U) 1120 #define XRDC_MDA_W7_1_DFMT1_LK1_SHIFT (30U) 1121 #define XRDC_MDA_W7_1_DFMT1_LK1_WIDTH (1U) 1122 #define XRDC_MDA_W7_1_DFMT1_LK1(x) (((uint32_t)(((uint32_t)(x)) << XRDC_MDA_W7_1_DFMT1_LK1_SHIFT)) & XRDC_MDA_W7_1_DFMT1_LK1_MASK) 1123 1124 #define XRDC_MDA_W7_1_DFMT1_VLD_MASK (0x80000000U) 1125 #define XRDC_MDA_W7_1_DFMT1_VLD_SHIFT (31U) 1126 #define XRDC_MDA_W7_1_DFMT1_VLD_WIDTH (1U) 1127 #define XRDC_MDA_W7_1_DFMT1_VLD(x) (((uint32_t)(((uint32_t)(x)) << XRDC_MDA_W7_1_DFMT1_VLD_SHIFT)) & XRDC_MDA_W7_1_DFMT1_VLD_MASK) 1128 /*! @} */ 1129 1130 /*! @name MDA_W0_2_DFMT1 - Master Domain Assignment */ 1131 /*! @{ */ 1132 1133 #define XRDC_MDA_W0_2_DFMT1_DID_MASK (0xFU) 1134 #define XRDC_MDA_W0_2_DFMT1_DID_SHIFT (0U) 1135 #define XRDC_MDA_W0_2_DFMT1_DID_WIDTH (4U) 1136 #define XRDC_MDA_W0_2_DFMT1_DID(x) (((uint32_t)(((uint32_t)(x)) << XRDC_MDA_W0_2_DFMT1_DID_SHIFT)) & XRDC_MDA_W0_2_DFMT1_DID_MASK) 1137 1138 #define XRDC_MDA_W0_2_DFMT1_PA_MASK (0x30U) 1139 #define XRDC_MDA_W0_2_DFMT1_PA_SHIFT (4U) 1140 #define XRDC_MDA_W0_2_DFMT1_PA_WIDTH (2U) 1141 #define XRDC_MDA_W0_2_DFMT1_PA(x) (((uint32_t)(((uint32_t)(x)) << XRDC_MDA_W0_2_DFMT1_PA_SHIFT)) & XRDC_MDA_W0_2_DFMT1_PA_MASK) 1142 1143 #define XRDC_MDA_W0_2_DFMT1_SA_MASK (0xC0U) 1144 #define XRDC_MDA_W0_2_DFMT1_SA_SHIFT (6U) 1145 #define XRDC_MDA_W0_2_DFMT1_SA_WIDTH (2U) 1146 #define XRDC_MDA_W0_2_DFMT1_SA(x) (((uint32_t)(((uint32_t)(x)) << XRDC_MDA_W0_2_DFMT1_SA_SHIFT)) & XRDC_MDA_W0_2_DFMT1_SA_MASK) 1147 1148 #define XRDC_MDA_W0_2_DFMT1_DIDB_MASK (0x100U) 1149 #define XRDC_MDA_W0_2_DFMT1_DIDB_SHIFT (8U) 1150 #define XRDC_MDA_W0_2_DFMT1_DIDB_WIDTH (1U) 1151 #define XRDC_MDA_W0_2_DFMT1_DIDB(x) (((uint32_t)(((uint32_t)(x)) << XRDC_MDA_W0_2_DFMT1_DIDB_SHIFT)) & XRDC_MDA_W0_2_DFMT1_DIDB_MASK) 1152 1153 #define XRDC_MDA_W0_2_DFMT1_LPID_MASK (0xF000000U) 1154 #define XRDC_MDA_W0_2_DFMT1_LPID_SHIFT (24U) 1155 #define XRDC_MDA_W0_2_DFMT1_LPID_WIDTH (4U) 1156 #define XRDC_MDA_W0_2_DFMT1_LPID(x) (((uint32_t)(((uint32_t)(x)) << XRDC_MDA_W0_2_DFMT1_LPID_SHIFT)) & XRDC_MDA_W0_2_DFMT1_LPID_MASK) 1157 1158 #define XRDC_MDA_W0_2_DFMT1_LPE_MASK (0x10000000U) 1159 #define XRDC_MDA_W0_2_DFMT1_LPE_SHIFT (28U) 1160 #define XRDC_MDA_W0_2_DFMT1_LPE_WIDTH (1U) 1161 #define XRDC_MDA_W0_2_DFMT1_LPE(x) (((uint32_t)(((uint32_t)(x)) << XRDC_MDA_W0_2_DFMT1_LPE_SHIFT)) & XRDC_MDA_W0_2_DFMT1_LPE_MASK) 1162 1163 #define XRDC_MDA_W0_2_DFMT1_DFMT_MASK (0x20000000U) 1164 #define XRDC_MDA_W0_2_DFMT1_DFMT_SHIFT (29U) 1165 #define XRDC_MDA_W0_2_DFMT1_DFMT_WIDTH (1U) 1166 #define XRDC_MDA_W0_2_DFMT1_DFMT(x) (((uint32_t)(((uint32_t)(x)) << XRDC_MDA_W0_2_DFMT1_DFMT_SHIFT)) & XRDC_MDA_W0_2_DFMT1_DFMT_MASK) 1167 1168 #define XRDC_MDA_W0_2_DFMT1_LK1_MASK (0x40000000U) 1169 #define XRDC_MDA_W0_2_DFMT1_LK1_SHIFT (30U) 1170 #define XRDC_MDA_W0_2_DFMT1_LK1_WIDTH (1U) 1171 #define XRDC_MDA_W0_2_DFMT1_LK1(x) (((uint32_t)(((uint32_t)(x)) << XRDC_MDA_W0_2_DFMT1_LK1_SHIFT)) & XRDC_MDA_W0_2_DFMT1_LK1_MASK) 1172 1173 #define XRDC_MDA_W0_2_DFMT1_VLD_MASK (0x80000000U) 1174 #define XRDC_MDA_W0_2_DFMT1_VLD_SHIFT (31U) 1175 #define XRDC_MDA_W0_2_DFMT1_VLD_WIDTH (1U) 1176 #define XRDC_MDA_W0_2_DFMT1_VLD(x) (((uint32_t)(((uint32_t)(x)) << XRDC_MDA_W0_2_DFMT1_VLD_SHIFT)) & XRDC_MDA_W0_2_DFMT1_VLD_MASK) 1177 /*! @} */ 1178 1179 /*! @name MDA_W1_2_DFMT1 - Master Domain Assignment */ 1180 /*! @{ */ 1181 1182 #define XRDC_MDA_W1_2_DFMT1_DID_MASK (0xFU) 1183 #define XRDC_MDA_W1_2_DFMT1_DID_SHIFT (0U) 1184 #define XRDC_MDA_W1_2_DFMT1_DID_WIDTH (4U) 1185 #define XRDC_MDA_W1_2_DFMT1_DID(x) (((uint32_t)(((uint32_t)(x)) << XRDC_MDA_W1_2_DFMT1_DID_SHIFT)) & XRDC_MDA_W1_2_DFMT1_DID_MASK) 1186 1187 #define XRDC_MDA_W1_2_DFMT1_PA_MASK (0x30U) 1188 #define XRDC_MDA_W1_2_DFMT1_PA_SHIFT (4U) 1189 #define XRDC_MDA_W1_2_DFMT1_PA_WIDTH (2U) 1190 #define XRDC_MDA_W1_2_DFMT1_PA(x) (((uint32_t)(((uint32_t)(x)) << XRDC_MDA_W1_2_DFMT1_PA_SHIFT)) & XRDC_MDA_W1_2_DFMT1_PA_MASK) 1191 1192 #define XRDC_MDA_W1_2_DFMT1_SA_MASK (0xC0U) 1193 #define XRDC_MDA_W1_2_DFMT1_SA_SHIFT (6U) 1194 #define XRDC_MDA_W1_2_DFMT1_SA_WIDTH (2U) 1195 #define XRDC_MDA_W1_2_DFMT1_SA(x) (((uint32_t)(((uint32_t)(x)) << XRDC_MDA_W1_2_DFMT1_SA_SHIFT)) & XRDC_MDA_W1_2_DFMT1_SA_MASK) 1196 1197 #define XRDC_MDA_W1_2_DFMT1_DIDB_MASK (0x100U) 1198 #define XRDC_MDA_W1_2_DFMT1_DIDB_SHIFT (8U) 1199 #define XRDC_MDA_W1_2_DFMT1_DIDB_WIDTH (1U) 1200 #define XRDC_MDA_W1_2_DFMT1_DIDB(x) (((uint32_t)(((uint32_t)(x)) << XRDC_MDA_W1_2_DFMT1_DIDB_SHIFT)) & XRDC_MDA_W1_2_DFMT1_DIDB_MASK) 1201 1202 #define XRDC_MDA_W1_2_DFMT1_LPID_MASK (0xF000000U) 1203 #define XRDC_MDA_W1_2_DFMT1_LPID_SHIFT (24U) 1204 #define XRDC_MDA_W1_2_DFMT1_LPID_WIDTH (4U) 1205 #define XRDC_MDA_W1_2_DFMT1_LPID(x) (((uint32_t)(((uint32_t)(x)) << XRDC_MDA_W1_2_DFMT1_LPID_SHIFT)) & XRDC_MDA_W1_2_DFMT1_LPID_MASK) 1206 1207 #define XRDC_MDA_W1_2_DFMT1_LPE_MASK (0x10000000U) 1208 #define XRDC_MDA_W1_2_DFMT1_LPE_SHIFT (28U) 1209 #define XRDC_MDA_W1_2_DFMT1_LPE_WIDTH (1U) 1210 #define XRDC_MDA_W1_2_DFMT1_LPE(x) (((uint32_t)(((uint32_t)(x)) << XRDC_MDA_W1_2_DFMT1_LPE_SHIFT)) & XRDC_MDA_W1_2_DFMT1_LPE_MASK) 1211 1212 #define XRDC_MDA_W1_2_DFMT1_DFMT_MASK (0x20000000U) 1213 #define XRDC_MDA_W1_2_DFMT1_DFMT_SHIFT (29U) 1214 #define XRDC_MDA_W1_2_DFMT1_DFMT_WIDTH (1U) 1215 #define XRDC_MDA_W1_2_DFMT1_DFMT(x) (((uint32_t)(((uint32_t)(x)) << XRDC_MDA_W1_2_DFMT1_DFMT_SHIFT)) & XRDC_MDA_W1_2_DFMT1_DFMT_MASK) 1216 1217 #define XRDC_MDA_W1_2_DFMT1_LK1_MASK (0x40000000U) 1218 #define XRDC_MDA_W1_2_DFMT1_LK1_SHIFT (30U) 1219 #define XRDC_MDA_W1_2_DFMT1_LK1_WIDTH (1U) 1220 #define XRDC_MDA_W1_2_DFMT1_LK1(x) (((uint32_t)(((uint32_t)(x)) << XRDC_MDA_W1_2_DFMT1_LK1_SHIFT)) & XRDC_MDA_W1_2_DFMT1_LK1_MASK) 1221 1222 #define XRDC_MDA_W1_2_DFMT1_VLD_MASK (0x80000000U) 1223 #define XRDC_MDA_W1_2_DFMT1_VLD_SHIFT (31U) 1224 #define XRDC_MDA_W1_2_DFMT1_VLD_WIDTH (1U) 1225 #define XRDC_MDA_W1_2_DFMT1_VLD(x) (((uint32_t)(((uint32_t)(x)) << XRDC_MDA_W1_2_DFMT1_VLD_SHIFT)) & XRDC_MDA_W1_2_DFMT1_VLD_MASK) 1226 /*! @} */ 1227 1228 /*! @name MDA_W2_2_DFMT1 - Master Domain Assignment */ 1229 /*! @{ */ 1230 1231 #define XRDC_MDA_W2_2_DFMT1_DID_MASK (0xFU) 1232 #define XRDC_MDA_W2_2_DFMT1_DID_SHIFT (0U) 1233 #define XRDC_MDA_W2_2_DFMT1_DID_WIDTH (4U) 1234 #define XRDC_MDA_W2_2_DFMT1_DID(x) (((uint32_t)(((uint32_t)(x)) << XRDC_MDA_W2_2_DFMT1_DID_SHIFT)) & XRDC_MDA_W2_2_DFMT1_DID_MASK) 1235 1236 #define XRDC_MDA_W2_2_DFMT1_PA_MASK (0x30U) 1237 #define XRDC_MDA_W2_2_DFMT1_PA_SHIFT (4U) 1238 #define XRDC_MDA_W2_2_DFMT1_PA_WIDTH (2U) 1239 #define XRDC_MDA_W2_2_DFMT1_PA(x) (((uint32_t)(((uint32_t)(x)) << XRDC_MDA_W2_2_DFMT1_PA_SHIFT)) & XRDC_MDA_W2_2_DFMT1_PA_MASK) 1240 1241 #define XRDC_MDA_W2_2_DFMT1_SA_MASK (0xC0U) 1242 #define XRDC_MDA_W2_2_DFMT1_SA_SHIFT (6U) 1243 #define XRDC_MDA_W2_2_DFMT1_SA_WIDTH (2U) 1244 #define XRDC_MDA_W2_2_DFMT1_SA(x) (((uint32_t)(((uint32_t)(x)) << XRDC_MDA_W2_2_DFMT1_SA_SHIFT)) & XRDC_MDA_W2_2_DFMT1_SA_MASK) 1245 1246 #define XRDC_MDA_W2_2_DFMT1_DIDB_MASK (0x100U) 1247 #define XRDC_MDA_W2_2_DFMT1_DIDB_SHIFT (8U) 1248 #define XRDC_MDA_W2_2_DFMT1_DIDB_WIDTH (1U) 1249 #define XRDC_MDA_W2_2_DFMT1_DIDB(x) (((uint32_t)(((uint32_t)(x)) << XRDC_MDA_W2_2_DFMT1_DIDB_SHIFT)) & XRDC_MDA_W2_2_DFMT1_DIDB_MASK) 1250 1251 #define XRDC_MDA_W2_2_DFMT1_LPID_MASK (0xF000000U) 1252 #define XRDC_MDA_W2_2_DFMT1_LPID_SHIFT (24U) 1253 #define XRDC_MDA_W2_2_DFMT1_LPID_WIDTH (4U) 1254 #define XRDC_MDA_W2_2_DFMT1_LPID(x) (((uint32_t)(((uint32_t)(x)) << XRDC_MDA_W2_2_DFMT1_LPID_SHIFT)) & XRDC_MDA_W2_2_DFMT1_LPID_MASK) 1255 1256 #define XRDC_MDA_W2_2_DFMT1_LPE_MASK (0x10000000U) 1257 #define XRDC_MDA_W2_2_DFMT1_LPE_SHIFT (28U) 1258 #define XRDC_MDA_W2_2_DFMT1_LPE_WIDTH (1U) 1259 #define XRDC_MDA_W2_2_DFMT1_LPE(x) (((uint32_t)(((uint32_t)(x)) << XRDC_MDA_W2_2_DFMT1_LPE_SHIFT)) & XRDC_MDA_W2_2_DFMT1_LPE_MASK) 1260 1261 #define XRDC_MDA_W2_2_DFMT1_DFMT_MASK (0x20000000U) 1262 #define XRDC_MDA_W2_2_DFMT1_DFMT_SHIFT (29U) 1263 #define XRDC_MDA_W2_2_DFMT1_DFMT_WIDTH (1U) 1264 #define XRDC_MDA_W2_2_DFMT1_DFMT(x) (((uint32_t)(((uint32_t)(x)) << XRDC_MDA_W2_2_DFMT1_DFMT_SHIFT)) & XRDC_MDA_W2_2_DFMT1_DFMT_MASK) 1265 1266 #define XRDC_MDA_W2_2_DFMT1_LK1_MASK (0x40000000U) 1267 #define XRDC_MDA_W2_2_DFMT1_LK1_SHIFT (30U) 1268 #define XRDC_MDA_W2_2_DFMT1_LK1_WIDTH (1U) 1269 #define XRDC_MDA_W2_2_DFMT1_LK1(x) (((uint32_t)(((uint32_t)(x)) << XRDC_MDA_W2_2_DFMT1_LK1_SHIFT)) & XRDC_MDA_W2_2_DFMT1_LK1_MASK) 1270 1271 #define XRDC_MDA_W2_2_DFMT1_VLD_MASK (0x80000000U) 1272 #define XRDC_MDA_W2_2_DFMT1_VLD_SHIFT (31U) 1273 #define XRDC_MDA_W2_2_DFMT1_VLD_WIDTH (1U) 1274 #define XRDC_MDA_W2_2_DFMT1_VLD(x) (((uint32_t)(((uint32_t)(x)) << XRDC_MDA_W2_2_DFMT1_VLD_SHIFT)) & XRDC_MDA_W2_2_DFMT1_VLD_MASK) 1275 /*! @} */ 1276 1277 /*! @name MDA_W3_2_DFMT1 - Master Domain Assignment */ 1278 /*! @{ */ 1279 1280 #define XRDC_MDA_W3_2_DFMT1_DID_MASK (0xFU) 1281 #define XRDC_MDA_W3_2_DFMT1_DID_SHIFT (0U) 1282 #define XRDC_MDA_W3_2_DFMT1_DID_WIDTH (4U) 1283 #define XRDC_MDA_W3_2_DFMT1_DID(x) (((uint32_t)(((uint32_t)(x)) << XRDC_MDA_W3_2_DFMT1_DID_SHIFT)) & XRDC_MDA_W3_2_DFMT1_DID_MASK) 1284 1285 #define XRDC_MDA_W3_2_DFMT1_PA_MASK (0x30U) 1286 #define XRDC_MDA_W3_2_DFMT1_PA_SHIFT (4U) 1287 #define XRDC_MDA_W3_2_DFMT1_PA_WIDTH (2U) 1288 #define XRDC_MDA_W3_2_DFMT1_PA(x) (((uint32_t)(((uint32_t)(x)) << XRDC_MDA_W3_2_DFMT1_PA_SHIFT)) & XRDC_MDA_W3_2_DFMT1_PA_MASK) 1289 1290 #define XRDC_MDA_W3_2_DFMT1_SA_MASK (0xC0U) 1291 #define XRDC_MDA_W3_2_DFMT1_SA_SHIFT (6U) 1292 #define XRDC_MDA_W3_2_DFMT1_SA_WIDTH (2U) 1293 #define XRDC_MDA_W3_2_DFMT1_SA(x) (((uint32_t)(((uint32_t)(x)) << XRDC_MDA_W3_2_DFMT1_SA_SHIFT)) & XRDC_MDA_W3_2_DFMT1_SA_MASK) 1294 1295 #define XRDC_MDA_W3_2_DFMT1_DIDB_MASK (0x100U) 1296 #define XRDC_MDA_W3_2_DFMT1_DIDB_SHIFT (8U) 1297 #define XRDC_MDA_W3_2_DFMT1_DIDB_WIDTH (1U) 1298 #define XRDC_MDA_W3_2_DFMT1_DIDB(x) (((uint32_t)(((uint32_t)(x)) << XRDC_MDA_W3_2_DFMT1_DIDB_SHIFT)) & XRDC_MDA_W3_2_DFMT1_DIDB_MASK) 1299 1300 #define XRDC_MDA_W3_2_DFMT1_LPID_MASK (0xF000000U) 1301 #define XRDC_MDA_W3_2_DFMT1_LPID_SHIFT (24U) 1302 #define XRDC_MDA_W3_2_DFMT1_LPID_WIDTH (4U) 1303 #define XRDC_MDA_W3_2_DFMT1_LPID(x) (((uint32_t)(((uint32_t)(x)) << XRDC_MDA_W3_2_DFMT1_LPID_SHIFT)) & XRDC_MDA_W3_2_DFMT1_LPID_MASK) 1304 1305 #define XRDC_MDA_W3_2_DFMT1_LPE_MASK (0x10000000U) 1306 #define XRDC_MDA_W3_2_DFMT1_LPE_SHIFT (28U) 1307 #define XRDC_MDA_W3_2_DFMT1_LPE_WIDTH (1U) 1308 #define XRDC_MDA_W3_2_DFMT1_LPE(x) (((uint32_t)(((uint32_t)(x)) << XRDC_MDA_W3_2_DFMT1_LPE_SHIFT)) & XRDC_MDA_W3_2_DFMT1_LPE_MASK) 1309 1310 #define XRDC_MDA_W3_2_DFMT1_DFMT_MASK (0x20000000U) 1311 #define XRDC_MDA_W3_2_DFMT1_DFMT_SHIFT (29U) 1312 #define XRDC_MDA_W3_2_DFMT1_DFMT_WIDTH (1U) 1313 #define XRDC_MDA_W3_2_DFMT1_DFMT(x) (((uint32_t)(((uint32_t)(x)) << XRDC_MDA_W3_2_DFMT1_DFMT_SHIFT)) & XRDC_MDA_W3_2_DFMT1_DFMT_MASK) 1314 1315 #define XRDC_MDA_W3_2_DFMT1_LK1_MASK (0x40000000U) 1316 #define XRDC_MDA_W3_2_DFMT1_LK1_SHIFT (30U) 1317 #define XRDC_MDA_W3_2_DFMT1_LK1_WIDTH (1U) 1318 #define XRDC_MDA_W3_2_DFMT1_LK1(x) (((uint32_t)(((uint32_t)(x)) << XRDC_MDA_W3_2_DFMT1_LK1_SHIFT)) & XRDC_MDA_W3_2_DFMT1_LK1_MASK) 1319 1320 #define XRDC_MDA_W3_2_DFMT1_VLD_MASK (0x80000000U) 1321 #define XRDC_MDA_W3_2_DFMT1_VLD_SHIFT (31U) 1322 #define XRDC_MDA_W3_2_DFMT1_VLD_WIDTH (1U) 1323 #define XRDC_MDA_W3_2_DFMT1_VLD(x) (((uint32_t)(((uint32_t)(x)) << XRDC_MDA_W3_2_DFMT1_VLD_SHIFT)) & XRDC_MDA_W3_2_DFMT1_VLD_MASK) 1324 /*! @} */ 1325 1326 /*! @name MDA_W4_2_DFMT1 - Master Domain Assignment */ 1327 /*! @{ */ 1328 1329 #define XRDC_MDA_W4_2_DFMT1_DID_MASK (0xFU) 1330 #define XRDC_MDA_W4_2_DFMT1_DID_SHIFT (0U) 1331 #define XRDC_MDA_W4_2_DFMT1_DID_WIDTH (4U) 1332 #define XRDC_MDA_W4_2_DFMT1_DID(x) (((uint32_t)(((uint32_t)(x)) << XRDC_MDA_W4_2_DFMT1_DID_SHIFT)) & XRDC_MDA_W4_2_DFMT1_DID_MASK) 1333 1334 #define XRDC_MDA_W4_2_DFMT1_PA_MASK (0x30U) 1335 #define XRDC_MDA_W4_2_DFMT1_PA_SHIFT (4U) 1336 #define XRDC_MDA_W4_2_DFMT1_PA_WIDTH (2U) 1337 #define XRDC_MDA_W4_2_DFMT1_PA(x) (((uint32_t)(((uint32_t)(x)) << XRDC_MDA_W4_2_DFMT1_PA_SHIFT)) & XRDC_MDA_W4_2_DFMT1_PA_MASK) 1338 1339 #define XRDC_MDA_W4_2_DFMT1_SA_MASK (0xC0U) 1340 #define XRDC_MDA_W4_2_DFMT1_SA_SHIFT (6U) 1341 #define XRDC_MDA_W4_2_DFMT1_SA_WIDTH (2U) 1342 #define XRDC_MDA_W4_2_DFMT1_SA(x) (((uint32_t)(((uint32_t)(x)) << XRDC_MDA_W4_2_DFMT1_SA_SHIFT)) & XRDC_MDA_W4_2_DFMT1_SA_MASK) 1343 1344 #define XRDC_MDA_W4_2_DFMT1_DIDB_MASK (0x100U) 1345 #define XRDC_MDA_W4_2_DFMT1_DIDB_SHIFT (8U) 1346 #define XRDC_MDA_W4_2_DFMT1_DIDB_WIDTH (1U) 1347 #define XRDC_MDA_W4_2_DFMT1_DIDB(x) (((uint32_t)(((uint32_t)(x)) << XRDC_MDA_W4_2_DFMT1_DIDB_SHIFT)) & XRDC_MDA_W4_2_DFMT1_DIDB_MASK) 1348 1349 #define XRDC_MDA_W4_2_DFMT1_LPID_MASK (0xF000000U) 1350 #define XRDC_MDA_W4_2_DFMT1_LPID_SHIFT (24U) 1351 #define XRDC_MDA_W4_2_DFMT1_LPID_WIDTH (4U) 1352 #define XRDC_MDA_W4_2_DFMT1_LPID(x) (((uint32_t)(((uint32_t)(x)) << XRDC_MDA_W4_2_DFMT1_LPID_SHIFT)) & XRDC_MDA_W4_2_DFMT1_LPID_MASK) 1353 1354 #define XRDC_MDA_W4_2_DFMT1_LPE_MASK (0x10000000U) 1355 #define XRDC_MDA_W4_2_DFMT1_LPE_SHIFT (28U) 1356 #define XRDC_MDA_W4_2_DFMT1_LPE_WIDTH (1U) 1357 #define XRDC_MDA_W4_2_DFMT1_LPE(x) (((uint32_t)(((uint32_t)(x)) << XRDC_MDA_W4_2_DFMT1_LPE_SHIFT)) & XRDC_MDA_W4_2_DFMT1_LPE_MASK) 1358 1359 #define XRDC_MDA_W4_2_DFMT1_DFMT_MASK (0x20000000U) 1360 #define XRDC_MDA_W4_2_DFMT1_DFMT_SHIFT (29U) 1361 #define XRDC_MDA_W4_2_DFMT1_DFMT_WIDTH (1U) 1362 #define XRDC_MDA_W4_2_DFMT1_DFMT(x) (((uint32_t)(((uint32_t)(x)) << XRDC_MDA_W4_2_DFMT1_DFMT_SHIFT)) & XRDC_MDA_W4_2_DFMT1_DFMT_MASK) 1363 1364 #define XRDC_MDA_W4_2_DFMT1_LK1_MASK (0x40000000U) 1365 #define XRDC_MDA_W4_2_DFMT1_LK1_SHIFT (30U) 1366 #define XRDC_MDA_W4_2_DFMT1_LK1_WIDTH (1U) 1367 #define XRDC_MDA_W4_2_DFMT1_LK1(x) (((uint32_t)(((uint32_t)(x)) << XRDC_MDA_W4_2_DFMT1_LK1_SHIFT)) & XRDC_MDA_W4_2_DFMT1_LK1_MASK) 1368 1369 #define XRDC_MDA_W4_2_DFMT1_VLD_MASK (0x80000000U) 1370 #define XRDC_MDA_W4_2_DFMT1_VLD_SHIFT (31U) 1371 #define XRDC_MDA_W4_2_DFMT1_VLD_WIDTH (1U) 1372 #define XRDC_MDA_W4_2_DFMT1_VLD(x) (((uint32_t)(((uint32_t)(x)) << XRDC_MDA_W4_2_DFMT1_VLD_SHIFT)) & XRDC_MDA_W4_2_DFMT1_VLD_MASK) 1373 /*! @} */ 1374 1375 /*! @name MDA_W5_2_DFMT1 - Master Domain Assignment */ 1376 /*! @{ */ 1377 1378 #define XRDC_MDA_W5_2_DFMT1_DID_MASK (0xFU) 1379 #define XRDC_MDA_W5_2_DFMT1_DID_SHIFT (0U) 1380 #define XRDC_MDA_W5_2_DFMT1_DID_WIDTH (4U) 1381 #define XRDC_MDA_W5_2_DFMT1_DID(x) (((uint32_t)(((uint32_t)(x)) << XRDC_MDA_W5_2_DFMT1_DID_SHIFT)) & XRDC_MDA_W5_2_DFMT1_DID_MASK) 1382 1383 #define XRDC_MDA_W5_2_DFMT1_PA_MASK (0x30U) 1384 #define XRDC_MDA_W5_2_DFMT1_PA_SHIFT (4U) 1385 #define XRDC_MDA_W5_2_DFMT1_PA_WIDTH (2U) 1386 #define XRDC_MDA_W5_2_DFMT1_PA(x) (((uint32_t)(((uint32_t)(x)) << XRDC_MDA_W5_2_DFMT1_PA_SHIFT)) & XRDC_MDA_W5_2_DFMT1_PA_MASK) 1387 1388 #define XRDC_MDA_W5_2_DFMT1_SA_MASK (0xC0U) 1389 #define XRDC_MDA_W5_2_DFMT1_SA_SHIFT (6U) 1390 #define XRDC_MDA_W5_2_DFMT1_SA_WIDTH (2U) 1391 #define XRDC_MDA_W5_2_DFMT1_SA(x) (((uint32_t)(((uint32_t)(x)) << XRDC_MDA_W5_2_DFMT1_SA_SHIFT)) & XRDC_MDA_W5_2_DFMT1_SA_MASK) 1392 1393 #define XRDC_MDA_W5_2_DFMT1_DIDB_MASK (0x100U) 1394 #define XRDC_MDA_W5_2_DFMT1_DIDB_SHIFT (8U) 1395 #define XRDC_MDA_W5_2_DFMT1_DIDB_WIDTH (1U) 1396 #define XRDC_MDA_W5_2_DFMT1_DIDB(x) (((uint32_t)(((uint32_t)(x)) << XRDC_MDA_W5_2_DFMT1_DIDB_SHIFT)) & XRDC_MDA_W5_2_DFMT1_DIDB_MASK) 1397 1398 #define XRDC_MDA_W5_2_DFMT1_LPID_MASK (0xF000000U) 1399 #define XRDC_MDA_W5_2_DFMT1_LPID_SHIFT (24U) 1400 #define XRDC_MDA_W5_2_DFMT1_LPID_WIDTH (4U) 1401 #define XRDC_MDA_W5_2_DFMT1_LPID(x) (((uint32_t)(((uint32_t)(x)) << XRDC_MDA_W5_2_DFMT1_LPID_SHIFT)) & XRDC_MDA_W5_2_DFMT1_LPID_MASK) 1402 1403 #define XRDC_MDA_W5_2_DFMT1_LPE_MASK (0x10000000U) 1404 #define XRDC_MDA_W5_2_DFMT1_LPE_SHIFT (28U) 1405 #define XRDC_MDA_W5_2_DFMT1_LPE_WIDTH (1U) 1406 #define XRDC_MDA_W5_2_DFMT1_LPE(x) (((uint32_t)(((uint32_t)(x)) << XRDC_MDA_W5_2_DFMT1_LPE_SHIFT)) & XRDC_MDA_W5_2_DFMT1_LPE_MASK) 1407 1408 #define XRDC_MDA_W5_2_DFMT1_DFMT_MASK (0x20000000U) 1409 #define XRDC_MDA_W5_2_DFMT1_DFMT_SHIFT (29U) 1410 #define XRDC_MDA_W5_2_DFMT1_DFMT_WIDTH (1U) 1411 #define XRDC_MDA_W5_2_DFMT1_DFMT(x) (((uint32_t)(((uint32_t)(x)) << XRDC_MDA_W5_2_DFMT1_DFMT_SHIFT)) & XRDC_MDA_W5_2_DFMT1_DFMT_MASK) 1412 1413 #define XRDC_MDA_W5_2_DFMT1_LK1_MASK (0x40000000U) 1414 #define XRDC_MDA_W5_2_DFMT1_LK1_SHIFT (30U) 1415 #define XRDC_MDA_W5_2_DFMT1_LK1_WIDTH (1U) 1416 #define XRDC_MDA_W5_2_DFMT1_LK1(x) (((uint32_t)(((uint32_t)(x)) << XRDC_MDA_W5_2_DFMT1_LK1_SHIFT)) & XRDC_MDA_W5_2_DFMT1_LK1_MASK) 1417 1418 #define XRDC_MDA_W5_2_DFMT1_VLD_MASK (0x80000000U) 1419 #define XRDC_MDA_W5_2_DFMT1_VLD_SHIFT (31U) 1420 #define XRDC_MDA_W5_2_DFMT1_VLD_WIDTH (1U) 1421 #define XRDC_MDA_W5_2_DFMT1_VLD(x) (((uint32_t)(((uint32_t)(x)) << XRDC_MDA_W5_2_DFMT1_VLD_SHIFT)) & XRDC_MDA_W5_2_DFMT1_VLD_MASK) 1422 /*! @} */ 1423 1424 /*! @name MDA_W6_2_DFMT1 - Master Domain Assignment */ 1425 /*! @{ */ 1426 1427 #define XRDC_MDA_W6_2_DFMT1_DID_MASK (0xFU) 1428 #define XRDC_MDA_W6_2_DFMT1_DID_SHIFT (0U) 1429 #define XRDC_MDA_W6_2_DFMT1_DID_WIDTH (4U) 1430 #define XRDC_MDA_W6_2_DFMT1_DID(x) (((uint32_t)(((uint32_t)(x)) << XRDC_MDA_W6_2_DFMT1_DID_SHIFT)) & XRDC_MDA_W6_2_DFMT1_DID_MASK) 1431 1432 #define XRDC_MDA_W6_2_DFMT1_PA_MASK (0x30U) 1433 #define XRDC_MDA_W6_2_DFMT1_PA_SHIFT (4U) 1434 #define XRDC_MDA_W6_2_DFMT1_PA_WIDTH (2U) 1435 #define XRDC_MDA_W6_2_DFMT1_PA(x) (((uint32_t)(((uint32_t)(x)) << XRDC_MDA_W6_2_DFMT1_PA_SHIFT)) & XRDC_MDA_W6_2_DFMT1_PA_MASK) 1436 1437 #define XRDC_MDA_W6_2_DFMT1_SA_MASK (0xC0U) 1438 #define XRDC_MDA_W6_2_DFMT1_SA_SHIFT (6U) 1439 #define XRDC_MDA_W6_2_DFMT1_SA_WIDTH (2U) 1440 #define XRDC_MDA_W6_2_DFMT1_SA(x) (((uint32_t)(((uint32_t)(x)) << XRDC_MDA_W6_2_DFMT1_SA_SHIFT)) & XRDC_MDA_W6_2_DFMT1_SA_MASK) 1441 1442 #define XRDC_MDA_W6_2_DFMT1_DIDB_MASK (0x100U) 1443 #define XRDC_MDA_W6_2_DFMT1_DIDB_SHIFT (8U) 1444 #define XRDC_MDA_W6_2_DFMT1_DIDB_WIDTH (1U) 1445 #define XRDC_MDA_W6_2_DFMT1_DIDB(x) (((uint32_t)(((uint32_t)(x)) << XRDC_MDA_W6_2_DFMT1_DIDB_SHIFT)) & XRDC_MDA_W6_2_DFMT1_DIDB_MASK) 1446 1447 #define XRDC_MDA_W6_2_DFMT1_LPID_MASK (0xF000000U) 1448 #define XRDC_MDA_W6_2_DFMT1_LPID_SHIFT (24U) 1449 #define XRDC_MDA_W6_2_DFMT1_LPID_WIDTH (4U) 1450 #define XRDC_MDA_W6_2_DFMT1_LPID(x) (((uint32_t)(((uint32_t)(x)) << XRDC_MDA_W6_2_DFMT1_LPID_SHIFT)) & XRDC_MDA_W6_2_DFMT1_LPID_MASK) 1451 1452 #define XRDC_MDA_W6_2_DFMT1_LPE_MASK (0x10000000U) 1453 #define XRDC_MDA_W6_2_DFMT1_LPE_SHIFT (28U) 1454 #define XRDC_MDA_W6_2_DFMT1_LPE_WIDTH (1U) 1455 #define XRDC_MDA_W6_2_DFMT1_LPE(x) (((uint32_t)(((uint32_t)(x)) << XRDC_MDA_W6_2_DFMT1_LPE_SHIFT)) & XRDC_MDA_W6_2_DFMT1_LPE_MASK) 1456 1457 #define XRDC_MDA_W6_2_DFMT1_DFMT_MASK (0x20000000U) 1458 #define XRDC_MDA_W6_2_DFMT1_DFMT_SHIFT (29U) 1459 #define XRDC_MDA_W6_2_DFMT1_DFMT_WIDTH (1U) 1460 #define XRDC_MDA_W6_2_DFMT1_DFMT(x) (((uint32_t)(((uint32_t)(x)) << XRDC_MDA_W6_2_DFMT1_DFMT_SHIFT)) & XRDC_MDA_W6_2_DFMT1_DFMT_MASK) 1461 1462 #define XRDC_MDA_W6_2_DFMT1_LK1_MASK (0x40000000U) 1463 #define XRDC_MDA_W6_2_DFMT1_LK1_SHIFT (30U) 1464 #define XRDC_MDA_W6_2_DFMT1_LK1_WIDTH (1U) 1465 #define XRDC_MDA_W6_2_DFMT1_LK1(x) (((uint32_t)(((uint32_t)(x)) << XRDC_MDA_W6_2_DFMT1_LK1_SHIFT)) & XRDC_MDA_W6_2_DFMT1_LK1_MASK) 1466 1467 #define XRDC_MDA_W6_2_DFMT1_VLD_MASK (0x80000000U) 1468 #define XRDC_MDA_W6_2_DFMT1_VLD_SHIFT (31U) 1469 #define XRDC_MDA_W6_2_DFMT1_VLD_WIDTH (1U) 1470 #define XRDC_MDA_W6_2_DFMT1_VLD(x) (((uint32_t)(((uint32_t)(x)) << XRDC_MDA_W6_2_DFMT1_VLD_SHIFT)) & XRDC_MDA_W6_2_DFMT1_VLD_MASK) 1471 /*! @} */ 1472 1473 /*! @name MDA_W7_2_DFMT1 - Master Domain Assignment */ 1474 /*! @{ */ 1475 1476 #define XRDC_MDA_W7_2_DFMT1_DID_MASK (0xFU) 1477 #define XRDC_MDA_W7_2_DFMT1_DID_SHIFT (0U) 1478 #define XRDC_MDA_W7_2_DFMT1_DID_WIDTH (4U) 1479 #define XRDC_MDA_W7_2_DFMT1_DID(x) (((uint32_t)(((uint32_t)(x)) << XRDC_MDA_W7_2_DFMT1_DID_SHIFT)) & XRDC_MDA_W7_2_DFMT1_DID_MASK) 1480 1481 #define XRDC_MDA_W7_2_DFMT1_PA_MASK (0x30U) 1482 #define XRDC_MDA_W7_2_DFMT1_PA_SHIFT (4U) 1483 #define XRDC_MDA_W7_2_DFMT1_PA_WIDTH (2U) 1484 #define XRDC_MDA_W7_2_DFMT1_PA(x) (((uint32_t)(((uint32_t)(x)) << XRDC_MDA_W7_2_DFMT1_PA_SHIFT)) & XRDC_MDA_W7_2_DFMT1_PA_MASK) 1485 1486 #define XRDC_MDA_W7_2_DFMT1_SA_MASK (0xC0U) 1487 #define XRDC_MDA_W7_2_DFMT1_SA_SHIFT (6U) 1488 #define XRDC_MDA_W7_2_DFMT1_SA_WIDTH (2U) 1489 #define XRDC_MDA_W7_2_DFMT1_SA(x) (((uint32_t)(((uint32_t)(x)) << XRDC_MDA_W7_2_DFMT1_SA_SHIFT)) & XRDC_MDA_W7_2_DFMT1_SA_MASK) 1490 1491 #define XRDC_MDA_W7_2_DFMT1_DIDB_MASK (0x100U) 1492 #define XRDC_MDA_W7_2_DFMT1_DIDB_SHIFT (8U) 1493 #define XRDC_MDA_W7_2_DFMT1_DIDB_WIDTH (1U) 1494 #define XRDC_MDA_W7_2_DFMT1_DIDB(x) (((uint32_t)(((uint32_t)(x)) << XRDC_MDA_W7_2_DFMT1_DIDB_SHIFT)) & XRDC_MDA_W7_2_DFMT1_DIDB_MASK) 1495 1496 #define XRDC_MDA_W7_2_DFMT1_LPID_MASK (0xF000000U) 1497 #define XRDC_MDA_W7_2_DFMT1_LPID_SHIFT (24U) 1498 #define XRDC_MDA_W7_2_DFMT1_LPID_WIDTH (4U) 1499 #define XRDC_MDA_W7_2_DFMT1_LPID(x) (((uint32_t)(((uint32_t)(x)) << XRDC_MDA_W7_2_DFMT1_LPID_SHIFT)) & XRDC_MDA_W7_2_DFMT1_LPID_MASK) 1500 1501 #define XRDC_MDA_W7_2_DFMT1_LPE_MASK (0x10000000U) 1502 #define XRDC_MDA_W7_2_DFMT1_LPE_SHIFT (28U) 1503 #define XRDC_MDA_W7_2_DFMT1_LPE_WIDTH (1U) 1504 #define XRDC_MDA_W7_2_DFMT1_LPE(x) (((uint32_t)(((uint32_t)(x)) << XRDC_MDA_W7_2_DFMT1_LPE_SHIFT)) & XRDC_MDA_W7_2_DFMT1_LPE_MASK) 1505 1506 #define XRDC_MDA_W7_2_DFMT1_DFMT_MASK (0x20000000U) 1507 #define XRDC_MDA_W7_2_DFMT1_DFMT_SHIFT (29U) 1508 #define XRDC_MDA_W7_2_DFMT1_DFMT_WIDTH (1U) 1509 #define XRDC_MDA_W7_2_DFMT1_DFMT(x) (((uint32_t)(((uint32_t)(x)) << XRDC_MDA_W7_2_DFMT1_DFMT_SHIFT)) & XRDC_MDA_W7_2_DFMT1_DFMT_MASK) 1510 1511 #define XRDC_MDA_W7_2_DFMT1_LK1_MASK (0x40000000U) 1512 #define XRDC_MDA_W7_2_DFMT1_LK1_SHIFT (30U) 1513 #define XRDC_MDA_W7_2_DFMT1_LK1_WIDTH (1U) 1514 #define XRDC_MDA_W7_2_DFMT1_LK1(x) (((uint32_t)(((uint32_t)(x)) << XRDC_MDA_W7_2_DFMT1_LK1_SHIFT)) & XRDC_MDA_W7_2_DFMT1_LK1_MASK) 1515 1516 #define XRDC_MDA_W7_2_DFMT1_VLD_MASK (0x80000000U) 1517 #define XRDC_MDA_W7_2_DFMT1_VLD_SHIFT (31U) 1518 #define XRDC_MDA_W7_2_DFMT1_VLD_WIDTH (1U) 1519 #define XRDC_MDA_W7_2_DFMT1_VLD(x) (((uint32_t)(((uint32_t)(x)) << XRDC_MDA_W7_2_DFMT1_VLD_SHIFT)) & XRDC_MDA_W7_2_DFMT1_VLD_MASK) 1520 /*! @} */ 1521 1522 /*! @name MDA_W0_3_DFMT1 - Master Domain Assignment */ 1523 /*! @{ */ 1524 1525 #define XRDC_MDA_W0_3_DFMT1_DID_MASK (0xFU) 1526 #define XRDC_MDA_W0_3_DFMT1_DID_SHIFT (0U) 1527 #define XRDC_MDA_W0_3_DFMT1_DID_WIDTH (4U) 1528 #define XRDC_MDA_W0_3_DFMT1_DID(x) (((uint32_t)(((uint32_t)(x)) << XRDC_MDA_W0_3_DFMT1_DID_SHIFT)) & XRDC_MDA_W0_3_DFMT1_DID_MASK) 1529 1530 #define XRDC_MDA_W0_3_DFMT1_PA_MASK (0x30U) 1531 #define XRDC_MDA_W0_3_DFMT1_PA_SHIFT (4U) 1532 #define XRDC_MDA_W0_3_DFMT1_PA_WIDTH (2U) 1533 #define XRDC_MDA_W0_3_DFMT1_PA(x) (((uint32_t)(((uint32_t)(x)) << XRDC_MDA_W0_3_DFMT1_PA_SHIFT)) & XRDC_MDA_W0_3_DFMT1_PA_MASK) 1534 1535 #define XRDC_MDA_W0_3_DFMT1_SA_MASK (0xC0U) 1536 #define XRDC_MDA_W0_3_DFMT1_SA_SHIFT (6U) 1537 #define XRDC_MDA_W0_3_DFMT1_SA_WIDTH (2U) 1538 #define XRDC_MDA_W0_3_DFMT1_SA(x) (((uint32_t)(((uint32_t)(x)) << XRDC_MDA_W0_3_DFMT1_SA_SHIFT)) & XRDC_MDA_W0_3_DFMT1_SA_MASK) 1539 1540 #define XRDC_MDA_W0_3_DFMT1_DIDB_MASK (0x100U) 1541 #define XRDC_MDA_W0_3_DFMT1_DIDB_SHIFT (8U) 1542 #define XRDC_MDA_W0_3_DFMT1_DIDB_WIDTH (1U) 1543 #define XRDC_MDA_W0_3_DFMT1_DIDB(x) (((uint32_t)(((uint32_t)(x)) << XRDC_MDA_W0_3_DFMT1_DIDB_SHIFT)) & XRDC_MDA_W0_3_DFMT1_DIDB_MASK) 1544 1545 #define XRDC_MDA_W0_3_DFMT1_DFMT_MASK (0x20000000U) 1546 #define XRDC_MDA_W0_3_DFMT1_DFMT_SHIFT (29U) 1547 #define XRDC_MDA_W0_3_DFMT1_DFMT_WIDTH (1U) 1548 #define XRDC_MDA_W0_3_DFMT1_DFMT(x) (((uint32_t)(((uint32_t)(x)) << XRDC_MDA_W0_3_DFMT1_DFMT_SHIFT)) & XRDC_MDA_W0_3_DFMT1_DFMT_MASK) 1549 1550 #define XRDC_MDA_W0_3_DFMT1_LK1_MASK (0x40000000U) 1551 #define XRDC_MDA_W0_3_DFMT1_LK1_SHIFT (30U) 1552 #define XRDC_MDA_W0_3_DFMT1_LK1_WIDTH (1U) 1553 #define XRDC_MDA_W0_3_DFMT1_LK1(x) (((uint32_t)(((uint32_t)(x)) << XRDC_MDA_W0_3_DFMT1_LK1_SHIFT)) & XRDC_MDA_W0_3_DFMT1_LK1_MASK) 1554 1555 #define XRDC_MDA_W0_3_DFMT1_VLD_MASK (0x80000000U) 1556 #define XRDC_MDA_W0_3_DFMT1_VLD_SHIFT (31U) 1557 #define XRDC_MDA_W0_3_DFMT1_VLD_WIDTH (1U) 1558 #define XRDC_MDA_W0_3_DFMT1_VLD(x) (((uint32_t)(((uint32_t)(x)) << XRDC_MDA_W0_3_DFMT1_VLD_SHIFT)) & XRDC_MDA_W0_3_DFMT1_VLD_MASK) 1559 /*! @} */ 1560 1561 /*! @name MDA_W0_4_DFMT1 - Master Domain Assignment */ 1562 /*! @{ */ 1563 1564 #define XRDC_MDA_W0_4_DFMT1_DID_MASK (0xFU) 1565 #define XRDC_MDA_W0_4_DFMT1_DID_SHIFT (0U) 1566 #define XRDC_MDA_W0_4_DFMT1_DID_WIDTH (4U) 1567 #define XRDC_MDA_W0_4_DFMT1_DID(x) (((uint32_t)(((uint32_t)(x)) << XRDC_MDA_W0_4_DFMT1_DID_SHIFT)) & XRDC_MDA_W0_4_DFMT1_DID_MASK) 1568 1569 #define XRDC_MDA_W0_4_DFMT1_PA_MASK (0x30U) 1570 #define XRDC_MDA_W0_4_DFMT1_PA_SHIFT (4U) 1571 #define XRDC_MDA_W0_4_DFMT1_PA_WIDTH (2U) 1572 #define XRDC_MDA_W0_4_DFMT1_PA(x) (((uint32_t)(((uint32_t)(x)) << XRDC_MDA_W0_4_DFMT1_PA_SHIFT)) & XRDC_MDA_W0_4_DFMT1_PA_MASK) 1573 1574 #define XRDC_MDA_W0_4_DFMT1_SA_MASK (0xC0U) 1575 #define XRDC_MDA_W0_4_DFMT1_SA_SHIFT (6U) 1576 #define XRDC_MDA_W0_4_DFMT1_SA_WIDTH (2U) 1577 #define XRDC_MDA_W0_4_DFMT1_SA(x) (((uint32_t)(((uint32_t)(x)) << XRDC_MDA_W0_4_DFMT1_SA_SHIFT)) & XRDC_MDA_W0_4_DFMT1_SA_MASK) 1578 1579 #define XRDC_MDA_W0_4_DFMT1_DIDB_MASK (0x100U) 1580 #define XRDC_MDA_W0_4_DFMT1_DIDB_SHIFT (8U) 1581 #define XRDC_MDA_W0_4_DFMT1_DIDB_WIDTH (1U) 1582 #define XRDC_MDA_W0_4_DFMT1_DIDB(x) (((uint32_t)(((uint32_t)(x)) << XRDC_MDA_W0_4_DFMT1_DIDB_SHIFT)) & XRDC_MDA_W0_4_DFMT1_DIDB_MASK) 1583 1584 #define XRDC_MDA_W0_4_DFMT1_DFMT_MASK (0x20000000U) 1585 #define XRDC_MDA_W0_4_DFMT1_DFMT_SHIFT (29U) 1586 #define XRDC_MDA_W0_4_DFMT1_DFMT_WIDTH (1U) 1587 #define XRDC_MDA_W0_4_DFMT1_DFMT(x) (((uint32_t)(((uint32_t)(x)) << XRDC_MDA_W0_4_DFMT1_DFMT_SHIFT)) & XRDC_MDA_W0_4_DFMT1_DFMT_MASK) 1588 1589 #define XRDC_MDA_W0_4_DFMT1_LK1_MASK (0x40000000U) 1590 #define XRDC_MDA_W0_4_DFMT1_LK1_SHIFT (30U) 1591 #define XRDC_MDA_W0_4_DFMT1_LK1_WIDTH (1U) 1592 #define XRDC_MDA_W0_4_DFMT1_LK1(x) (((uint32_t)(((uint32_t)(x)) << XRDC_MDA_W0_4_DFMT1_LK1_SHIFT)) & XRDC_MDA_W0_4_DFMT1_LK1_MASK) 1593 1594 #define XRDC_MDA_W0_4_DFMT1_VLD_MASK (0x80000000U) 1595 #define XRDC_MDA_W0_4_DFMT1_VLD_SHIFT (31U) 1596 #define XRDC_MDA_W0_4_DFMT1_VLD_WIDTH (1U) 1597 #define XRDC_MDA_W0_4_DFMT1_VLD(x) (((uint32_t)(((uint32_t)(x)) << XRDC_MDA_W0_4_DFMT1_VLD_SHIFT)) & XRDC_MDA_W0_4_DFMT1_VLD_MASK) 1598 /*! @} */ 1599 1600 /*! @name PDAC_W0 - Peripheral Domain Access Control Word 0 */ 1601 /*! @{ */ 1602 1603 #define XRDC_PDAC_W0_D0ACP_MASK (0x7U) 1604 #define XRDC_PDAC_W0_D0ACP_SHIFT (0U) 1605 #define XRDC_PDAC_W0_D0ACP_WIDTH (3U) 1606 #define XRDC_PDAC_W0_D0ACP(x) (((uint32_t)(((uint32_t)(x)) << XRDC_PDAC_W0_D0ACP_SHIFT)) & XRDC_PDAC_W0_D0ACP_MASK) 1607 1608 #define XRDC_PDAC_W0_D1ACP_MASK (0x38U) 1609 #define XRDC_PDAC_W0_D1ACP_SHIFT (3U) 1610 #define XRDC_PDAC_W0_D1ACP_WIDTH (3U) 1611 #define XRDC_PDAC_W0_D1ACP(x) (((uint32_t)(((uint32_t)(x)) << XRDC_PDAC_W0_D1ACP_SHIFT)) & XRDC_PDAC_W0_D1ACP_MASK) 1612 1613 #define XRDC_PDAC_W0_D2ACP_MASK (0x1C0U) 1614 #define XRDC_PDAC_W0_D2ACP_SHIFT (6U) 1615 #define XRDC_PDAC_W0_D2ACP_WIDTH (3U) 1616 #define XRDC_PDAC_W0_D2ACP(x) (((uint32_t)(((uint32_t)(x)) << XRDC_PDAC_W0_D2ACP_SHIFT)) & XRDC_PDAC_W0_D2ACP_MASK) 1617 1618 #define XRDC_PDAC_W0_D3ACP_MASK (0xE00U) 1619 #define XRDC_PDAC_W0_D3ACP_SHIFT (9U) 1620 #define XRDC_PDAC_W0_D3ACP_WIDTH (3U) 1621 #define XRDC_PDAC_W0_D3ACP(x) (((uint32_t)(((uint32_t)(x)) << XRDC_PDAC_W0_D3ACP_SHIFT)) & XRDC_PDAC_W0_D3ACP_MASK) 1622 1623 #define XRDC_PDAC_W0_D4ACP_MASK (0x7000U) 1624 #define XRDC_PDAC_W0_D4ACP_SHIFT (12U) 1625 #define XRDC_PDAC_W0_D4ACP_WIDTH (3U) 1626 #define XRDC_PDAC_W0_D4ACP(x) (((uint32_t)(((uint32_t)(x)) << XRDC_PDAC_W0_D4ACP_SHIFT)) & XRDC_PDAC_W0_D4ACP_MASK) 1627 1628 #define XRDC_PDAC_W0_D5ACP_MASK (0x38000U) 1629 #define XRDC_PDAC_W0_D5ACP_SHIFT (15U) 1630 #define XRDC_PDAC_W0_D5ACP_WIDTH (3U) 1631 #define XRDC_PDAC_W0_D5ACP(x) (((uint32_t)(((uint32_t)(x)) << XRDC_PDAC_W0_D5ACP_SHIFT)) & XRDC_PDAC_W0_D5ACP_MASK) 1632 1633 #define XRDC_PDAC_W0_D6ACP_MASK (0x1C0000U) 1634 #define XRDC_PDAC_W0_D6ACP_SHIFT (18U) 1635 #define XRDC_PDAC_W0_D6ACP_WIDTH (3U) 1636 #define XRDC_PDAC_W0_D6ACP(x) (((uint32_t)(((uint32_t)(x)) << XRDC_PDAC_W0_D6ACP_SHIFT)) & XRDC_PDAC_W0_D6ACP_MASK) 1637 1638 #define XRDC_PDAC_W0_D7ACP_MASK (0xE00000U) 1639 #define XRDC_PDAC_W0_D7ACP_SHIFT (21U) 1640 #define XRDC_PDAC_W0_D7ACP_WIDTH (3U) 1641 #define XRDC_PDAC_W0_D7ACP(x) (((uint32_t)(((uint32_t)(x)) << XRDC_PDAC_W0_D7ACP_SHIFT)) & XRDC_PDAC_W0_D7ACP_MASK) 1642 1643 #define XRDC_PDAC_W0_SNUM_MASK (0xF000000U) 1644 #define XRDC_PDAC_W0_SNUM_SHIFT (24U) 1645 #define XRDC_PDAC_W0_SNUM_WIDTH (4U) 1646 #define XRDC_PDAC_W0_SNUM(x) (((uint32_t)(((uint32_t)(x)) << XRDC_PDAC_W0_SNUM_SHIFT)) & XRDC_PDAC_W0_SNUM_MASK) 1647 1648 #define XRDC_PDAC_W0_SE_MASK (0x40000000U) 1649 #define XRDC_PDAC_W0_SE_SHIFT (30U) 1650 #define XRDC_PDAC_W0_SE_WIDTH (1U) 1651 #define XRDC_PDAC_W0_SE(x) (((uint32_t)(((uint32_t)(x)) << XRDC_PDAC_W0_SE_SHIFT)) & XRDC_PDAC_W0_SE_MASK) 1652 /*! @} */ 1653 1654 /*! @name PDAC_W1 - Peripheral Domain Access Control Word 1 */ 1655 /*! @{ */ 1656 1657 #define XRDC_PDAC_W1_D8ACP_MASK (0x7U) 1658 #define XRDC_PDAC_W1_D8ACP_SHIFT (0U) 1659 #define XRDC_PDAC_W1_D8ACP_WIDTH (3U) 1660 #define XRDC_PDAC_W1_D8ACP(x) (((uint32_t)(((uint32_t)(x)) << XRDC_PDAC_W1_D8ACP_SHIFT)) & XRDC_PDAC_W1_D8ACP_MASK) 1661 1662 #define XRDC_PDAC_W1_D9ACP_MASK (0x38U) 1663 #define XRDC_PDAC_W1_D9ACP_SHIFT (3U) 1664 #define XRDC_PDAC_W1_D9ACP_WIDTH (3U) 1665 #define XRDC_PDAC_W1_D9ACP(x) (((uint32_t)(((uint32_t)(x)) << XRDC_PDAC_W1_D9ACP_SHIFT)) & XRDC_PDAC_W1_D9ACP_MASK) 1666 1667 #define XRDC_PDAC_W1_D10ACP_MASK (0x1C0U) 1668 #define XRDC_PDAC_W1_D10ACP_SHIFT (6U) 1669 #define XRDC_PDAC_W1_D10ACP_WIDTH (3U) 1670 #define XRDC_PDAC_W1_D10ACP(x) (((uint32_t)(((uint32_t)(x)) << XRDC_PDAC_W1_D10ACP_SHIFT)) & XRDC_PDAC_W1_D10ACP_MASK) 1671 1672 #define XRDC_PDAC_W1_D11ACP_MASK (0xE00U) 1673 #define XRDC_PDAC_W1_D11ACP_SHIFT (9U) 1674 #define XRDC_PDAC_W1_D11ACP_WIDTH (3U) 1675 #define XRDC_PDAC_W1_D11ACP(x) (((uint32_t)(((uint32_t)(x)) << XRDC_PDAC_W1_D11ACP_SHIFT)) & XRDC_PDAC_W1_D11ACP_MASK) 1676 1677 #define XRDC_PDAC_W1_D12ACP_MASK (0x7000U) 1678 #define XRDC_PDAC_W1_D12ACP_SHIFT (12U) 1679 #define XRDC_PDAC_W1_D12ACP_WIDTH (3U) 1680 #define XRDC_PDAC_W1_D12ACP(x) (((uint32_t)(((uint32_t)(x)) << XRDC_PDAC_W1_D12ACP_SHIFT)) & XRDC_PDAC_W1_D12ACP_MASK) 1681 1682 #define XRDC_PDAC_W1_D13ACP_MASK (0x38000U) 1683 #define XRDC_PDAC_W1_D13ACP_SHIFT (15U) 1684 #define XRDC_PDAC_W1_D13ACP_WIDTH (3U) 1685 #define XRDC_PDAC_W1_D13ACP(x) (((uint32_t)(((uint32_t)(x)) << XRDC_PDAC_W1_D13ACP_SHIFT)) & XRDC_PDAC_W1_D13ACP_MASK) 1686 1687 #define XRDC_PDAC_W1_D14ACP_MASK (0x1C0000U) 1688 #define XRDC_PDAC_W1_D14ACP_SHIFT (18U) 1689 #define XRDC_PDAC_W1_D14ACP_WIDTH (3U) 1690 #define XRDC_PDAC_W1_D14ACP(x) (((uint32_t)(((uint32_t)(x)) << XRDC_PDAC_W1_D14ACP_SHIFT)) & XRDC_PDAC_W1_D14ACP_MASK) 1691 1692 #define XRDC_PDAC_W1_D15ACP_MASK (0xE00000U) 1693 #define XRDC_PDAC_W1_D15ACP_SHIFT (21U) 1694 #define XRDC_PDAC_W1_D15ACP_WIDTH (3U) 1695 #define XRDC_PDAC_W1_D15ACP(x) (((uint32_t)(((uint32_t)(x)) << XRDC_PDAC_W1_D15ACP_SHIFT)) & XRDC_PDAC_W1_D15ACP_MASK) 1696 1697 #define XRDC_PDAC_W1_LK2_MASK (0x60000000U) 1698 #define XRDC_PDAC_W1_LK2_SHIFT (29U) 1699 #define XRDC_PDAC_W1_LK2_WIDTH (2U) 1700 #define XRDC_PDAC_W1_LK2(x) (((uint32_t)(((uint32_t)(x)) << XRDC_PDAC_W1_LK2_SHIFT)) & XRDC_PDAC_W1_LK2_MASK) 1701 1702 #define XRDC_PDAC_W1_VLD_MASK (0x80000000U) 1703 #define XRDC_PDAC_W1_VLD_SHIFT (31U) 1704 #define XRDC_PDAC_W1_VLD_WIDTH (1U) 1705 #define XRDC_PDAC_W1_VLD(x) (((uint32_t)(((uint32_t)(x)) << XRDC_PDAC_W1_VLD_SHIFT)) & XRDC_PDAC_W1_VLD_MASK) 1706 /*! @} */ 1707 1708 /*! @name XRDC_MRGD_W0 - Memory Region Descriptor Word 0 */ 1709 /*! @{ */ 1710 1711 #define XRDC_XRDC_MRGD_W0_SRTADDR_MASK (0xFFFFFFE0U) 1712 #define XRDC_XRDC_MRGD_W0_SRTADDR_SHIFT (5U) 1713 #define XRDC_XRDC_MRGD_W0_SRTADDR_WIDTH (27U) 1714 #define XRDC_XRDC_MRGD_W0_SRTADDR(x) (((uint32_t)(((uint32_t)(x)) << XRDC_XRDC_MRGD_W0_SRTADDR_SHIFT)) & XRDC_XRDC_MRGD_W0_SRTADDR_MASK) 1715 /*! @} */ 1716 1717 /*! @name XRDC_MRGD_W1 - Memory Region Descriptor Word 1 */ 1718 /*! @{ */ 1719 1720 #define XRDC_XRDC_MRGD_W1_ENDADDR_MASK (0xFFFFFFE0U) 1721 #define XRDC_XRDC_MRGD_W1_ENDADDR_SHIFT (5U) 1722 #define XRDC_XRDC_MRGD_W1_ENDADDR_WIDTH (27U) 1723 #define XRDC_XRDC_MRGD_W1_ENDADDR(x) (((uint32_t)(((uint32_t)(x)) << XRDC_XRDC_MRGD_W1_ENDADDR_SHIFT)) & XRDC_XRDC_MRGD_W1_ENDADDR_MASK) 1724 /*! @} */ 1725 1726 /*! @name XRDC_MRGD_W2 - Memory Region Descriptor Word 2 */ 1727 /*! @{ */ 1728 1729 #define XRDC_XRDC_MRGD_W2_D0ACP_MASK (0x7U) 1730 #define XRDC_XRDC_MRGD_W2_D0ACP_SHIFT (0U) 1731 #define XRDC_XRDC_MRGD_W2_D0ACP_WIDTH (3U) 1732 #define XRDC_XRDC_MRGD_W2_D0ACP(x) (((uint32_t)(((uint32_t)(x)) << XRDC_XRDC_MRGD_W2_D0ACP_SHIFT)) & XRDC_XRDC_MRGD_W2_D0ACP_MASK) 1733 1734 #define XRDC_XRDC_MRGD_W2_D1ACP_MASK (0x38U) 1735 #define XRDC_XRDC_MRGD_W2_D1ACP_SHIFT (3U) 1736 #define XRDC_XRDC_MRGD_W2_D1ACP_WIDTH (3U) 1737 #define XRDC_XRDC_MRGD_W2_D1ACP(x) (((uint32_t)(((uint32_t)(x)) << XRDC_XRDC_MRGD_W2_D1ACP_SHIFT)) & XRDC_XRDC_MRGD_W2_D1ACP_MASK) 1738 1739 #define XRDC_XRDC_MRGD_W2_D2ACP_MASK (0x1C0U) 1740 #define XRDC_XRDC_MRGD_W2_D2ACP_SHIFT (6U) 1741 #define XRDC_XRDC_MRGD_W2_D2ACP_WIDTH (3U) 1742 #define XRDC_XRDC_MRGD_W2_D2ACP(x) (((uint32_t)(((uint32_t)(x)) << XRDC_XRDC_MRGD_W2_D2ACP_SHIFT)) & XRDC_XRDC_MRGD_W2_D2ACP_MASK) 1743 1744 #define XRDC_XRDC_MRGD_W2_D3ACP_MASK (0xE00U) 1745 #define XRDC_XRDC_MRGD_W2_D3ACP_SHIFT (9U) 1746 #define XRDC_XRDC_MRGD_W2_D3ACP_WIDTH (3U) 1747 #define XRDC_XRDC_MRGD_W2_D3ACP(x) (((uint32_t)(((uint32_t)(x)) << XRDC_XRDC_MRGD_W2_D3ACP_SHIFT)) & XRDC_XRDC_MRGD_W2_D3ACP_MASK) 1748 1749 #define XRDC_XRDC_MRGD_W2_D4ACP_MASK (0x7000U) 1750 #define XRDC_XRDC_MRGD_W2_D4ACP_SHIFT (12U) 1751 #define XRDC_XRDC_MRGD_W2_D4ACP_WIDTH (3U) 1752 #define XRDC_XRDC_MRGD_W2_D4ACP(x) (((uint32_t)(((uint32_t)(x)) << XRDC_XRDC_MRGD_W2_D4ACP_SHIFT)) & XRDC_XRDC_MRGD_W2_D4ACP_MASK) 1753 1754 #define XRDC_XRDC_MRGD_W2_D5ACP_MASK (0x38000U) 1755 #define XRDC_XRDC_MRGD_W2_D5ACP_SHIFT (15U) 1756 #define XRDC_XRDC_MRGD_W2_D5ACP_WIDTH (3U) 1757 #define XRDC_XRDC_MRGD_W2_D5ACP(x) (((uint32_t)(((uint32_t)(x)) << XRDC_XRDC_MRGD_W2_D5ACP_SHIFT)) & XRDC_XRDC_MRGD_W2_D5ACP_MASK) 1758 1759 #define XRDC_XRDC_MRGD_W2_D6ACP_MASK (0x1C0000U) 1760 #define XRDC_XRDC_MRGD_W2_D6ACP_SHIFT (18U) 1761 #define XRDC_XRDC_MRGD_W2_D6ACP_WIDTH (3U) 1762 #define XRDC_XRDC_MRGD_W2_D6ACP(x) (((uint32_t)(((uint32_t)(x)) << XRDC_XRDC_MRGD_W2_D6ACP_SHIFT)) & XRDC_XRDC_MRGD_W2_D6ACP_MASK) 1763 1764 #define XRDC_XRDC_MRGD_W2_D7ACP_MASK (0xE00000U) 1765 #define XRDC_XRDC_MRGD_W2_D7ACP_SHIFT (21U) 1766 #define XRDC_XRDC_MRGD_W2_D7ACP_WIDTH (3U) 1767 #define XRDC_XRDC_MRGD_W2_D7ACP(x) (((uint32_t)(((uint32_t)(x)) << XRDC_XRDC_MRGD_W2_D7ACP_SHIFT)) & XRDC_XRDC_MRGD_W2_D7ACP_MASK) 1768 1769 #define XRDC_XRDC_MRGD_W2_SNUM_MASK (0xF000000U) 1770 #define XRDC_XRDC_MRGD_W2_SNUM_SHIFT (24U) 1771 #define XRDC_XRDC_MRGD_W2_SNUM_WIDTH (4U) 1772 #define XRDC_XRDC_MRGD_W2_SNUM(x) (((uint32_t)(((uint32_t)(x)) << XRDC_XRDC_MRGD_W2_SNUM_SHIFT)) & XRDC_XRDC_MRGD_W2_SNUM_MASK) 1773 1774 #define XRDC_XRDC_MRGD_W2_SE_MASK (0x40000000U) 1775 #define XRDC_XRDC_MRGD_W2_SE_SHIFT (30U) 1776 #define XRDC_XRDC_MRGD_W2_SE_WIDTH (1U) 1777 #define XRDC_XRDC_MRGD_W2_SE(x) (((uint32_t)(((uint32_t)(x)) << XRDC_XRDC_MRGD_W2_SE_SHIFT)) & XRDC_XRDC_MRGD_W2_SE_MASK) 1778 /*! @} */ 1779 1780 /*! @name XRDC_MRGD_W3 - Memory Region Descriptor Word 3 */ 1781 /*! @{ */ 1782 1783 #define XRDC_XRDC_MRGD_W3_D8ACP_MASK (0x7U) 1784 #define XRDC_XRDC_MRGD_W3_D8ACP_SHIFT (0U) 1785 #define XRDC_XRDC_MRGD_W3_D8ACP_WIDTH (3U) 1786 #define XRDC_XRDC_MRGD_W3_D8ACP(x) (((uint32_t)(((uint32_t)(x)) << XRDC_XRDC_MRGD_W3_D8ACP_SHIFT)) & XRDC_XRDC_MRGD_W3_D8ACP_MASK) 1787 1788 #define XRDC_XRDC_MRGD_W3_D9ACP_MASK (0x38U) 1789 #define XRDC_XRDC_MRGD_W3_D9ACP_SHIFT (3U) 1790 #define XRDC_XRDC_MRGD_W3_D9ACP_WIDTH (3U) 1791 #define XRDC_XRDC_MRGD_W3_D9ACP(x) (((uint32_t)(((uint32_t)(x)) << XRDC_XRDC_MRGD_W3_D9ACP_SHIFT)) & XRDC_XRDC_MRGD_W3_D9ACP_MASK) 1792 1793 #define XRDC_XRDC_MRGD_W3_D10ACP_MASK (0x1C0U) 1794 #define XRDC_XRDC_MRGD_W3_D10ACP_SHIFT (6U) 1795 #define XRDC_XRDC_MRGD_W3_D10ACP_WIDTH (3U) 1796 #define XRDC_XRDC_MRGD_W3_D10ACP(x) (((uint32_t)(((uint32_t)(x)) << XRDC_XRDC_MRGD_W3_D10ACP_SHIFT)) & XRDC_XRDC_MRGD_W3_D10ACP_MASK) 1797 1798 #define XRDC_XRDC_MRGD_W3_D11ACP_MASK (0xE00U) 1799 #define XRDC_XRDC_MRGD_W3_D11ACP_SHIFT (9U) 1800 #define XRDC_XRDC_MRGD_W3_D11ACP_WIDTH (3U) 1801 #define XRDC_XRDC_MRGD_W3_D11ACP(x) (((uint32_t)(((uint32_t)(x)) << XRDC_XRDC_MRGD_W3_D11ACP_SHIFT)) & XRDC_XRDC_MRGD_W3_D11ACP_MASK) 1802 1803 #define XRDC_XRDC_MRGD_W3_D12ACP_MASK (0x7000U) 1804 #define XRDC_XRDC_MRGD_W3_D12ACP_SHIFT (12U) 1805 #define XRDC_XRDC_MRGD_W3_D12ACP_WIDTH (3U) 1806 #define XRDC_XRDC_MRGD_W3_D12ACP(x) (((uint32_t)(((uint32_t)(x)) << XRDC_XRDC_MRGD_W3_D12ACP_SHIFT)) & XRDC_XRDC_MRGD_W3_D12ACP_MASK) 1807 1808 #define XRDC_XRDC_MRGD_W3_D13ACP_MASK (0x38000U) 1809 #define XRDC_XRDC_MRGD_W3_D13ACP_SHIFT (15U) 1810 #define XRDC_XRDC_MRGD_W3_D13ACP_WIDTH (3U) 1811 #define XRDC_XRDC_MRGD_W3_D13ACP(x) (((uint32_t)(((uint32_t)(x)) << XRDC_XRDC_MRGD_W3_D13ACP_SHIFT)) & XRDC_XRDC_MRGD_W3_D13ACP_MASK) 1812 1813 #define XRDC_XRDC_MRGD_W3_D14ACP_MASK (0x1C0000U) 1814 #define XRDC_XRDC_MRGD_W3_D14ACP_SHIFT (18U) 1815 #define XRDC_XRDC_MRGD_W3_D14ACP_WIDTH (3U) 1816 #define XRDC_XRDC_MRGD_W3_D14ACP(x) (((uint32_t)(((uint32_t)(x)) << XRDC_XRDC_MRGD_W3_D14ACP_SHIFT)) & XRDC_XRDC_MRGD_W3_D14ACP_MASK) 1817 1818 #define XRDC_XRDC_MRGD_W3_D15ACP_MASK (0xE00000U) 1819 #define XRDC_XRDC_MRGD_W3_D15ACP_SHIFT (21U) 1820 #define XRDC_XRDC_MRGD_W3_D15ACP_WIDTH (3U) 1821 #define XRDC_XRDC_MRGD_W3_D15ACP(x) (((uint32_t)(((uint32_t)(x)) << XRDC_XRDC_MRGD_W3_D15ACP_SHIFT)) & XRDC_XRDC_MRGD_W3_D15ACP_MASK) 1822 1823 #define XRDC_XRDC_MRGD_W3_LK2_MASK (0x60000000U) 1824 #define XRDC_XRDC_MRGD_W3_LK2_SHIFT (29U) 1825 #define XRDC_XRDC_MRGD_W3_LK2_WIDTH (2U) 1826 #define XRDC_XRDC_MRGD_W3_LK2(x) (((uint32_t)(((uint32_t)(x)) << XRDC_XRDC_MRGD_W3_LK2_SHIFT)) & XRDC_XRDC_MRGD_W3_LK2_MASK) 1827 1828 #define XRDC_XRDC_MRGD_W3_VLD_MASK (0x80000000U) 1829 #define XRDC_XRDC_MRGD_W3_VLD_SHIFT (31U) 1830 #define XRDC_XRDC_MRGD_W3_VLD_WIDTH (1U) 1831 #define XRDC_XRDC_MRGD_W3_VLD(x) (((uint32_t)(((uint32_t)(x)) << XRDC_XRDC_MRGD_W3_VLD_SHIFT)) & XRDC_XRDC_MRGD_W3_VLD_MASK) 1832 /*! @} */ 1833 1834 /*! 1835 * @} 1836 */ /* end of group XRDC_Register_Masks */ 1837 1838 /*! 1839 * @} 1840 */ /* end of group XRDC_Peripheral_Access_Layer */ 1841 1842 #endif /* #if !defined(S32Z2_XRDC_H_) */ 1843
