1 /* 2 * Copyright 1997-2016 Freescale Semiconductor, Inc. 3 * Copyright 2016-2021 NXP 4 * 5 * SPDX-License-Identifier: BSD-3-Clause 6 */ 7 8 /*! 9 * @file S32K344_XRDC.h 10 * @version 1.9 11 * @date 2021-10-27 12 * @brief Peripheral Access Layer for S32K344_XRDC 13 * 14 * This file contains register definitions and macros for easy access to their 15 * bit fields. 16 * 17 * This file assumes LITTLE endian system. 18 */ 19 20 /** 21 * @page misra_violations MISRA-C:2012 violations 22 * 23 * @section [global] 24 * Violates MISRA 2012 Advisory Rule 2.3, local typedef not referenced 25 * The SoC header defines typedef for all modules. 26 * 27 * @section [global] 28 * Violates MISRA 2012 Advisory Rule 2.5, local macro not referenced 29 * The SoC header defines macros for all modules and registers. 30 * 31 * @section [global] 32 * Violates MISRA 2012 Advisory Directive 4.9, Function-like macro 33 * These are generated macros used for accessing the bit-fields from registers. 34 * 35 * @section [global] 36 * Violates MISRA 2012 Required Rule 5.1, identifier clash 37 * The supported compilers use more than 31 significant characters for identifiers. 38 * 39 * @section [global] 40 * Violates MISRA 2012 Required Rule 5.2, identifier clash 41 * The supported compilers use more than 31 significant characters for identifiers. 42 * 43 * @section [global] 44 * Violates MISRA 2012 Required Rule 5.4, identifier clash 45 * The supported compilers use more than 31 significant characters for identifiers. 46 * 47 * @section [global] 48 * Violates MISRA 2012 Required Rule 5.5, identifier clash 49 * The supported compilers use more than 31 significant characters for identifiers. 50 * 51 * @section [global] 52 * Violates MISRA 2012 Required Rule 21.1, defined macro '__I' is reserved to the compiler 53 * This type qualifier is needed to ensure correct I/O access and addressing. 54 */ 55 56 /* Prevention from multiple including the same memory map */ 57 #if !defined(S32K344_XRDC_H_) /* Check if memory map has not been already included */ 58 #define S32K344_XRDC_H_ 59 60 #include "S32K344_COMMON.h" 61 62 /* ---------------------------------------------------------------------------- 63 -- XRDC Peripheral Access Layer 64 ---------------------------------------------------------------------------- */ 65 66 /*! 67 * @addtogroup XRDC_Peripheral_Access_Layer XRDC Peripheral Access Layer 68 * @{ 69 */ 70 71 /** XRDC - Size of Registers Arrays */ 72 #define XRDC_MDAC_COUNT 6u 73 #define XRDC_MRC_COUNT 3u 74 #define XRDC_DERRLOC_COUNT 3u 75 #define XRDC_DERRW0_COUNT 19u 76 #define XRDC_PID_COUNT 4u 77 #define XRDC_PDAC_SLOT_PDACN_COUNT 109u 78 #define XRDC_PDAC_SLOT_COUNT 3u 79 #define XRDC_MRCN_COUNT 3u 80 #define XRDC_MRCN_MRGDN_COUNT 16u 81 82 /** XRDC - Register Layout Typedef */ 83 typedef struct { 84 __IO uint32_t CR; /**< Control, offset: 0x0 */ 85 uint8_t RESERVED_0[236]; 86 __I uint32_t HWCFG0; /**< Hardware Configuration 0, offset: 0xF0 */ 87 __I uint32_t HWCFG1; /**< Hardware Configuration 1, offset: 0xF4 */ 88 __I uint32_t HWCFG2; /**< Hardware Configuration 2, offset: 0xF8 */ 89 uint8_t RESERVED_1[4]; 90 __I uint8_t MDACFG[XRDC_MDAC_COUNT]; /**< Master Domain Assignment Configuration, array offset: 0x100, array step: 0x1 */ 91 uint8_t RESERVED_2[58]; 92 __I uint8_t MRCFG[XRDC_MRC_COUNT]; /**< Memory Region Configuration, array offset: 0x140, array step: 0x1 */ 93 uint8_t RESERVED_3[189]; 94 __I uint32_t DERRLOC[XRDC_DERRLOC_COUNT]; /**< Domain Error Location, array offset: 0x200, array step: 0x4 */ 95 uint8_t RESERVED_4[500]; 96 struct { /* offset: 0x400, array step: 0x10 */ 97 __I uint32_t DERR_W0; /**< Domain Error Word 0, array offset: 0x400, array step: 0x10 */ 98 __I uint32_t DERR_W1; /**< Domain Error Word 1, array offset: 0x404, array step: 0x10 */ 99 uint8_t RESERVED_0[4]; 100 __O uint32_t DERR_W3; /**< Domain Error Word 3, array offset: 0x40C, array step: 0x10 */ 101 } DERRW0[XRDC_DERRW0_COUNT]; 102 uint8_t RESERVED_5[464]; 103 __IO uint32_t PID[XRDC_PID_COUNT]; /**< Process Identifier, array offset: 0x700, array step: 0x4 */ 104 uint8_t RESERVED_6[240]; 105 __IO uint32_t MDA_W0_0_DFMT0; /**< Master Domain Assignment, offset: 0x800 */ 106 uint8_t RESERVED_7[28]; 107 __IO uint32_t MDA_W0_1_DFMT1; /**< Master Domain Assignment, offset: 0x820 */ 108 uint8_t RESERVED_8[28]; 109 __IO uint32_t MDA_W0_2_DFMT1; /**< Master Domain Assignment, offset: 0x840 */ 110 uint8_t RESERVED_9[28]; 111 __IO uint32_t MDA_W0_3_DFMT0; /**< Master Domain Assignment, offset: 0x860 */ 112 uint8_t RESERVED_10[60]; 113 __IO uint32_t MDA_W0_5_DFMT1; /**< Master Domain Assignment, offset: 0x8A0 */ 114 uint8_t RESERVED_11[1884]; 115 struct { /* offset: 0x1000, array step: 0x400 */ 116 struct { /* offset: 0x1000, array step: index*0x400, index2*0x8 */ 117 __IO uint32_t PDAC_W0; /**< Peripheral Domain Access Control Word 0, array offset: 0x1000, array step: index*0x400, index2*0x8 */ 118 __IO uint32_t PDAC_W1; /**< Peripheral Domain Access Control Word 1, array offset: 0x1004, array step: index*0x400, index2*0x8 */ 119 } PDACN[XRDC_PDAC_SLOT_PDACN_COUNT]; 120 uint8_t RESERVED_0[152]; 121 } PDAC_SLOT[XRDC_PDAC_SLOT_COUNT]; 122 uint8_t RESERVED_12[1024]; 123 struct { /* offset: 0x2000, array step: index*0x200, index2*0x20 */ 124 __IO uint32_t XRDC_MRGD_W0; /**< Memory Region Descriptor Word 0, array offset: 0x2000, array step: index*0x200, index2*0x20 */ 125 __IO uint32_t XRDC_MRGD_W1; /**< Memory Region Descriptor Word 1, array offset: 0x2004, array step: index*0x200, index2*0x20 */ 126 __IO uint32_t XRDC_MRGD_W2; /**< Memory Region Descriptor Word 2, array offset: 0x2008, array step: index*0x200, index2*0x20 */ 127 __IO uint32_t XRDC_MRGD_W3; /**< Memory Region Descriptor Word 3, array offset: 0x200C, array step: index*0x200, index2*0x20 */ 128 uint8_t RESERVED_0[16]; 129 } MRGDN[XRDC_MRCN_COUNT][XRDC_MRCN_MRGDN_COUNT]; 130 } XRDC_Type, *XRDC_MemMapPtr; 131 132 /** Number of instances of the XRDC module. */ 133 #define XRDC_INSTANCE_COUNT (1u) 134 135 /* XRDC - Peripheral instance base addresses */ 136 /** Peripheral XRDC base address */ 137 #define IP_XRDC_BASE (0x40278000u) 138 /** Peripheral XRDC base pointer */ 139 #define IP_XRDC ((XRDC_Type *)IP_XRDC_BASE) 140 /** Array initializer of XRDC peripheral base addresses */ 141 #define IP_XRDC_BASE_ADDRS { IP_XRDC_BASE } 142 /** Array initializer of XRDC peripheral base pointers */ 143 #define IP_XRDC_BASE_PTRS { IP_XRDC } 144 145 /* ---------------------------------------------------------------------------- 146 -- XRDC Register Masks 147 ---------------------------------------------------------------------------- */ 148 149 /*! 150 * @addtogroup XRDC_Register_Masks XRDC Register Masks 151 * @{ 152 */ 153 154 /*! @name CR - Control */ 155 /*! @{ */ 156 157 #define XRDC_CR_GVLD_MASK (0x1U) 158 #define XRDC_CR_GVLD_SHIFT (0U) 159 #define XRDC_CR_GVLD_WIDTH (1U) 160 #define XRDC_CR_GVLD(x) (((uint32_t)(((uint32_t)(x)) << XRDC_CR_GVLD_SHIFT)) & XRDC_CR_GVLD_MASK) 161 162 #define XRDC_CR_HRL_MASK (0x1EU) 163 #define XRDC_CR_HRL_SHIFT (1U) 164 #define XRDC_CR_HRL_WIDTH (4U) 165 #define XRDC_CR_HRL(x) (((uint32_t)(((uint32_t)(x)) << XRDC_CR_HRL_SHIFT)) & XRDC_CR_HRL_MASK) 166 167 #define XRDC_CR_MRF_MASK (0x80U) 168 #define XRDC_CR_MRF_SHIFT (7U) 169 #define XRDC_CR_MRF_WIDTH (1U) 170 #define XRDC_CR_MRF(x) (((uint32_t)(((uint32_t)(x)) << XRDC_CR_MRF_SHIFT)) & XRDC_CR_MRF_MASK) 171 172 #define XRDC_CR_VAW_MASK (0x100U) 173 #define XRDC_CR_VAW_SHIFT (8U) 174 #define XRDC_CR_VAW_WIDTH (1U) 175 #define XRDC_CR_VAW(x) (((uint32_t)(((uint32_t)(x)) << XRDC_CR_VAW_SHIFT)) & XRDC_CR_VAW_MASK) 176 177 #define XRDC_CR_LK1_MASK (0x40000000U) 178 #define XRDC_CR_LK1_SHIFT (30U) 179 #define XRDC_CR_LK1_WIDTH (1U) 180 #define XRDC_CR_LK1(x) (((uint32_t)(((uint32_t)(x)) << XRDC_CR_LK1_SHIFT)) & XRDC_CR_LK1_MASK) 181 /*! @} */ 182 183 /*! @name HWCFG0 - Hardware Configuration 0 */ 184 /*! @{ */ 185 186 #define XRDC_HWCFG0_NDID_MASK (0xFFU) 187 #define XRDC_HWCFG0_NDID_SHIFT (0U) 188 #define XRDC_HWCFG0_NDID_WIDTH (8U) 189 #define XRDC_HWCFG0_NDID(x) (((uint32_t)(((uint32_t)(x)) << XRDC_HWCFG0_NDID_SHIFT)) & XRDC_HWCFG0_NDID_MASK) 190 191 #define XRDC_HWCFG0_NMSTR_MASK (0xFF00U) 192 #define XRDC_HWCFG0_NMSTR_SHIFT (8U) 193 #define XRDC_HWCFG0_NMSTR_WIDTH (8U) 194 #define XRDC_HWCFG0_NMSTR(x) (((uint32_t)(((uint32_t)(x)) << XRDC_HWCFG0_NMSTR_SHIFT)) & XRDC_HWCFG0_NMSTR_MASK) 195 196 #define XRDC_HWCFG0_NMRC_MASK (0xFF0000U) 197 #define XRDC_HWCFG0_NMRC_SHIFT (16U) 198 #define XRDC_HWCFG0_NMRC_WIDTH (8U) 199 #define XRDC_HWCFG0_NMRC(x) (((uint32_t)(((uint32_t)(x)) << XRDC_HWCFG0_NMRC_SHIFT)) & XRDC_HWCFG0_NMRC_MASK) 200 201 #define XRDC_HWCFG0_NPAC_MASK (0xF000000U) 202 #define XRDC_HWCFG0_NPAC_SHIFT (24U) 203 #define XRDC_HWCFG0_NPAC_WIDTH (4U) 204 #define XRDC_HWCFG0_NPAC(x) (((uint32_t)(((uint32_t)(x)) << XRDC_HWCFG0_NPAC_SHIFT)) & XRDC_HWCFG0_NPAC_MASK) 205 206 #define XRDC_HWCFG0_MID_MASK (0xF0000000U) 207 #define XRDC_HWCFG0_MID_SHIFT (28U) 208 #define XRDC_HWCFG0_MID_WIDTH (4U) 209 #define XRDC_HWCFG0_MID(x) (((uint32_t)(((uint32_t)(x)) << XRDC_HWCFG0_MID_SHIFT)) & XRDC_HWCFG0_MID_MASK) 210 /*! @} */ 211 212 /*! @name HWCFG1 - Hardware Configuration 1 */ 213 /*! @{ */ 214 215 #define XRDC_HWCFG1_DID_MASK (0xFU) 216 #define XRDC_HWCFG1_DID_SHIFT (0U) 217 #define XRDC_HWCFG1_DID_WIDTH (4U) 218 #define XRDC_HWCFG1_DID(x) (((uint32_t)(((uint32_t)(x)) << XRDC_HWCFG1_DID_SHIFT)) & XRDC_HWCFG1_DID_MASK) 219 /*! @} */ 220 221 /*! @name HWCFG2 - Hardware Configuration 2 */ 222 /*! @{ */ 223 224 #define XRDC_HWCFG2_PIDP0_MASK (0x1U) 225 #define XRDC_HWCFG2_PIDP0_SHIFT (0U) 226 #define XRDC_HWCFG2_PIDP0_WIDTH (1U) 227 #define XRDC_HWCFG2_PIDP0(x) (((uint32_t)(((uint32_t)(x)) << XRDC_HWCFG2_PIDP0_SHIFT)) & XRDC_HWCFG2_PIDP0_MASK) 228 229 #define XRDC_HWCFG2_PIDP1_MASK (0x2U) 230 #define XRDC_HWCFG2_PIDP1_SHIFT (1U) 231 #define XRDC_HWCFG2_PIDP1_WIDTH (1U) 232 #define XRDC_HWCFG2_PIDP1(x) (((uint32_t)(((uint32_t)(x)) << XRDC_HWCFG2_PIDP1_SHIFT)) & XRDC_HWCFG2_PIDP1_MASK) 233 234 #define XRDC_HWCFG2_PIDP2_MASK (0x4U) 235 #define XRDC_HWCFG2_PIDP2_SHIFT (2U) 236 #define XRDC_HWCFG2_PIDP2_WIDTH (1U) 237 #define XRDC_HWCFG2_PIDP2(x) (((uint32_t)(((uint32_t)(x)) << XRDC_HWCFG2_PIDP2_SHIFT)) & XRDC_HWCFG2_PIDP2_MASK) 238 239 #define XRDC_HWCFG2_PIDP3_MASK (0x8U) 240 #define XRDC_HWCFG2_PIDP3_SHIFT (3U) 241 #define XRDC_HWCFG2_PIDP3_WIDTH (1U) 242 #define XRDC_HWCFG2_PIDP3(x) (((uint32_t)(((uint32_t)(x)) << XRDC_HWCFG2_PIDP3_SHIFT)) & XRDC_HWCFG2_PIDP3_MASK) 243 244 #define XRDC_HWCFG2_PIDP4_MASK (0x10U) 245 #define XRDC_HWCFG2_PIDP4_SHIFT (4U) 246 #define XRDC_HWCFG2_PIDP4_WIDTH (1U) 247 #define XRDC_HWCFG2_PIDP4(x) (((uint32_t)(((uint32_t)(x)) << XRDC_HWCFG2_PIDP4_SHIFT)) & XRDC_HWCFG2_PIDP4_MASK) 248 249 #define XRDC_HWCFG2_PIDP5_MASK (0x20U) 250 #define XRDC_HWCFG2_PIDP5_SHIFT (5U) 251 #define XRDC_HWCFG2_PIDP5_WIDTH (1U) 252 #define XRDC_HWCFG2_PIDP5(x) (((uint32_t)(((uint32_t)(x)) << XRDC_HWCFG2_PIDP5_SHIFT)) & XRDC_HWCFG2_PIDP5_MASK) 253 254 #define XRDC_HWCFG2_PIDP6_MASK (0x40U) 255 #define XRDC_HWCFG2_PIDP6_SHIFT (6U) 256 #define XRDC_HWCFG2_PIDP6_WIDTH (1U) 257 #define XRDC_HWCFG2_PIDP6(x) (((uint32_t)(((uint32_t)(x)) << XRDC_HWCFG2_PIDP6_SHIFT)) & XRDC_HWCFG2_PIDP6_MASK) 258 259 #define XRDC_HWCFG2_PIDP7_MASK (0x80U) 260 #define XRDC_HWCFG2_PIDP7_SHIFT (7U) 261 #define XRDC_HWCFG2_PIDP7_WIDTH (1U) 262 #define XRDC_HWCFG2_PIDP7(x) (((uint32_t)(((uint32_t)(x)) << XRDC_HWCFG2_PIDP7_SHIFT)) & XRDC_HWCFG2_PIDP7_MASK) 263 264 #define XRDC_HWCFG2_PIDP8_MASK (0x100U) 265 #define XRDC_HWCFG2_PIDP8_SHIFT (8U) 266 #define XRDC_HWCFG2_PIDP8_WIDTH (1U) 267 #define XRDC_HWCFG2_PIDP8(x) (((uint32_t)(((uint32_t)(x)) << XRDC_HWCFG2_PIDP8_SHIFT)) & XRDC_HWCFG2_PIDP8_MASK) 268 269 #define XRDC_HWCFG2_PIDP9_MASK (0x200U) 270 #define XRDC_HWCFG2_PIDP9_SHIFT (9U) 271 #define XRDC_HWCFG2_PIDP9_WIDTH (1U) 272 #define XRDC_HWCFG2_PIDP9(x) (((uint32_t)(((uint32_t)(x)) << XRDC_HWCFG2_PIDP9_SHIFT)) & XRDC_HWCFG2_PIDP9_MASK) 273 274 #define XRDC_HWCFG2_PIDP10_MASK (0x400U) 275 #define XRDC_HWCFG2_PIDP10_SHIFT (10U) 276 #define XRDC_HWCFG2_PIDP10_WIDTH (1U) 277 #define XRDC_HWCFG2_PIDP10(x) (((uint32_t)(((uint32_t)(x)) << XRDC_HWCFG2_PIDP10_SHIFT)) & XRDC_HWCFG2_PIDP10_MASK) 278 279 #define XRDC_HWCFG2_PIDP11_MASK (0x800U) 280 #define XRDC_HWCFG2_PIDP11_SHIFT (11U) 281 #define XRDC_HWCFG2_PIDP11_WIDTH (1U) 282 #define XRDC_HWCFG2_PIDP11(x) (((uint32_t)(((uint32_t)(x)) << XRDC_HWCFG2_PIDP11_SHIFT)) & XRDC_HWCFG2_PIDP11_MASK) 283 284 #define XRDC_HWCFG2_PIDP12_MASK (0x1000U) 285 #define XRDC_HWCFG2_PIDP12_SHIFT (12U) 286 #define XRDC_HWCFG2_PIDP12_WIDTH (1U) 287 #define XRDC_HWCFG2_PIDP12(x) (((uint32_t)(((uint32_t)(x)) << XRDC_HWCFG2_PIDP12_SHIFT)) & XRDC_HWCFG2_PIDP12_MASK) 288 289 #define XRDC_HWCFG2_PIDP13_MASK (0x2000U) 290 #define XRDC_HWCFG2_PIDP13_SHIFT (13U) 291 #define XRDC_HWCFG2_PIDP13_WIDTH (1U) 292 #define XRDC_HWCFG2_PIDP13(x) (((uint32_t)(((uint32_t)(x)) << XRDC_HWCFG2_PIDP13_SHIFT)) & XRDC_HWCFG2_PIDP13_MASK) 293 294 #define XRDC_HWCFG2_PIDP14_MASK (0x4000U) 295 #define XRDC_HWCFG2_PIDP14_SHIFT (14U) 296 #define XRDC_HWCFG2_PIDP14_WIDTH (1U) 297 #define XRDC_HWCFG2_PIDP14(x) (((uint32_t)(((uint32_t)(x)) << XRDC_HWCFG2_PIDP14_SHIFT)) & XRDC_HWCFG2_PIDP14_MASK) 298 299 #define XRDC_HWCFG2_PIDP15_MASK (0x8000U) 300 #define XRDC_HWCFG2_PIDP15_SHIFT (15U) 301 #define XRDC_HWCFG2_PIDP15_WIDTH (1U) 302 #define XRDC_HWCFG2_PIDP15(x) (((uint32_t)(((uint32_t)(x)) << XRDC_HWCFG2_PIDP15_SHIFT)) & XRDC_HWCFG2_PIDP15_MASK) 303 304 #define XRDC_HWCFG2_PIDP16_MASK (0x10000U) 305 #define XRDC_HWCFG2_PIDP16_SHIFT (16U) 306 #define XRDC_HWCFG2_PIDP16_WIDTH (1U) 307 #define XRDC_HWCFG2_PIDP16(x) (((uint32_t)(((uint32_t)(x)) << XRDC_HWCFG2_PIDP16_SHIFT)) & XRDC_HWCFG2_PIDP16_MASK) 308 309 #define XRDC_HWCFG2_PIDP17_MASK (0x20000U) 310 #define XRDC_HWCFG2_PIDP17_SHIFT (17U) 311 #define XRDC_HWCFG2_PIDP17_WIDTH (1U) 312 #define XRDC_HWCFG2_PIDP17(x) (((uint32_t)(((uint32_t)(x)) << XRDC_HWCFG2_PIDP17_SHIFT)) & XRDC_HWCFG2_PIDP17_MASK) 313 314 #define XRDC_HWCFG2_PIDP18_MASK (0x40000U) 315 #define XRDC_HWCFG2_PIDP18_SHIFT (18U) 316 #define XRDC_HWCFG2_PIDP18_WIDTH (1U) 317 #define XRDC_HWCFG2_PIDP18(x) (((uint32_t)(((uint32_t)(x)) << XRDC_HWCFG2_PIDP18_SHIFT)) & XRDC_HWCFG2_PIDP18_MASK) 318 319 #define XRDC_HWCFG2_PIDP19_MASK (0x80000U) 320 #define XRDC_HWCFG2_PIDP19_SHIFT (19U) 321 #define XRDC_HWCFG2_PIDP19_WIDTH (1U) 322 #define XRDC_HWCFG2_PIDP19(x) (((uint32_t)(((uint32_t)(x)) << XRDC_HWCFG2_PIDP19_SHIFT)) & XRDC_HWCFG2_PIDP19_MASK) 323 324 #define XRDC_HWCFG2_PIDP20_MASK (0x100000U) 325 #define XRDC_HWCFG2_PIDP20_SHIFT (20U) 326 #define XRDC_HWCFG2_PIDP20_WIDTH (1U) 327 #define XRDC_HWCFG2_PIDP20(x) (((uint32_t)(((uint32_t)(x)) << XRDC_HWCFG2_PIDP20_SHIFT)) & XRDC_HWCFG2_PIDP20_MASK) 328 329 #define XRDC_HWCFG2_PIDP21_MASK (0x200000U) 330 #define XRDC_HWCFG2_PIDP21_SHIFT (21U) 331 #define XRDC_HWCFG2_PIDP21_WIDTH (1U) 332 #define XRDC_HWCFG2_PIDP21(x) (((uint32_t)(((uint32_t)(x)) << XRDC_HWCFG2_PIDP21_SHIFT)) & XRDC_HWCFG2_PIDP21_MASK) 333 334 #define XRDC_HWCFG2_PIDP22_MASK (0x400000U) 335 #define XRDC_HWCFG2_PIDP22_SHIFT (22U) 336 #define XRDC_HWCFG2_PIDP22_WIDTH (1U) 337 #define XRDC_HWCFG2_PIDP22(x) (((uint32_t)(((uint32_t)(x)) << XRDC_HWCFG2_PIDP22_SHIFT)) & XRDC_HWCFG2_PIDP22_MASK) 338 339 #define XRDC_HWCFG2_PIDP23_MASK (0x800000U) 340 #define XRDC_HWCFG2_PIDP23_SHIFT (23U) 341 #define XRDC_HWCFG2_PIDP23_WIDTH (1U) 342 #define XRDC_HWCFG2_PIDP23(x) (((uint32_t)(((uint32_t)(x)) << XRDC_HWCFG2_PIDP23_SHIFT)) & XRDC_HWCFG2_PIDP23_MASK) 343 344 #define XRDC_HWCFG2_PIDP24_MASK (0x1000000U) 345 #define XRDC_HWCFG2_PIDP24_SHIFT (24U) 346 #define XRDC_HWCFG2_PIDP24_WIDTH (1U) 347 #define XRDC_HWCFG2_PIDP24(x) (((uint32_t)(((uint32_t)(x)) << XRDC_HWCFG2_PIDP24_SHIFT)) & XRDC_HWCFG2_PIDP24_MASK) 348 349 #define XRDC_HWCFG2_PIDP25_MASK (0x2000000U) 350 #define XRDC_HWCFG2_PIDP25_SHIFT (25U) 351 #define XRDC_HWCFG2_PIDP25_WIDTH (1U) 352 #define XRDC_HWCFG2_PIDP25(x) (((uint32_t)(((uint32_t)(x)) << XRDC_HWCFG2_PIDP25_SHIFT)) & XRDC_HWCFG2_PIDP25_MASK) 353 354 #define XRDC_HWCFG2_PIDP26_MASK (0x4000000U) 355 #define XRDC_HWCFG2_PIDP26_SHIFT (26U) 356 #define XRDC_HWCFG2_PIDP26_WIDTH (1U) 357 #define XRDC_HWCFG2_PIDP26(x) (((uint32_t)(((uint32_t)(x)) << XRDC_HWCFG2_PIDP26_SHIFT)) & XRDC_HWCFG2_PIDP26_MASK) 358 359 #define XRDC_HWCFG2_PIDP27_MASK (0x8000000U) 360 #define XRDC_HWCFG2_PIDP27_SHIFT (27U) 361 #define XRDC_HWCFG2_PIDP27_WIDTH (1U) 362 #define XRDC_HWCFG2_PIDP27(x) (((uint32_t)(((uint32_t)(x)) << XRDC_HWCFG2_PIDP27_SHIFT)) & XRDC_HWCFG2_PIDP27_MASK) 363 364 #define XRDC_HWCFG2_PIDP28_MASK (0x10000000U) 365 #define XRDC_HWCFG2_PIDP28_SHIFT (28U) 366 #define XRDC_HWCFG2_PIDP28_WIDTH (1U) 367 #define XRDC_HWCFG2_PIDP28(x) (((uint32_t)(((uint32_t)(x)) << XRDC_HWCFG2_PIDP28_SHIFT)) & XRDC_HWCFG2_PIDP28_MASK) 368 369 #define XRDC_HWCFG2_PIDP29_MASK (0x20000000U) 370 #define XRDC_HWCFG2_PIDP29_SHIFT (29U) 371 #define XRDC_HWCFG2_PIDP29_WIDTH (1U) 372 #define XRDC_HWCFG2_PIDP29(x) (((uint32_t)(((uint32_t)(x)) << XRDC_HWCFG2_PIDP29_SHIFT)) & XRDC_HWCFG2_PIDP29_MASK) 373 374 #define XRDC_HWCFG2_PIDP30_MASK (0x40000000U) 375 #define XRDC_HWCFG2_PIDP30_SHIFT (30U) 376 #define XRDC_HWCFG2_PIDP30_WIDTH (1U) 377 #define XRDC_HWCFG2_PIDP30(x) (((uint32_t)(((uint32_t)(x)) << XRDC_HWCFG2_PIDP30_SHIFT)) & XRDC_HWCFG2_PIDP30_MASK) 378 379 #define XRDC_HWCFG2_PIDP31_MASK (0x80000000U) 380 #define XRDC_HWCFG2_PIDP31_SHIFT (31U) 381 #define XRDC_HWCFG2_PIDP31_WIDTH (1U) 382 #define XRDC_HWCFG2_PIDP31(x) (((uint32_t)(((uint32_t)(x)) << XRDC_HWCFG2_PIDP31_SHIFT)) & XRDC_HWCFG2_PIDP31_MASK) 383 /*! @} */ 384 385 /*! @name MDACFG - Master Domain Assignment Configuration */ 386 /*! @{ */ 387 388 #define XRDC_MDACFG_NMDAR_MASK (0xFU) 389 #define XRDC_MDACFG_NMDAR_SHIFT (0U) 390 #define XRDC_MDACFG_NMDAR_WIDTH (4U) 391 #define XRDC_MDACFG_NMDAR(x) (((uint8_t)(((uint8_t)(x)) << XRDC_MDACFG_NMDAR_SHIFT)) & XRDC_MDACFG_NMDAR_MASK) 392 393 #define XRDC_MDACFG_NCM_MASK (0x80U) 394 #define XRDC_MDACFG_NCM_SHIFT (7U) 395 #define XRDC_MDACFG_NCM_WIDTH (1U) 396 #define XRDC_MDACFG_NCM(x) (((uint8_t)(((uint8_t)(x)) << XRDC_MDACFG_NCM_SHIFT)) & XRDC_MDACFG_NCM_MASK) 397 /*! @} */ 398 399 /*! @name MRCFG - Memory Region Configuration */ 400 /*! @{ */ 401 402 #define XRDC_MRCFG_NMRGD_MASK (0x1FU) 403 #define XRDC_MRCFG_NMRGD_SHIFT (0U) 404 #define XRDC_MRCFG_NMRGD_WIDTH (5U) 405 #define XRDC_MRCFG_NMRGD(x) (((uint8_t)(((uint8_t)(x)) << XRDC_MRCFG_NMRGD_SHIFT)) & XRDC_MRCFG_NMRGD_MASK) 406 /*! @} */ 407 408 /*! @name DERRLOC - Domain Error Location */ 409 /*! @{ */ 410 411 #define XRDC_DERRLOC_MRCINST_MASK (0xFFFFU) 412 #define XRDC_DERRLOC_MRCINST_SHIFT (0U) 413 #define XRDC_DERRLOC_MRCINST_WIDTH (16U) 414 #define XRDC_DERRLOC_MRCINST(x) (((uint32_t)(((uint32_t)(x)) << XRDC_DERRLOC_MRCINST_SHIFT)) & XRDC_DERRLOC_MRCINST_MASK) 415 416 #define XRDC_DERRLOC_PACINST_MASK (0xF0000U) 417 #define XRDC_DERRLOC_PACINST_SHIFT (16U) 418 #define XRDC_DERRLOC_PACINST_WIDTH (4U) 419 #define XRDC_DERRLOC_PACINST(x) (((uint32_t)(((uint32_t)(x)) << XRDC_DERRLOC_PACINST_SHIFT)) & XRDC_DERRLOC_PACINST_MASK) 420 /*! @} */ 421 422 /*! @name DERR_W0 - Domain Error Word 0 */ 423 /*! @{ */ 424 425 #define XRDC_DERR_W0_EADDR_MASK (0xFFFFFFFFU) 426 #define XRDC_DERR_W0_EADDR_SHIFT (0U) 427 #define XRDC_DERR_W0_EADDR_WIDTH (32U) 428 #define XRDC_DERR_W0_EADDR(x) (((uint32_t)(((uint32_t)(x)) << XRDC_DERR_W0_EADDR_SHIFT)) & XRDC_DERR_W0_EADDR_MASK) 429 /*! @} */ 430 431 /*! @name DERR_W1 - Domain Error Word 1 */ 432 /*! @{ */ 433 434 #define XRDC_DERR_W1_EDID_MASK (0xFU) 435 #define XRDC_DERR_W1_EDID_SHIFT (0U) 436 #define XRDC_DERR_W1_EDID_WIDTH (4U) 437 #define XRDC_DERR_W1_EDID(x) (((uint32_t)(((uint32_t)(x)) << XRDC_DERR_W1_EDID_SHIFT)) & XRDC_DERR_W1_EDID_MASK) 438 439 #define XRDC_DERR_W1_EATR_MASK (0x700U) 440 #define XRDC_DERR_W1_EATR_SHIFT (8U) 441 #define XRDC_DERR_W1_EATR_WIDTH (3U) 442 #define XRDC_DERR_W1_EATR(x) (((uint32_t)(((uint32_t)(x)) << XRDC_DERR_W1_EATR_SHIFT)) & XRDC_DERR_W1_EATR_MASK) 443 444 #define XRDC_DERR_W1_ERW_MASK (0x800U) 445 #define XRDC_DERR_W1_ERW_SHIFT (11U) 446 #define XRDC_DERR_W1_ERW_WIDTH (1U) 447 #define XRDC_DERR_W1_ERW(x) (((uint32_t)(((uint32_t)(x)) << XRDC_DERR_W1_ERW_SHIFT)) & XRDC_DERR_W1_ERW_MASK) 448 449 #define XRDC_DERR_W1_EPORT_MASK (0x7000000U) 450 #define XRDC_DERR_W1_EPORT_SHIFT (24U) 451 #define XRDC_DERR_W1_EPORT_WIDTH (3U) 452 #define XRDC_DERR_W1_EPORT(x) (((uint32_t)(((uint32_t)(x)) << XRDC_DERR_W1_EPORT_SHIFT)) & XRDC_DERR_W1_EPORT_MASK) 453 454 #define XRDC_DERR_W1_EST_MASK (0xC0000000U) 455 #define XRDC_DERR_W1_EST_SHIFT (30U) 456 #define XRDC_DERR_W1_EST_WIDTH (2U) 457 #define XRDC_DERR_W1_EST(x) (((uint32_t)(((uint32_t)(x)) << XRDC_DERR_W1_EST_SHIFT)) & XRDC_DERR_W1_EST_MASK) 458 /*! @} */ 459 460 /*! @name DERR_W3 - Domain Error Word 3 */ 461 /*! @{ */ 462 463 #define XRDC_DERR_W3_RECR_MASK (0xC0000000U) 464 #define XRDC_DERR_W3_RECR_SHIFT (30U) 465 #define XRDC_DERR_W3_RECR_WIDTH (2U) 466 #define XRDC_DERR_W3_RECR(x) (((uint32_t)(((uint32_t)(x)) << XRDC_DERR_W3_RECR_SHIFT)) & XRDC_DERR_W3_RECR_MASK) 467 /*! @} */ 468 469 /*! @name PID - Process Identifier */ 470 /*! @{ */ 471 472 #define XRDC_PID_PID_MASK (0x3FU) 473 #define XRDC_PID_PID_SHIFT (0U) 474 #define XRDC_PID_PID_WIDTH (6U) 475 #define XRDC_PID_PID(x) (((uint32_t)(((uint32_t)(x)) << XRDC_PID_PID_SHIFT)) & XRDC_PID_PID_MASK) 476 477 #define XRDC_PID_TSM_MASK (0x10000000U) 478 #define XRDC_PID_TSM_SHIFT (28U) 479 #define XRDC_PID_TSM_WIDTH (1U) 480 #define XRDC_PID_TSM(x) (((uint32_t)(((uint32_t)(x)) << XRDC_PID_TSM_SHIFT)) & XRDC_PID_TSM_MASK) 481 482 #define XRDC_PID_LK2_MASK (0x60000000U) 483 #define XRDC_PID_LK2_SHIFT (29U) 484 #define XRDC_PID_LK2_WIDTH (2U) 485 #define XRDC_PID_LK2(x) (((uint32_t)(((uint32_t)(x)) << XRDC_PID_LK2_SHIFT)) & XRDC_PID_LK2_MASK) 486 /*! @} */ 487 488 /*! @name MDA_W0_0_DFMT0 - Master Domain Assignment */ 489 /*! @{ */ 490 491 #define XRDC_MDA_W0_0_DFMT0_DID_MASK (0x3U) 492 #define XRDC_MDA_W0_0_DFMT0_DID_SHIFT (0U) 493 #define XRDC_MDA_W0_0_DFMT0_DID_WIDTH (2U) 494 #define XRDC_MDA_W0_0_DFMT0_DID(x) (((uint32_t)(((uint32_t)(x)) << XRDC_MDA_W0_0_DFMT0_DID_SHIFT)) & XRDC_MDA_W0_0_DFMT0_DID_MASK) 495 496 #define XRDC_MDA_W0_0_DFMT0_DIDS_MASK (0x30U) 497 #define XRDC_MDA_W0_0_DFMT0_DIDS_SHIFT (4U) 498 #define XRDC_MDA_W0_0_DFMT0_DIDS_WIDTH (2U) 499 #define XRDC_MDA_W0_0_DFMT0_DIDS(x) (((uint32_t)(((uint32_t)(x)) << XRDC_MDA_W0_0_DFMT0_DIDS_SHIFT)) & XRDC_MDA_W0_0_DFMT0_DIDS_MASK) 500 501 #define XRDC_MDA_W0_0_DFMT0_PE_MASK (0xC0U) 502 #define XRDC_MDA_W0_0_DFMT0_PE_SHIFT (6U) 503 #define XRDC_MDA_W0_0_DFMT0_PE_WIDTH (2U) 504 #define XRDC_MDA_W0_0_DFMT0_PE(x) (((uint32_t)(((uint32_t)(x)) << XRDC_MDA_W0_0_DFMT0_PE_SHIFT)) & XRDC_MDA_W0_0_DFMT0_PE_MASK) 505 506 #define XRDC_MDA_W0_0_DFMT0_PIDM_MASK (0x3F00U) 507 #define XRDC_MDA_W0_0_DFMT0_PIDM_SHIFT (8U) 508 #define XRDC_MDA_W0_0_DFMT0_PIDM_WIDTH (6U) 509 #define XRDC_MDA_W0_0_DFMT0_PIDM(x) (((uint32_t)(((uint32_t)(x)) << XRDC_MDA_W0_0_DFMT0_PIDM_SHIFT)) & XRDC_MDA_W0_0_DFMT0_PIDM_MASK) 510 511 #define XRDC_MDA_W0_0_DFMT0_PID_MASK (0x3F0000U) 512 #define XRDC_MDA_W0_0_DFMT0_PID_SHIFT (16U) 513 #define XRDC_MDA_W0_0_DFMT0_PID_WIDTH (6U) 514 #define XRDC_MDA_W0_0_DFMT0_PID(x) (((uint32_t)(((uint32_t)(x)) << XRDC_MDA_W0_0_DFMT0_PID_SHIFT)) & XRDC_MDA_W0_0_DFMT0_PID_MASK) 515 516 #define XRDC_MDA_W0_0_DFMT0_DFMT_MASK (0x20000000U) 517 #define XRDC_MDA_W0_0_DFMT0_DFMT_SHIFT (29U) 518 #define XRDC_MDA_W0_0_DFMT0_DFMT_WIDTH (1U) 519 #define XRDC_MDA_W0_0_DFMT0_DFMT(x) (((uint32_t)(((uint32_t)(x)) << XRDC_MDA_W0_0_DFMT0_DFMT_SHIFT)) & XRDC_MDA_W0_0_DFMT0_DFMT_MASK) 520 521 #define XRDC_MDA_W0_0_DFMT0_LK1_MASK (0x40000000U) 522 #define XRDC_MDA_W0_0_DFMT0_LK1_SHIFT (30U) 523 #define XRDC_MDA_W0_0_DFMT0_LK1_WIDTH (1U) 524 #define XRDC_MDA_W0_0_DFMT0_LK1(x) (((uint32_t)(((uint32_t)(x)) << XRDC_MDA_W0_0_DFMT0_LK1_SHIFT)) & XRDC_MDA_W0_0_DFMT0_LK1_MASK) 525 526 #define XRDC_MDA_W0_0_DFMT0_VLD_MASK (0x80000000U) 527 #define XRDC_MDA_W0_0_DFMT0_VLD_SHIFT (31U) 528 #define XRDC_MDA_W0_0_DFMT0_VLD_WIDTH (1U) 529 #define XRDC_MDA_W0_0_DFMT0_VLD(x) (((uint32_t)(((uint32_t)(x)) << XRDC_MDA_W0_0_DFMT0_VLD_SHIFT)) & XRDC_MDA_W0_0_DFMT0_VLD_MASK) 530 /*! @} */ 531 532 /*! @name MDA_W0_1_DFMT1 - Master Domain Assignment */ 533 /*! @{ */ 534 535 #define XRDC_MDA_W0_1_DFMT1_DID_MASK (0x3U) 536 #define XRDC_MDA_W0_1_DFMT1_DID_SHIFT (0U) 537 #define XRDC_MDA_W0_1_DFMT1_DID_WIDTH (2U) 538 #define XRDC_MDA_W0_1_DFMT1_DID(x) (((uint32_t)(((uint32_t)(x)) << XRDC_MDA_W0_1_DFMT1_DID_SHIFT)) & XRDC_MDA_W0_1_DFMT1_DID_MASK) 539 540 #define XRDC_MDA_W0_1_DFMT1_PA_MASK (0x30U) 541 #define XRDC_MDA_W0_1_DFMT1_PA_SHIFT (4U) 542 #define XRDC_MDA_W0_1_DFMT1_PA_WIDTH (2U) 543 #define XRDC_MDA_W0_1_DFMT1_PA(x) (((uint32_t)(((uint32_t)(x)) << XRDC_MDA_W0_1_DFMT1_PA_SHIFT)) & XRDC_MDA_W0_1_DFMT1_PA_MASK) 544 545 #define XRDC_MDA_W0_1_DFMT1_SA_MASK (0xC0U) 546 #define XRDC_MDA_W0_1_DFMT1_SA_SHIFT (6U) 547 #define XRDC_MDA_W0_1_DFMT1_SA_WIDTH (2U) 548 #define XRDC_MDA_W0_1_DFMT1_SA(x) (((uint32_t)(((uint32_t)(x)) << XRDC_MDA_W0_1_DFMT1_SA_SHIFT)) & XRDC_MDA_W0_1_DFMT1_SA_MASK) 549 550 #define XRDC_MDA_W0_1_DFMT1_DIDB_MASK (0x100U) 551 #define XRDC_MDA_W0_1_DFMT1_DIDB_SHIFT (8U) 552 #define XRDC_MDA_W0_1_DFMT1_DIDB_WIDTH (1U) 553 #define XRDC_MDA_W0_1_DFMT1_DIDB(x) (((uint32_t)(((uint32_t)(x)) << XRDC_MDA_W0_1_DFMT1_DIDB_SHIFT)) & XRDC_MDA_W0_1_DFMT1_DIDB_MASK) 554 555 #define XRDC_MDA_W0_1_DFMT1_DFMT_MASK (0x20000000U) 556 #define XRDC_MDA_W0_1_DFMT1_DFMT_SHIFT (29U) 557 #define XRDC_MDA_W0_1_DFMT1_DFMT_WIDTH (1U) 558 #define XRDC_MDA_W0_1_DFMT1_DFMT(x) (((uint32_t)(((uint32_t)(x)) << XRDC_MDA_W0_1_DFMT1_DFMT_SHIFT)) & XRDC_MDA_W0_1_DFMT1_DFMT_MASK) 559 560 #define XRDC_MDA_W0_1_DFMT1_LK1_MASK (0x40000000U) 561 #define XRDC_MDA_W0_1_DFMT1_LK1_SHIFT (30U) 562 #define XRDC_MDA_W0_1_DFMT1_LK1_WIDTH (1U) 563 #define XRDC_MDA_W0_1_DFMT1_LK1(x) (((uint32_t)(((uint32_t)(x)) << XRDC_MDA_W0_1_DFMT1_LK1_SHIFT)) & XRDC_MDA_W0_1_DFMT1_LK1_MASK) 564 565 #define XRDC_MDA_W0_1_DFMT1_VLD_MASK (0x80000000U) 566 #define XRDC_MDA_W0_1_DFMT1_VLD_SHIFT (31U) 567 #define XRDC_MDA_W0_1_DFMT1_VLD_WIDTH (1U) 568 #define XRDC_MDA_W0_1_DFMT1_VLD(x) (((uint32_t)(((uint32_t)(x)) << XRDC_MDA_W0_1_DFMT1_VLD_SHIFT)) & XRDC_MDA_W0_1_DFMT1_VLD_MASK) 569 /*! @} */ 570 571 /*! @name MDA_W0_2_DFMT1 - Master Domain Assignment */ 572 /*! @{ */ 573 574 #define XRDC_MDA_W0_2_DFMT1_DID_MASK (0x3U) 575 #define XRDC_MDA_W0_2_DFMT1_DID_SHIFT (0U) 576 #define XRDC_MDA_W0_2_DFMT1_DID_WIDTH (2U) 577 #define XRDC_MDA_W0_2_DFMT1_DID(x) (((uint32_t)(((uint32_t)(x)) << XRDC_MDA_W0_2_DFMT1_DID_SHIFT)) & XRDC_MDA_W0_2_DFMT1_DID_MASK) 578 579 #define XRDC_MDA_W0_2_DFMT1_PA_MASK (0x30U) 580 #define XRDC_MDA_W0_2_DFMT1_PA_SHIFT (4U) 581 #define XRDC_MDA_W0_2_DFMT1_PA_WIDTH (2U) 582 #define XRDC_MDA_W0_2_DFMT1_PA(x) (((uint32_t)(((uint32_t)(x)) << XRDC_MDA_W0_2_DFMT1_PA_SHIFT)) & XRDC_MDA_W0_2_DFMT1_PA_MASK) 583 584 #define XRDC_MDA_W0_2_DFMT1_SA_MASK (0xC0U) 585 #define XRDC_MDA_W0_2_DFMT1_SA_SHIFT (6U) 586 #define XRDC_MDA_W0_2_DFMT1_SA_WIDTH (2U) 587 #define XRDC_MDA_W0_2_DFMT1_SA(x) (((uint32_t)(((uint32_t)(x)) << XRDC_MDA_W0_2_DFMT1_SA_SHIFT)) & XRDC_MDA_W0_2_DFMT1_SA_MASK) 588 589 #define XRDC_MDA_W0_2_DFMT1_DIDB_MASK (0x100U) 590 #define XRDC_MDA_W0_2_DFMT1_DIDB_SHIFT (8U) 591 #define XRDC_MDA_W0_2_DFMT1_DIDB_WIDTH (1U) 592 #define XRDC_MDA_W0_2_DFMT1_DIDB(x) (((uint32_t)(((uint32_t)(x)) << XRDC_MDA_W0_2_DFMT1_DIDB_SHIFT)) & XRDC_MDA_W0_2_DFMT1_DIDB_MASK) 593 594 #define XRDC_MDA_W0_2_DFMT1_DFMT_MASK (0x20000000U) 595 #define XRDC_MDA_W0_2_DFMT1_DFMT_SHIFT (29U) 596 #define XRDC_MDA_W0_2_DFMT1_DFMT_WIDTH (1U) 597 #define XRDC_MDA_W0_2_DFMT1_DFMT(x) (((uint32_t)(((uint32_t)(x)) << XRDC_MDA_W0_2_DFMT1_DFMT_SHIFT)) & XRDC_MDA_W0_2_DFMT1_DFMT_MASK) 598 599 #define XRDC_MDA_W0_2_DFMT1_LK1_MASK (0x40000000U) 600 #define XRDC_MDA_W0_2_DFMT1_LK1_SHIFT (30U) 601 #define XRDC_MDA_W0_2_DFMT1_LK1_WIDTH (1U) 602 #define XRDC_MDA_W0_2_DFMT1_LK1(x) (((uint32_t)(((uint32_t)(x)) << XRDC_MDA_W0_2_DFMT1_LK1_SHIFT)) & XRDC_MDA_W0_2_DFMT1_LK1_MASK) 603 604 #define XRDC_MDA_W0_2_DFMT1_VLD_MASK (0x80000000U) 605 #define XRDC_MDA_W0_2_DFMT1_VLD_SHIFT (31U) 606 #define XRDC_MDA_W0_2_DFMT1_VLD_WIDTH (1U) 607 #define XRDC_MDA_W0_2_DFMT1_VLD(x) (((uint32_t)(((uint32_t)(x)) << XRDC_MDA_W0_2_DFMT1_VLD_SHIFT)) & XRDC_MDA_W0_2_DFMT1_VLD_MASK) 608 /*! @} */ 609 610 /*! @name MDA_W0_3_DFMT0 - Master Domain Assignment */ 611 /*! @{ */ 612 613 #define XRDC_MDA_W0_3_DFMT0_DID_MASK (0x3U) 614 #define XRDC_MDA_W0_3_DFMT0_DID_SHIFT (0U) 615 #define XRDC_MDA_W0_3_DFMT0_DID_WIDTH (2U) 616 #define XRDC_MDA_W0_3_DFMT0_DID(x) (((uint32_t)(((uint32_t)(x)) << XRDC_MDA_W0_3_DFMT0_DID_SHIFT)) & XRDC_MDA_W0_3_DFMT0_DID_MASK) 617 618 #define XRDC_MDA_W0_3_DFMT0_DIDS_MASK (0x30U) 619 #define XRDC_MDA_W0_3_DFMT0_DIDS_SHIFT (4U) 620 #define XRDC_MDA_W0_3_DFMT0_DIDS_WIDTH (2U) 621 #define XRDC_MDA_W0_3_DFMT0_DIDS(x) (((uint32_t)(((uint32_t)(x)) << XRDC_MDA_W0_3_DFMT0_DIDS_SHIFT)) & XRDC_MDA_W0_3_DFMT0_DIDS_MASK) 622 623 #define XRDC_MDA_W0_3_DFMT0_PE_MASK (0xC0U) 624 #define XRDC_MDA_W0_3_DFMT0_PE_SHIFT (6U) 625 #define XRDC_MDA_W0_3_DFMT0_PE_WIDTH (2U) 626 #define XRDC_MDA_W0_3_DFMT0_PE(x) (((uint32_t)(((uint32_t)(x)) << XRDC_MDA_W0_3_DFMT0_PE_SHIFT)) & XRDC_MDA_W0_3_DFMT0_PE_MASK) 627 628 #define XRDC_MDA_W0_3_DFMT0_PIDM_MASK (0x3F00U) 629 #define XRDC_MDA_W0_3_DFMT0_PIDM_SHIFT (8U) 630 #define XRDC_MDA_W0_3_DFMT0_PIDM_WIDTH (6U) 631 #define XRDC_MDA_W0_3_DFMT0_PIDM(x) (((uint32_t)(((uint32_t)(x)) << XRDC_MDA_W0_3_DFMT0_PIDM_SHIFT)) & XRDC_MDA_W0_3_DFMT0_PIDM_MASK) 632 633 #define XRDC_MDA_W0_3_DFMT0_PID_MASK (0x3F0000U) 634 #define XRDC_MDA_W0_3_DFMT0_PID_SHIFT (16U) 635 #define XRDC_MDA_W0_3_DFMT0_PID_WIDTH (6U) 636 #define XRDC_MDA_W0_3_DFMT0_PID(x) (((uint32_t)(((uint32_t)(x)) << XRDC_MDA_W0_3_DFMT0_PID_SHIFT)) & XRDC_MDA_W0_3_DFMT0_PID_MASK) 637 638 #define XRDC_MDA_W0_3_DFMT0_DFMT_MASK (0x20000000U) 639 #define XRDC_MDA_W0_3_DFMT0_DFMT_SHIFT (29U) 640 #define XRDC_MDA_W0_3_DFMT0_DFMT_WIDTH (1U) 641 #define XRDC_MDA_W0_3_DFMT0_DFMT(x) (((uint32_t)(((uint32_t)(x)) << XRDC_MDA_W0_3_DFMT0_DFMT_SHIFT)) & XRDC_MDA_W0_3_DFMT0_DFMT_MASK) 642 643 #define XRDC_MDA_W0_3_DFMT0_LK1_MASK (0x40000000U) 644 #define XRDC_MDA_W0_3_DFMT0_LK1_SHIFT (30U) 645 #define XRDC_MDA_W0_3_DFMT0_LK1_WIDTH (1U) 646 #define XRDC_MDA_W0_3_DFMT0_LK1(x) (((uint32_t)(((uint32_t)(x)) << XRDC_MDA_W0_3_DFMT0_LK1_SHIFT)) & XRDC_MDA_W0_3_DFMT0_LK1_MASK) 647 648 #define XRDC_MDA_W0_3_DFMT0_VLD_MASK (0x80000000U) 649 #define XRDC_MDA_W0_3_DFMT0_VLD_SHIFT (31U) 650 #define XRDC_MDA_W0_3_DFMT0_VLD_WIDTH (1U) 651 #define XRDC_MDA_W0_3_DFMT0_VLD(x) (((uint32_t)(((uint32_t)(x)) << XRDC_MDA_W0_3_DFMT0_VLD_SHIFT)) & XRDC_MDA_W0_3_DFMT0_VLD_MASK) 652 /*! @} */ 653 654 /*! @name MDA_W0_5_DFMT1 - Master Domain Assignment */ 655 /*! @{ */ 656 657 #define XRDC_MDA_W0_5_DFMT1_DID_MASK (0x3U) 658 #define XRDC_MDA_W0_5_DFMT1_DID_SHIFT (0U) 659 #define XRDC_MDA_W0_5_DFMT1_DID_WIDTH (2U) 660 #define XRDC_MDA_W0_5_DFMT1_DID(x) (((uint32_t)(((uint32_t)(x)) << XRDC_MDA_W0_5_DFMT1_DID_SHIFT)) & XRDC_MDA_W0_5_DFMT1_DID_MASK) 661 662 #define XRDC_MDA_W0_5_DFMT1_PA_MASK (0x30U) 663 #define XRDC_MDA_W0_5_DFMT1_PA_SHIFT (4U) 664 #define XRDC_MDA_W0_5_DFMT1_PA_WIDTH (2U) 665 #define XRDC_MDA_W0_5_DFMT1_PA(x) (((uint32_t)(((uint32_t)(x)) << XRDC_MDA_W0_5_DFMT1_PA_SHIFT)) & XRDC_MDA_W0_5_DFMT1_PA_MASK) 666 667 #define XRDC_MDA_W0_5_DFMT1_SA_MASK (0xC0U) 668 #define XRDC_MDA_W0_5_DFMT1_SA_SHIFT (6U) 669 #define XRDC_MDA_W0_5_DFMT1_SA_WIDTH (2U) 670 #define XRDC_MDA_W0_5_DFMT1_SA(x) (((uint32_t)(((uint32_t)(x)) << XRDC_MDA_W0_5_DFMT1_SA_SHIFT)) & XRDC_MDA_W0_5_DFMT1_SA_MASK) 671 672 #define XRDC_MDA_W0_5_DFMT1_DIDB_MASK (0x100U) 673 #define XRDC_MDA_W0_5_DFMT1_DIDB_SHIFT (8U) 674 #define XRDC_MDA_W0_5_DFMT1_DIDB_WIDTH (1U) 675 #define XRDC_MDA_W0_5_DFMT1_DIDB(x) (((uint32_t)(((uint32_t)(x)) << XRDC_MDA_W0_5_DFMT1_DIDB_SHIFT)) & XRDC_MDA_W0_5_DFMT1_DIDB_MASK) 676 677 #define XRDC_MDA_W0_5_DFMT1_DFMT_MASK (0x20000000U) 678 #define XRDC_MDA_W0_5_DFMT1_DFMT_SHIFT (29U) 679 #define XRDC_MDA_W0_5_DFMT1_DFMT_WIDTH (1U) 680 #define XRDC_MDA_W0_5_DFMT1_DFMT(x) (((uint32_t)(((uint32_t)(x)) << XRDC_MDA_W0_5_DFMT1_DFMT_SHIFT)) & XRDC_MDA_W0_5_DFMT1_DFMT_MASK) 681 682 #define XRDC_MDA_W0_5_DFMT1_LK1_MASK (0x40000000U) 683 #define XRDC_MDA_W0_5_DFMT1_LK1_SHIFT (30U) 684 #define XRDC_MDA_W0_5_DFMT1_LK1_WIDTH (1U) 685 #define XRDC_MDA_W0_5_DFMT1_LK1(x) (((uint32_t)(((uint32_t)(x)) << XRDC_MDA_W0_5_DFMT1_LK1_SHIFT)) & XRDC_MDA_W0_5_DFMT1_LK1_MASK) 686 687 #define XRDC_MDA_W0_5_DFMT1_VLD_MASK (0x80000000U) 688 #define XRDC_MDA_W0_5_DFMT1_VLD_SHIFT (31U) 689 #define XRDC_MDA_W0_5_DFMT1_VLD_WIDTH (1U) 690 #define XRDC_MDA_W0_5_DFMT1_VLD(x) (((uint32_t)(((uint32_t)(x)) << XRDC_MDA_W0_5_DFMT1_VLD_SHIFT)) & XRDC_MDA_W0_5_DFMT1_VLD_MASK) 691 /*! @} */ 692 693 /*! @name PDAC_W0 - Peripheral Domain Access Control Word 0 */ 694 /*! @{ */ 695 696 #define XRDC_PDAC_W0_D0ACP_MASK (0x7U) 697 #define XRDC_PDAC_W0_D0ACP_SHIFT (0U) 698 #define XRDC_PDAC_W0_D0ACP_WIDTH (3U) 699 #define XRDC_PDAC_W0_D0ACP(x) (((uint32_t)(((uint32_t)(x)) << XRDC_PDAC_W0_D0ACP_SHIFT)) & XRDC_PDAC_W0_D0ACP_MASK) 700 701 #define XRDC_PDAC_W0_D1ACP_MASK (0x38U) 702 #define XRDC_PDAC_W0_D1ACP_SHIFT (3U) 703 #define XRDC_PDAC_W0_D1ACP_WIDTH (3U) 704 #define XRDC_PDAC_W0_D1ACP(x) (((uint32_t)(((uint32_t)(x)) << XRDC_PDAC_W0_D1ACP_SHIFT)) & XRDC_PDAC_W0_D1ACP_MASK) 705 706 #define XRDC_PDAC_W0_D2ACP_MASK (0x1C0U) 707 #define XRDC_PDAC_W0_D2ACP_SHIFT (6U) 708 #define XRDC_PDAC_W0_D2ACP_WIDTH (3U) 709 #define XRDC_PDAC_W0_D2ACP(x) (((uint32_t)(((uint32_t)(x)) << XRDC_PDAC_W0_D2ACP_SHIFT)) & XRDC_PDAC_W0_D2ACP_MASK) 710 711 #define XRDC_PDAC_W0_SNUM_MASK (0xF000000U) 712 #define XRDC_PDAC_W0_SNUM_SHIFT (24U) 713 #define XRDC_PDAC_W0_SNUM_WIDTH (4U) 714 #define XRDC_PDAC_W0_SNUM(x) (((uint32_t)(((uint32_t)(x)) << XRDC_PDAC_W0_SNUM_SHIFT)) & XRDC_PDAC_W0_SNUM_MASK) 715 716 #define XRDC_PDAC_W0_SE_MASK (0x40000000U) 717 #define XRDC_PDAC_W0_SE_SHIFT (30U) 718 #define XRDC_PDAC_W0_SE_WIDTH (1U) 719 #define XRDC_PDAC_W0_SE(x) (((uint32_t)(((uint32_t)(x)) << XRDC_PDAC_W0_SE_SHIFT)) & XRDC_PDAC_W0_SE_MASK) 720 /*! @} */ 721 722 /*! @name PDAC_W1 - Peripheral Domain Access Control Word 1 */ 723 /*! @{ */ 724 725 #define XRDC_PDAC_W1_LK2_MASK (0x60000000U) 726 #define XRDC_PDAC_W1_LK2_SHIFT (29U) 727 #define XRDC_PDAC_W1_LK2_WIDTH (2U) 728 #define XRDC_PDAC_W1_LK2(x) (((uint32_t)(((uint32_t)(x)) << XRDC_PDAC_W1_LK2_SHIFT)) & XRDC_PDAC_W1_LK2_MASK) 729 730 #define XRDC_PDAC_W1_VLD_MASK (0x80000000U) 731 #define XRDC_PDAC_W1_VLD_SHIFT (31U) 732 #define XRDC_PDAC_W1_VLD_WIDTH (1U) 733 #define XRDC_PDAC_W1_VLD(x) (((uint32_t)(((uint32_t)(x)) << XRDC_PDAC_W1_VLD_SHIFT)) & XRDC_PDAC_W1_VLD_MASK) 734 /*! @} */ 735 736 /*! @name XRDC_MRGD_W0 - Memory Region Descriptor Word 0 */ 737 /*! @{ */ 738 739 #define XRDC_XRDC_MRGD_W0_SRTADDR_MASK (0xFFFFFFE0U) 740 #define XRDC_XRDC_MRGD_W0_SRTADDR_SHIFT (5U) 741 #define XRDC_XRDC_MRGD_W0_SRTADDR_WIDTH (27U) 742 #define XRDC_XRDC_MRGD_W0_SRTADDR(x) (((uint32_t)(((uint32_t)(x)) << XRDC_XRDC_MRGD_W0_SRTADDR_SHIFT)) & XRDC_XRDC_MRGD_W0_SRTADDR_MASK) 743 /*! @} */ 744 745 /*! @name XRDC_MRGD_W1 - Memory Region Descriptor Word 1 */ 746 /*! @{ */ 747 748 #define XRDC_XRDC_MRGD_W1_ENDADDR_MASK (0xFFFFFFE0U) 749 #define XRDC_XRDC_MRGD_W1_ENDADDR_SHIFT (5U) 750 #define XRDC_XRDC_MRGD_W1_ENDADDR_WIDTH (27U) 751 #define XRDC_XRDC_MRGD_W1_ENDADDR(x) (((uint32_t)(((uint32_t)(x)) << XRDC_XRDC_MRGD_W1_ENDADDR_SHIFT)) & XRDC_XRDC_MRGD_W1_ENDADDR_MASK) 752 /*! @} */ 753 754 /*! @name XRDC_MRGD_W2 - Memory Region Descriptor Word 2 */ 755 /*! @{ */ 756 757 #define XRDC_XRDC_MRGD_W2_D0ACP_MASK (0x7U) 758 #define XRDC_XRDC_MRGD_W2_D0ACP_SHIFT (0U) 759 #define XRDC_XRDC_MRGD_W2_D0ACP_WIDTH (3U) 760 #define XRDC_XRDC_MRGD_W2_D0ACP(x) (((uint32_t)(((uint32_t)(x)) << XRDC_XRDC_MRGD_W2_D0ACP_SHIFT)) & XRDC_XRDC_MRGD_W2_D0ACP_MASK) 761 762 #define XRDC_XRDC_MRGD_W2_D1ACP_MASK (0x38U) 763 #define XRDC_XRDC_MRGD_W2_D1ACP_SHIFT (3U) 764 #define XRDC_XRDC_MRGD_W2_D1ACP_WIDTH (3U) 765 #define XRDC_XRDC_MRGD_W2_D1ACP(x) (((uint32_t)(((uint32_t)(x)) << XRDC_XRDC_MRGD_W2_D1ACP_SHIFT)) & XRDC_XRDC_MRGD_W2_D1ACP_MASK) 766 767 #define XRDC_XRDC_MRGD_W2_D2ACP_MASK (0x1C0U) 768 #define XRDC_XRDC_MRGD_W2_D2ACP_SHIFT (6U) 769 #define XRDC_XRDC_MRGD_W2_D2ACP_WIDTH (3U) 770 #define XRDC_XRDC_MRGD_W2_D2ACP(x) (((uint32_t)(((uint32_t)(x)) << XRDC_XRDC_MRGD_W2_D2ACP_SHIFT)) & XRDC_XRDC_MRGD_W2_D2ACP_MASK) 771 772 #define XRDC_XRDC_MRGD_W2_SNUM_MASK (0xF000000U) 773 #define XRDC_XRDC_MRGD_W2_SNUM_SHIFT (24U) 774 #define XRDC_XRDC_MRGD_W2_SNUM_WIDTH (4U) 775 #define XRDC_XRDC_MRGD_W2_SNUM(x) (((uint32_t)(((uint32_t)(x)) << XRDC_XRDC_MRGD_W2_SNUM_SHIFT)) & XRDC_XRDC_MRGD_W2_SNUM_MASK) 776 777 #define XRDC_XRDC_MRGD_W2_SE_MASK (0x40000000U) 778 #define XRDC_XRDC_MRGD_W2_SE_SHIFT (30U) 779 #define XRDC_XRDC_MRGD_W2_SE_WIDTH (1U) 780 #define XRDC_XRDC_MRGD_W2_SE(x) (((uint32_t)(((uint32_t)(x)) << XRDC_XRDC_MRGD_W2_SE_SHIFT)) & XRDC_XRDC_MRGD_W2_SE_MASK) 781 /*! @} */ 782 783 /*! @name XRDC_MRGD_W3 - Memory Region Descriptor Word 3 */ 784 /*! @{ */ 785 786 #define XRDC_XRDC_MRGD_W3_LK2_MASK (0x60000000U) 787 #define XRDC_XRDC_MRGD_W3_LK2_SHIFT (29U) 788 #define XRDC_XRDC_MRGD_W3_LK2_WIDTH (2U) 789 #define XRDC_XRDC_MRGD_W3_LK2(x) (((uint32_t)(((uint32_t)(x)) << XRDC_XRDC_MRGD_W3_LK2_SHIFT)) & XRDC_XRDC_MRGD_W3_LK2_MASK) 790 791 #define XRDC_XRDC_MRGD_W3_VLD_MASK (0x80000000U) 792 #define XRDC_XRDC_MRGD_W3_VLD_SHIFT (31U) 793 #define XRDC_XRDC_MRGD_W3_VLD_WIDTH (1U) 794 #define XRDC_XRDC_MRGD_W3_VLD(x) (((uint32_t)(((uint32_t)(x)) << XRDC_XRDC_MRGD_W3_VLD_SHIFT)) & XRDC_XRDC_MRGD_W3_VLD_MASK) 795 /*! @} */ 796 797 /*! 798 * @} 799 */ /* end of group XRDC_Register_Masks */ 800 801 /*! 802 * @} 803 */ /* end of group XRDC_Peripheral_Access_Layer */ 804 805 #endif /* #if !defined(S32K344_XRDC_H_) */ 806
