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Searched refs:WUU_PDC2_Reserved31_MASK (Results 1 – 15 of 15) sorted by relevance

/hal_nxp-latest/mcux/mcux-sdk/devices/MCXN236/
DMCXN236.h69717 #define WUU_PDC2_Reserved31_MASK (0xC0000000U) macro
69725 … (((uint32_t)(((uint32_t)(x)) << WUU_PDC2_Reserved31_SHIFT)) & WUU_PDC2_Reserved31_MASK)
/hal_nxp-latest/mcux/mcux-sdk/devices/MCXN235/
DMCXN235.h69675 #define WUU_PDC2_Reserved31_MASK (0xC0000000U) macro
69683 … (((uint32_t)(((uint32_t)(x)) << WUU_PDC2_Reserved31_SHIFT)) & WUU_PDC2_Reserved31_MASK)
/hal_nxp-latest/mcux/mcux-sdk/devices/MCXW727C/
DMCXW727C_cm33_core0.h52784 #define WUU_PDC2_Reserved31_MASK (0xC0000000U) macro
52792 … (((uint32_t)(((uint32_t)(x)) << WUU_PDC2_Reserved31_SHIFT)) & WUU_PDC2_Reserved31_MASK)
DMCXW727C_cm33_core1.h58574 #define WUU_PDC2_Reserved31_MASK (0xC0000000U) macro
58582 … (((uint32_t)(((uint32_t)(x)) << WUU_PDC2_Reserved31_SHIFT)) & WUU_PDC2_Reserved31_MASK)
/hal_nxp-latest/mcux/mcux-sdk/devices/MIMX8UD7/
DMIMX8UD7_dsp1.h140395 #define WUU_PDC2_Reserved31_MASK (0xC0000000U) macro
140403 … (((uint32_t)(((uint32_t)(x)) << WUU_PDC2_Reserved31_SHIFT)) & WUU_PDC2_Reserved31_MASK)
DMIMX8UD7_dsp0.h140289 #define WUU_PDC2_Reserved31_MASK (0xC0000000U) macro
140297 … (((uint32_t)(((uint32_t)(x)) << WUU_PDC2_Reserved31_SHIFT)) & WUU_PDC2_Reserved31_MASK)
DMIMX8UD7_cm33.h142603 #define WUU_PDC2_Reserved31_MASK (0xC0000000U) macro
142611 … (((uint32_t)(((uint32_t)(x)) << WUU_PDC2_Reserved31_SHIFT)) & WUU_PDC2_Reserved31_MASK)
/hal_nxp-latest/mcux/mcux-sdk/devices/MIMX8UD3/
DMIMX8UD3_cm33.h142603 #define WUU_PDC2_Reserved31_MASK (0xC0000000U) macro
142611 … (((uint32_t)(((uint32_t)(x)) << WUU_PDC2_Reserved31_SHIFT)) & WUU_PDC2_Reserved31_MASK)
DMIMX8UD3_dsp0.h140289 #define WUU_PDC2_Reserved31_MASK (0xC0000000U) macro
140297 … (((uint32_t)(((uint32_t)(x)) << WUU_PDC2_Reserved31_SHIFT)) & WUU_PDC2_Reserved31_MASK)
/hal_nxp-latest/mcux/mcux-sdk/devices/MIMX8UD5/
DMIMX8UD5_cm33.h140995 #define WUU_PDC2_Reserved31_MASK (0xC0000000U) macro
141003 … (((uint32_t)(((uint32_t)(x)) << WUU_PDC2_Reserved31_SHIFT)) & WUU_PDC2_Reserved31_MASK)
DMIMX8UD5_dsp0.h138702 #define WUU_PDC2_Reserved31_MASK (0xC0000000U) macro
138710 … (((uint32_t)(((uint32_t)(x)) << WUU_PDC2_Reserved31_SHIFT)) & WUU_PDC2_Reserved31_MASK)
/hal_nxp-latest/mcux/mcux-sdk/devices/MIMX8US5/
DMIMX8US5_dsp0.h138702 #define WUU_PDC2_Reserved31_MASK (0xC0000000U) macro
138710 … (((uint32_t)(((uint32_t)(x)) << WUU_PDC2_Reserved31_SHIFT)) & WUU_PDC2_Reserved31_MASK)
DMIMX8US5_cm33.h140995 #define WUU_PDC2_Reserved31_MASK (0xC0000000U) macro
141003 … (((uint32_t)(((uint32_t)(x)) << WUU_PDC2_Reserved31_SHIFT)) & WUU_PDC2_Reserved31_MASK)
/hal_nxp-latest/mcux/mcux-sdk/devices/MIMX8US3/
DMIMX8US3_dsp0.h140289 #define WUU_PDC2_Reserved31_MASK (0xC0000000U) macro
140297 … (((uint32_t)(((uint32_t)(x)) << WUU_PDC2_Reserved31_SHIFT)) & WUU_PDC2_Reserved31_MASK)
DMIMX8US3_cm33.h142603 #define WUU_PDC2_Reserved31_MASK (0xC0000000U) macro
142611 … (((uint32_t)(((uint32_t)(x)) << WUU_PDC2_Reserved31_SHIFT)) & WUU_PDC2_Reserved31_MASK)