1 /* 2 * Copyright 1997-2016 Freescale Semiconductor, Inc. 3 * Copyright 2016-2024 NXP 4 * 5 * SPDX-License-Identifier: BSD-3-Clause 6 */ 7 8 /*! 9 * @file S32Z2_WATCHDOG.h 10 * @version 2.3 11 * @date 2024-05-03 12 * @brief Peripheral Access Layer for S32Z2_WATCHDOG 13 * 14 * This file contains register definitions and macros for easy access to their 15 * bit fields. 16 * 17 * This file assumes LITTLE endian system. 18 */ 19 20 /** 21 * @page misra_violations MISRA-C:2012 violations 22 * 23 * @section [global] 24 * Violates MISRA 2012 Advisory Rule 2.3, local typedef not referenced 25 * The SoC header defines typedef for all modules. 26 * 27 * @section [global] 28 * Violates MISRA 2012 Advisory Rule 2.5, local macro not referenced 29 * The SoC header defines macros for all modules and registers. 30 * 31 * @section [global] 32 * Violates MISRA 2012 Advisory Directive 4.9, Function-like macro 33 * These are generated macros used for accessing the bit-fields from registers. 34 * 35 * @section [global] 36 * Violates MISRA 2012 Required Rule 5.1, identifier clash 37 * The supported compilers use more than 31 significant characters for identifiers. 38 * 39 * @section [global] 40 * Violates MISRA 2012 Required Rule 5.2, identifier clash 41 * The supported compilers use more than 31 significant characters for identifiers. 42 * 43 * @section [global] 44 * Violates MISRA 2012 Required Rule 5.4, identifier clash 45 * The supported compilers use more than 31 significant characters for identifiers. 46 * 47 * @section [global] 48 * Violates MISRA 2012 Required Rule 5.5, identifier clash 49 * The supported compilers use more than 31 significant characters for identifiers. 50 * 51 * @section [global] 52 * Violates MISRA 2012 Required Rule 21.1, defined macro '__I' is reserved to the compiler 53 * This type qualifier is needed to ensure correct I/O access and addressing. 54 */ 55 56 /* Prevention from multiple including the same memory map */ 57 #if !defined(S32Z2_WATCHDOG_H_) /* Check if memory map has not been already included */ 58 #define S32Z2_WATCHDOG_H_ 59 60 #include "S32Z2_COMMON.h" 61 62 /* ---------------------------------------------------------------------------- 63 -- WATCHDOG Peripheral Access Layer 64 ---------------------------------------------------------------------------- */ 65 66 /*! 67 * @addtogroup WATCHDOG_Peripheral_Access_Layer WATCHDOG Peripheral Access Layer 68 * @{ 69 */ 70 71 /** WATCHDOG - Register Layout Typedef */ 72 typedef struct { 73 __O uint32_t WDOGACS; /**< Watchdog Access Control, offset: 0x0 */ 74 __IO uint32_t WDOGCFG; /**< System Watchdog Configuration, offset: 0x4 */ 75 __IO uint32_t WDOGMIN; /**< System Watchdog Minimum Threshold Configuration, offset: 0x8 */ 76 __IO uint32_t WDOGMAX; /**< System Watchdog Maximum Threshold Configuration, offset: 0xC */ 77 uint8_t RESERVED_0[8]; 78 __I uint32_t WDOGCNT; /**< System Watchdog Count Value, offset: 0x18 */ 79 __IO uint32_t MPWDOGCFG; /**< Master Port Watchdog Control, offset: 0x1C */ 80 __IO uint32_t MPWDOGT; /**< DMSS Master Port Watchdog Threshold, offset: 0x20 */ 81 __I uint32_t EPPWDOGC; /**< PMSS Master Port Watchdog Threshold, offset: 0x24 */ 82 __I uint32_t EDPWDOGC; /**< EDP Master Port Count Value, offset: 0x28 */ 83 uint8_t RESERVED_1[20]; 84 __IO uint32_t ICUWDOGCFG; /**< ICU Watchdog Configuration, offset: 0x40 */ 85 __IO uint32_t ICUWDOGT; /**< ICU Watchdog Threshold Configuration, offset: 0x44 */ 86 __IO uint32_t SYSWDOGSIG; /**< System Watchdog Signal, offset: 0x48 */ 87 __I uint32_t ICUWDOGC; /**< ICU Watchdog Count Value, offset: 0x4C */ 88 } WATCHDOG_Type, *WATCHDOG_MemMapPtr; 89 90 /** Number of instances of the WATCHDOG module. */ 91 #define WATCHDOG_INSTANCE_COUNT (1u) 92 93 /* WATCHDOG - Peripheral instance base addresses */ 94 /** Peripheral CEVA_SPF2__WATCHDOG base address */ 95 #define IP_CEVA_SPF2__WATCHDOG_BASE (0x24400700u) 96 /** Peripheral CEVA_SPF2__WATCHDOG base pointer */ 97 #define IP_CEVA_SPF2__WATCHDOG ((WATCHDOG_Type *)IP_CEVA_SPF2__WATCHDOG_BASE) 98 /** Array initializer of WATCHDOG peripheral base addresses */ 99 #define IP_WATCHDOG_BASE_ADDRS { IP_CEVA_SPF2__WATCHDOG_BASE } 100 /** Array initializer of WATCHDOG peripheral base pointers */ 101 #define IP_WATCHDOG_BASE_PTRS { IP_CEVA_SPF2__WATCHDOG } 102 103 /* ---------------------------------------------------------------------------- 104 -- WATCHDOG Register Masks 105 ---------------------------------------------------------------------------- */ 106 107 /*! 108 * @addtogroup WATCHDOG_Register_Masks WATCHDOG Register Masks 109 * @{ 110 */ 111 112 /*! @name WDOGACS - Watchdog Access Control */ 113 /*! @{ */ 114 115 #define WATCHDOG_WDOGACS_WDOG_ACS_MASK (0xFFFFU) 116 #define WATCHDOG_WDOGACS_WDOG_ACS_SHIFT (0U) 117 #define WATCHDOG_WDOGACS_WDOG_ACS_WIDTH (16U) 118 #define WATCHDOG_WDOGACS_WDOG_ACS(x) (((uint32_t)(((uint32_t)(x)) << WATCHDOG_WDOGACS_WDOG_ACS_SHIFT)) & WATCHDOG_WDOGACS_WDOG_ACS_MASK) 119 /*! @} */ 120 121 /*! @name WDOGCFG - System Watchdog Configuration */ 122 /*! @{ */ 123 124 #define WATCHDOG_WDOGCFG_WDOG_EN_MASK (0x1U) 125 #define WATCHDOG_WDOGCFG_WDOG_EN_SHIFT (0U) 126 #define WATCHDOG_WDOGCFG_WDOG_EN_WIDTH (1U) 127 #define WATCHDOG_WDOGCFG_WDOG_EN(x) (((uint32_t)(((uint32_t)(x)) << WATCHDOG_WDOGCFG_WDOG_EN_SHIFT)) & WATCHDOG_WDOGCFG_WDOG_EN_MASK) 128 /*! @} */ 129 130 /*! @name WDOGMIN - System Watchdog Minimum Threshold Configuration */ 131 /*! @{ */ 132 133 #define WATCHDOG_WDOGMIN_WDOGMIN_MASK (0xFFFFFFFFU) 134 #define WATCHDOG_WDOGMIN_WDOGMIN_SHIFT (0U) 135 #define WATCHDOG_WDOGMIN_WDOGMIN_WIDTH (32U) 136 #define WATCHDOG_WDOGMIN_WDOGMIN(x) (((uint32_t)(((uint32_t)(x)) << WATCHDOG_WDOGMIN_WDOGMIN_SHIFT)) & WATCHDOG_WDOGMIN_WDOGMIN_MASK) 137 /*! @} */ 138 139 /*! @name WDOGMAX - System Watchdog Maximum Threshold Configuration */ 140 /*! @{ */ 141 142 #define WATCHDOG_WDOGMAX_WDOGMAX_MASK (0xFFFFFFFFU) 143 #define WATCHDOG_WDOGMAX_WDOGMAX_SHIFT (0U) 144 #define WATCHDOG_WDOGMAX_WDOGMAX_WIDTH (32U) 145 #define WATCHDOG_WDOGMAX_WDOGMAX(x) (((uint32_t)(((uint32_t)(x)) << WATCHDOG_WDOGMAX_WDOGMAX_SHIFT)) & WATCHDOG_WDOGMAX_WDOGMAX_MASK) 146 /*! @} */ 147 148 /*! @name WDOGCNT - System Watchdog Count Value */ 149 /*! @{ */ 150 151 #define WATCHDOG_WDOGCNT_WDOGCNT_MASK (0xFFFFFFFFU) 152 #define WATCHDOG_WDOGCNT_WDOGCNT_SHIFT (0U) 153 #define WATCHDOG_WDOGCNT_WDOGCNT_WIDTH (32U) 154 #define WATCHDOG_WDOGCNT_WDOGCNT(x) (((uint32_t)(((uint32_t)(x)) << WATCHDOG_WDOGCNT_WDOGCNT_SHIFT)) & WATCHDOG_WDOGCNT_WDOGCNT_MASK) 155 /*! @} */ 156 157 /*! @name MPWDOGCFG - Master Port Watchdog Control */ 158 /*! @{ */ 159 160 #define WATCHDOG_MPWDOGCFG_EPPWDOG_EN_MASK (0x2U) 161 #define WATCHDOG_MPWDOGCFG_EPPWDOG_EN_SHIFT (1U) 162 #define WATCHDOG_MPWDOGCFG_EPPWDOG_EN_WIDTH (1U) 163 #define WATCHDOG_MPWDOGCFG_EPPWDOG_EN(x) (((uint32_t)(((uint32_t)(x)) << WATCHDOG_MPWDOGCFG_EPPWDOG_EN_SHIFT)) & WATCHDOG_MPWDOGCFG_EPPWDOG_EN_MASK) 164 165 #define WATCHDOG_MPWDOGCFG_EDPWDOG_EN_MASK (0x4U) 166 #define WATCHDOG_MPWDOGCFG_EDPWDOG_EN_SHIFT (2U) 167 #define WATCHDOG_MPWDOGCFG_EDPWDOG_EN_WIDTH (1U) 168 #define WATCHDOG_MPWDOGCFG_EDPWDOG_EN(x) (((uint32_t)(((uint32_t)(x)) << WATCHDOG_MPWDOGCFG_EDPWDOG_EN_SHIFT)) & WATCHDOG_MPWDOGCFG_EDPWDOG_EN_MASK) 169 /*! @} */ 170 171 /*! @name MPWDOGT - DMSS Master Port Watchdog Threshold */ 172 /*! @{ */ 173 174 #define WATCHDOG_MPWDOGT_MPWDOGT_MASK (0xFFFFFFFFU) 175 #define WATCHDOG_MPWDOGT_MPWDOGT_SHIFT (0U) 176 #define WATCHDOG_MPWDOGT_MPWDOGT_WIDTH (32U) 177 #define WATCHDOG_MPWDOGT_MPWDOGT(x) (((uint32_t)(((uint32_t)(x)) << WATCHDOG_MPWDOGT_MPWDOGT_SHIFT)) & WATCHDOG_MPWDOGT_MPWDOGT_MASK) 178 /*! @} */ 179 180 /*! @name EPPWDOGC - PMSS Master Port Watchdog Threshold */ 181 /*! @{ */ 182 183 #define WATCHDOG_EPPWDOGC_EPPWDOGC_MASK (0xFFFFFFFFU) 184 #define WATCHDOG_EPPWDOGC_EPPWDOGC_SHIFT (0U) 185 #define WATCHDOG_EPPWDOGC_EPPWDOGC_WIDTH (32U) 186 #define WATCHDOG_EPPWDOGC_EPPWDOGC(x) (((uint32_t)(((uint32_t)(x)) << WATCHDOG_EPPWDOGC_EPPWDOGC_SHIFT)) & WATCHDOG_EPPWDOGC_EPPWDOGC_MASK) 187 /*! @} */ 188 189 /*! @name EDPWDOGC - EDP Master Port Count Value */ 190 /*! @{ */ 191 192 #define WATCHDOG_EDPWDOGC_EDPWDOGC_MASK (0xFFFFFFFFU) 193 #define WATCHDOG_EDPWDOGC_EDPWDOGC_SHIFT (0U) 194 #define WATCHDOG_EDPWDOGC_EDPWDOGC_WIDTH (32U) 195 #define WATCHDOG_EDPWDOGC_EDPWDOGC(x) (((uint32_t)(((uint32_t)(x)) << WATCHDOG_EDPWDOGC_EDPWDOGC_SHIFT)) & WATCHDOG_EDPWDOGC_EDPWDOGC_MASK) 196 /*! @} */ 197 198 /*! @name ICUWDOGCFG - ICU Watchdog Configuration */ 199 /*! @{ */ 200 201 #define WATCHDOG_ICUWDOGCFG_ICUWDOG_EN_MASK (0x1U) 202 #define WATCHDOG_ICUWDOGCFG_ICUWDOG_EN_SHIFT (0U) 203 #define WATCHDOG_ICUWDOGCFG_ICUWDOG_EN_WIDTH (1U) 204 #define WATCHDOG_ICUWDOGCFG_ICUWDOG_EN(x) (((uint32_t)(((uint32_t)(x)) << WATCHDOG_ICUWDOGCFG_ICUWDOG_EN_SHIFT)) & WATCHDOG_ICUWDOGCFG_ICUWDOG_EN_MASK) 205 /*! @} */ 206 207 /*! @name ICUWDOGT - ICU Watchdog Threshold Configuration */ 208 /*! @{ */ 209 210 #define WATCHDOG_ICUWDOGT_ICUWDOGT_MASK (0xFFFFFFFFU) 211 #define WATCHDOG_ICUWDOGT_ICUWDOGT_SHIFT (0U) 212 #define WATCHDOG_ICUWDOGT_ICUWDOGT_WIDTH (32U) 213 #define WATCHDOG_ICUWDOGT_ICUWDOGT(x) (((uint32_t)(((uint32_t)(x)) << WATCHDOG_ICUWDOGT_ICUWDOGT_SHIFT)) & WATCHDOG_ICUWDOGT_ICUWDOGT_MASK) 214 /*! @} */ 215 216 /*! @name SYSWDOGSIG - System Watchdog Signal */ 217 /*! @{ */ 218 219 #define WATCHDOG_SYSWDOGSIG_TASK0_STATE_MASK (0x3U) 220 #define WATCHDOG_SYSWDOGSIG_TASK0_STATE_SHIFT (0U) 221 #define WATCHDOG_SYSWDOGSIG_TASK0_STATE_WIDTH (2U) 222 #define WATCHDOG_SYSWDOGSIG_TASK0_STATE(x) (((uint32_t)(((uint32_t)(x)) << WATCHDOG_SYSWDOGSIG_TASK0_STATE_SHIFT)) & WATCHDOG_SYSWDOGSIG_TASK0_STATE_MASK) 223 224 #define WATCHDOG_SYSWDOGSIG_TASK1_STATE_MASK (0xCU) 225 #define WATCHDOG_SYSWDOGSIG_TASK1_STATE_SHIFT (2U) 226 #define WATCHDOG_SYSWDOGSIG_TASK1_STATE_WIDTH (2U) 227 #define WATCHDOG_SYSWDOGSIG_TASK1_STATE(x) (((uint32_t)(((uint32_t)(x)) << WATCHDOG_SYSWDOGSIG_TASK1_STATE_SHIFT)) & WATCHDOG_SYSWDOGSIG_TASK1_STATE_MASK) 228 229 #define WATCHDOG_SYSWDOGSIG_TASK2_STATE_MASK (0x30U) 230 #define WATCHDOG_SYSWDOGSIG_TASK2_STATE_SHIFT (4U) 231 #define WATCHDOG_SYSWDOGSIG_TASK2_STATE_WIDTH (2U) 232 #define WATCHDOG_SYSWDOGSIG_TASK2_STATE(x) (((uint32_t)(((uint32_t)(x)) << WATCHDOG_SYSWDOGSIG_TASK2_STATE_SHIFT)) & WATCHDOG_SYSWDOGSIG_TASK2_STATE_MASK) 233 234 #define WATCHDOG_SYSWDOGSIG_TASK3_STATE_MASK (0xC0U) 235 #define WATCHDOG_SYSWDOGSIG_TASK3_STATE_SHIFT (6U) 236 #define WATCHDOG_SYSWDOGSIG_TASK3_STATE_WIDTH (2U) 237 #define WATCHDOG_SYSWDOGSIG_TASK3_STATE(x) (((uint32_t)(((uint32_t)(x)) << WATCHDOG_SYSWDOGSIG_TASK3_STATE_SHIFT)) & WATCHDOG_SYSWDOGSIG_TASK3_STATE_MASK) 238 239 #define WATCHDOG_SYSWDOGSIG_TASK4_STATE_MASK (0x300U) 240 #define WATCHDOG_SYSWDOGSIG_TASK4_STATE_SHIFT (8U) 241 #define WATCHDOG_SYSWDOGSIG_TASK4_STATE_WIDTH (2U) 242 #define WATCHDOG_SYSWDOGSIG_TASK4_STATE(x) (((uint32_t)(((uint32_t)(x)) << WATCHDOG_SYSWDOGSIG_TASK4_STATE_SHIFT)) & WATCHDOG_SYSWDOGSIG_TASK4_STATE_MASK) 243 244 #define WATCHDOG_SYSWDOGSIG_TASK5_STATE_MASK (0xC00U) 245 #define WATCHDOG_SYSWDOGSIG_TASK5_STATE_SHIFT (10U) 246 #define WATCHDOG_SYSWDOGSIG_TASK5_STATE_WIDTH (2U) 247 #define WATCHDOG_SYSWDOGSIG_TASK5_STATE(x) (((uint32_t)(((uint32_t)(x)) << WATCHDOG_SYSWDOGSIG_TASK5_STATE_SHIFT)) & WATCHDOG_SYSWDOGSIG_TASK5_STATE_MASK) 248 249 #define WATCHDOG_SYSWDOGSIG_TASK6_STATE_MASK (0x3000U) 250 #define WATCHDOG_SYSWDOGSIG_TASK6_STATE_SHIFT (12U) 251 #define WATCHDOG_SYSWDOGSIG_TASK6_STATE_WIDTH (2U) 252 #define WATCHDOG_SYSWDOGSIG_TASK6_STATE(x) (((uint32_t)(((uint32_t)(x)) << WATCHDOG_SYSWDOGSIG_TASK6_STATE_SHIFT)) & WATCHDOG_SYSWDOGSIG_TASK6_STATE_MASK) 253 254 #define WATCHDOG_SYSWDOGSIG_TASK7_STATE_MASK (0xC000U) 255 #define WATCHDOG_SYSWDOGSIG_TASK7_STATE_SHIFT (14U) 256 #define WATCHDOG_SYSWDOGSIG_TASK7_STATE_WIDTH (2U) 257 #define WATCHDOG_SYSWDOGSIG_TASK7_STATE(x) (((uint32_t)(((uint32_t)(x)) << WATCHDOG_SYSWDOGSIG_TASK7_STATE_SHIFT)) & WATCHDOG_SYSWDOGSIG_TASK7_STATE_MASK) 258 /*! @} */ 259 260 /*! @name ICUWDOGC - ICU Watchdog Count Value */ 261 /*! @{ */ 262 263 #define WATCHDOG_ICUWDOGC_ICUWDOGC_MASK (0xFFFFFFFFU) 264 #define WATCHDOG_ICUWDOGC_ICUWDOGC_SHIFT (0U) 265 #define WATCHDOG_ICUWDOGC_ICUWDOGC_WIDTH (32U) 266 #define WATCHDOG_ICUWDOGC_ICUWDOGC(x) (((uint32_t)(((uint32_t)(x)) << WATCHDOG_ICUWDOGC_ICUWDOGC_SHIFT)) & WATCHDOG_ICUWDOGC_ICUWDOGC_MASK) 267 /*! @} */ 268 269 /*! 270 * @} 271 */ /* end of group WATCHDOG_Register_Masks */ 272 273 /*! 274 * @} 275 */ /* end of group WATCHDOG_Peripheral_Access_Layer */ 276 277 #endif /* #if !defined(S32Z2_WATCHDOG_H_) */ 278
