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Searched refs:Value (Results 1 – 25 of 42) sorted by relevance

12

/hal_nxp-latest/s32/drivers/s32ze/Spi/src/
DSpi_Ip.c609 DmaTcdList[0u].Value = 0u; /* dummy src address read, it will be updated later */ in Spi_Ip_CmdDmaTcdSGInit()
610 DmaTcdList[1u].Value = (Dma_Ip_uintPtrType)&Base->PUSHR.FIFO.CMD; /* dest address write*/ in Spi_Ip_CmdDmaTcdSGInit()
611 DmaTcdList[2u].Value = 0u; /* no src offset */ in Spi_Ip_CmdDmaTcdSGInit()
612 DmaTcdList[3u].Value = DMA_IP_TRANSFER_SIZE_2_BYTE; /* 2 bytes src transfer size */ in Spi_Ip_CmdDmaTcdSGInit()
613 DmaTcdList[4u].Value = DMA_IP_TRANSFER_SIZE_2_BYTE; /* 2 bytes dest transfer size */ in Spi_Ip_CmdDmaTcdSGInit()
614 DmaTcdList[5u].Value = 2u; /* bytes to transfer for each request */ in Spi_Ip_CmdDmaTcdSGInit()
615 DmaTcdList[6u].Value = 0u; /* no dest offset */ in Spi_Ip_CmdDmaTcdSGInit()
616 DmaTcdList[7u].Value = 0u; /* dummy iteration count will be updated later */ in Spi_Ip_CmdDmaTcdSGInit()
617 …DmaTcdList[8u].Value = 1u; /* dummy disable hardware request when major loop complete, will be u… in Spi_Ip_CmdDmaTcdSGInit()
649 DmaTcdList[1u].Value = (Dma_Ip_uintPtrType)&Base->PUSHR.FIFO.TX; /* dest address write*/ in Spi_Ip_TxDmaTcdSGInit()
[all …]
/hal_nxp-latest/s32/drivers/s32k3/Pwm/include/
DEmios_Pwm_Ip_HwAccess.h153 boolean Value) in Emios_Pwm_Ip_SetOutputUpdate() argument
155 Base->OUDIS = Base->OUDIS | (eMIOS_OUDIS_OU0((Value == TRUE) ? 0x00U : 0x01U) << Channel); in Emios_Pwm_Ip_SetOutputUpdate()
187 boolean Value) in Emios_Pwm_Ip_SetChannelEnable() argument
189 Base->UCDIS = Base->UCDIS | (eMIOS_UCDIS_UCDIS0((Value == TRUE) ? 0x00U : 0x01U) << Channel); in Emios_Pwm_Ip_SetChannelEnable()
213 Emios_Pwm_Ip_PeriodType Value) in Emios_Pwm_Ip_SetUCRegA() argument
215 Base->CH.UC[Channel].A = eMIOS_A_A(Value); in Emios_Pwm_Ip_SetUCRegA()
239 Emios_Pwm_Ip_PeriodType Value) in Emios_Pwm_Ip_SetUCRegB() argument
241 Base->CH.UC[Channel].B = eMIOS_B_B(Value); in Emios_Pwm_Ip_SetUCRegB()
280 boolean Value) in Emios_Pwm_Ip_SetFreezeEnable() argument
282 uint8 ValueConvert = (Value == FALSE)? 0U : 1U; in Emios_Pwm_Ip_SetFreezeEnable()
[all …]
DEmios_Pwm_Ip.h395 boolean Value);
407 Emios_Pwm_Ip_CounterBusSourceType Value);
419 Emios_Pwm_Ip_InternalClkPsType Value);
459 void Emios_Pwm_Ip_UpdateUCRegA(uint8 Instance, uint8 Channel, Emios_Pwm_Ip_PeriodType Value);
472 void Emios_Pwm_Ip_UpdateUCRegB(uint8 Instance, uint8 Channel, Emios_Pwm_Ip_PeriodType Value);
/hal_nxp-latest/s32/drivers/s32ze/Pwm/include/
DEmios_Pwm_Ip_HwAccess.h170 boolean Value in Emios_Pwm_Ip_SetOutputUpdate() argument
173 Base->OUDIS = Base->OUDIS | (eMIOS_OUDIS_OU0((Value == TRUE) ? 0x00U : 0x01U) << Channel); in Emios_Pwm_Ip_SetOutputUpdate()
206 Emios_Pwm_Ip_PeriodType Value in Emios_Pwm_Ip_SetUCRegA() argument
209 Base->CH.UC[Channel].A = eMIOS_A_A(Value); in Emios_Pwm_Ip_SetUCRegA()
234 Emios_Pwm_Ip_PeriodType Value in Emios_Pwm_Ip_SetUCRegB() argument
237 Base->CH.UC[Channel].B = eMIOS_B_B(Value); in Emios_Pwm_Ip_SetUCRegB()
278 boolean Value in Emios_Pwm_Ip_SetFreezeEnable() argument
281 uint8 ValueConvert = (Value == FALSE)? 0U : 1U; in Emios_Pwm_Ip_SetFreezeEnable()
293 boolean Value in Emios_Pwm_Ip_SetOutDisable() argument
296 uint8 ValueConvert = (Value == FALSE)? 0U : 1U; in Emios_Pwm_Ip_SetOutDisable()
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DEmios_Pwm_Ip.h522 boolean Value
535 Emios_Pwm_Ip_CounterBusSourceType Value
548 Emios_Pwm_Ip_InternalClkPsType Value
589 void Emios_Pwm_Ip_UpdateUCRegA(uint8 Instance, uint8 Channel, Emios_Pwm_Ip_PeriodType Value);
602 void Emios_Pwm_Ip_UpdateUCRegB(uint8 Instance, uint8 Channel, Emios_Pwm_Ip_PeriodType Value);
/hal_nxp-latest/s32/drivers/s32k3/Adc/include/
DAdc_Sar_Ip_HwAccess.h285 uint32 Value = ADC_THRHLR_THRH(HighThreshold) | in Adc_Sar_WriteThresholds() local
287 AdcBasePtr->THRHLR[RegisterNumber] = Value; in Adc_Sar_WriteThresholds()
291 uint32 Value = ADC_THRHLR0_THRH(HighThreshold) | in Adc_Sar_WriteThresholds() local
296 *THRHLR0Addr = Value; in Adc_Sar_WriteThresholds()
299 *THRHLR1Addr = Value; in Adc_Sar_WriteThresholds()
302 *THRHLR2Addr = Value; in Adc_Sar_WriteThresholds()
305 *THRHLR3Addr = Value; in Adc_Sar_WriteThresholds()
308 *THRHLR4Addr = Value; in Adc_Sar_WriteThresholds()
311 *THRHLR5Addr = Value; in Adc_Sar_WriteThresholds()
315 *THRHLR6Addr = Value; in Adc_Sar_WriteThresholds()
[all …]
/hal_nxp-latest/s32/drivers/s32ze/Adc/include/
DAdc_Sar_Ip_HwAccess.h290 uint32 Value = ADC_THRHLR_THRH(HighThreshold) | in Adc_Sar_WriteThresholds() local
292 AdcBasePtr->THRHLR[RegisterNumber] = Value; in Adc_Sar_WriteThresholds()
296 uint32 Value = ADC_THRHLR0_THRH(HighThreshold) | in Adc_Sar_WriteThresholds() local
301 *THRHLR0Addr = Value; in Adc_Sar_WriteThresholds()
304 *THRHLR1Addr = Value; in Adc_Sar_WriteThresholds()
307 *THRHLR2Addr = Value; in Adc_Sar_WriteThresholds()
310 *THRHLR3Addr = Value; in Adc_Sar_WriteThresholds()
313 *THRHLR4Addr = Value; in Adc_Sar_WriteThresholds()
316 *THRHLR5Addr = Value; in Adc_Sar_WriteThresholds()
320 *THRHLR6Addr = Value; in Adc_Sar_WriteThresholds()
[all …]
/hal_nxp-latest/s32/drivers/s32k3/Mcu/src/
DClock_Ip_Pll.c187 uint32 Value; in Clock_Ip_SetPllRdivMfiMfnOdiv2SdmenSsscgbypSpreadctlStepnoStepsize() local
196 Value = Clock_Ip_apxPll[Instance].PllInstance->PLLDV; in Clock_Ip_SetPllRdivMfiMfnOdiv2SdmenSsscgbypSpreadctlStepnoStepsize()
197 Value &= ~(PLL_PLLDV_RDIV_MASK | PLL_PLLDV_MFI_MASK); in Clock_Ip_SetPllRdivMfiMfnOdiv2SdmenSsscgbypSpreadctlStepnoStepsize()
198 Value |= (uint32) (PLL_PLLDV_RDIV(Config->Predivider) | in Clock_Ip_SetPllRdivMfiMfnOdiv2SdmenSsscgbypSpreadctlStepnoStepsize()
200 Clock_Ip_apxPll[Instance].PllInstance->PLLDV = Value; in Clock_Ip_SetPllRdivMfiMfnOdiv2SdmenSsscgbypSpreadctlStepnoStepsize()
203 Value = Clock_Ip_apxPll[Instance].PllInstance->PLLFD; in Clock_Ip_SetPllRdivMfiMfnOdiv2SdmenSsscgbypSpreadctlStepnoStepsize()
204 Value &= ~(PLL_PLLFD_MFN_MASK | PLL_PLLFD_SDMEN_MASK); in Clock_Ip_SetPllRdivMfiMfnOdiv2SdmenSsscgbypSpreadctlStepnoStepsize()
205 Value |= PLL_PLLFD_MFN(Config->NumeratorFracLoopDiv); in Clock_Ip_SetPllRdivMfiMfnOdiv2SdmenSsscgbypSpreadctlStepnoStepsize()
206 Value |= PLL_PLLFD_SDMEN(Config->SigmaDelta); in Clock_Ip_SetPllRdivMfiMfnOdiv2SdmenSsscgbypSpreadctlStepnoStepsize()
207 Clock_Ip_apxPll[Instance].PllInstance->PLLFD = Value; in Clock_Ip_SetPllRdivMfiMfnOdiv2SdmenSsscgbypSpreadctlStepnoStepsize()
[all …]
DClock_Ip_Divider.c161 if (Config->Value != 0U) in Clock_Ip_SetCgmXDeDivStatWithoutPhase()
165 RegValue |= (((Config->Value-1U) << DividerShift) & DividerMask); in Clock_Ip_SetCgmXDeDivStatWithoutPhase()
196 if (Config->Value != 0U) in Clock_Ip_SetCgmXDeDivStatWithoutPhase()
243 if (Config->Value != 0U) in Clock_Ip_SetPllPll0divDeDivOutput()
248 RegValue |= PLL_PLLODIV_DIV(Config->Value - 1U); in Clock_Ip_SetPllPll0divDeDivOutput()
272 DividerValue = (Config->Value != 0U) ? Config->Value : 1U; in Clock_Ip_SetPllPlldvOdiv2Output()
/hal_nxp-latest/s32/drivers/s32k3/BaseNXP/src/
DOsIf_Timer.c240 uint32 Value = 0u; in OsIf_GetCounter() local
243 Value = OsIf_Timer_Dummy_GetCounter(); in OsIf_GetCounter()
247 Value = OsIf_Timer_System_GetCounter(); in OsIf_GetCounter()
252 Value = OsIf_Timer_Custom_GetCounter(); in OsIf_GetCounter()
257 return Value; in OsIf_GetCounter()
264 uint32 Value = 0u; in OsIf_GetElapsed() local
267 Value = OsIf_Timer_Dummy_GetElapsed(CurrentRef); in OsIf_GetElapsed()
271 Value = OsIf_Timer_System_GetElapsed(CurrentRef); in OsIf_GetElapsed()
276 Value = OsIf_Timer_Custom_GetElapsed(CurrentRef); in OsIf_GetElapsed()
281 return Value; in OsIf_GetElapsed()
[all …]
/hal_nxp-latest/s32/drivers/s32k1/BaseNXP/src/
DOsIf_Timer.c281 uint32 Value = 0U; in OsIf_GetCounter() local
285 Value = OsIf_Timer_Dummy_GetCounter(); in OsIf_GetCounter()
289 Value = OsIf_Timer_System_GetCounter(); in OsIf_GetCounter()
294 Value = OsIf_Timer_Custom_GetCounter(); in OsIf_GetCounter()
302 return Value; in OsIf_GetCounter()
315 uint32 Value = 0U; in OsIf_GetElapsed() local
319 Value = OsIf_Timer_Dummy_GetElapsed(CurrentRef); in OsIf_GetElapsed()
323 Value = OsIf_Timer_System_GetElapsed(CurrentRef); in OsIf_GetElapsed()
328 Value = OsIf_Timer_Custom_GetElapsed(CurrentRef); in OsIf_GetElapsed()
336 return Value; in OsIf_GetElapsed()
[all …]
/hal_nxp-latest/s32/drivers/s32ze/BaseNXP/src/
DOsIf_Timer.c314 uint32 Value = 0U; in OsIf_GetCounter() local
318 Value = OsIf_Timer_Dummy_GetCounter(); in OsIf_GetCounter()
322 Value = OsIf_Timer_System_GetCounter(); in OsIf_GetCounter()
327 Value = OsIf_Timer_Custom_GetCounter(); in OsIf_GetCounter()
335 return Value; in OsIf_GetCounter()
348 uint32 Value = 0U; in OsIf_GetElapsed() local
352 Value = OsIf_Timer_Dummy_GetElapsed(CurrentRef); in OsIf_GetElapsed()
356 Value = OsIf_Timer_System_GetElapsed(CurrentRef); in OsIf_GetElapsed()
361 Value = OsIf_Timer_Custom_GetElapsed(CurrentRef); in OsIf_GetElapsed()
369 return Value; in OsIf_GetElapsed()
[all …]
/hal_nxp-latest/s32/drivers/s32ze/Mcu/src/
DClock_Ip_Pll.c193 uint32 Value; in Clock_Ip_SetPlldigRdivMfiMfnSdmenSsscgbypSpreadctlStepnoStepsize() local
218 Value = Clock_Ip_apxPll[Instance].PllInstance->PLLDV; in Clock_Ip_SetPlldigRdivMfiMfnSdmenSsscgbypSpreadctlStepnoStepsize()
219 Value &= ~(PLLDIG_PLLDV_RDIV_MASK | PLLDIG_PLLDV_MFI_MASK); in Clock_Ip_SetPlldigRdivMfiMfnSdmenSsscgbypSpreadctlStepnoStepsize()
220 Value |= (uint32) (PLLDIG_PLLDV_RDIV(Config->Predivider) | in Clock_Ip_SetPlldigRdivMfiMfnSdmenSsscgbypSpreadctlStepnoStepsize()
222 Clock_Ip_apxPll[Instance].PllInstance->PLLDV = Value; in Clock_Ip_SetPlldigRdivMfiMfnSdmenSsscgbypSpreadctlStepnoStepsize()
224 Value = Clock_Ip_apxPll[Instance].PllInstance->PLLFD; in Clock_Ip_SetPlldigRdivMfiMfnSdmenSsscgbypSpreadctlStepnoStepsize()
225 Value &= ~(PLLDIG_PLLFD_MFN_MASK | PLLDIG_PLLFD_SDMEN_MASK); in Clock_Ip_SetPlldigRdivMfiMfnSdmenSsscgbypSpreadctlStepnoStepsize()
226 Value |= PLLDIG_PLLFD_MFN(Config->NumeratorFracLoopDiv); in Clock_Ip_SetPlldigRdivMfiMfnSdmenSsscgbypSpreadctlStepnoStepsize()
227 Value |= PLLDIG_PLLFD_SDMEN(Config->SigmaDelta); in Clock_Ip_SetPlldigRdivMfiMfnSdmenSsscgbypSpreadctlStepnoStepsize()
228 Clock_Ip_apxPll[Instance].PllInstance->PLLFD = Value; in Clock_Ip_SetPlldigRdivMfiMfnSdmenSsscgbypSpreadctlStepnoStepsize()
[all …]
DClock_Ip_FracDiv.c158 uint32 Value = 0U; in Clock_Ip_SetDfsMfiMfn() local
164 IntegerPart = Config->Value[0U]; in Clock_Ip_SetDfsMfiMfn()
165 FractionalPart = Config->Value[1U]; in Clock_Ip_SetDfsMfiMfn()
171 Value |= DFS_DVPORT_MFN(FractionalPart); in Clock_Ip_SetDfsMfiMfn()
172 Value |= DFS_DVPORT_MFI(IntegerPart); in Clock_Ip_SetDfsMfiMfn()
173 Clock_Ip_apxDfs[Instance]->DVPORT[DividerIndex] = Value; in Clock_Ip_SetDfsMfiMfn()
DClock_Ip_Divider.c165 if (Config->Value != 0U) in Clock_Ip_SetCgmXDeDivStatWithoutPhase()
168 RegValue |= (((Config->Value-1U) << DividerShift) & DividerMask); in Clock_Ip_SetCgmXDeDivStatWithoutPhase()
254 if (Config->Value != 0U) in Clock_Ip_SetCgmXDeDivFmtStatWithoutPhase()
257 RegValue |= (((Config->Value-1U) << DividerShift) & DividerMask); in Clock_Ip_SetCgmXDeDivFmtStatWithoutPhase()
332 if (Config->Value != 0U) in Clock_Ip_SetCgmXDeDivStatWithoutPhaseWithTrigger()
335 RegValue |= ((Config->Value-1U) << DividerShift) & DividerMask; in Clock_Ip_SetCgmXDeDivStatWithoutPhaseWithTrigger()
399 if (Config->Value != 0U) in Clock_Ip_SetPlldigPll0divDeDivOutput()
404 RegValue |= PLLDIG_PLLODIV_DIV(Config->Value - 1U); in Clock_Ip_SetPlldigPll0divDeDivOutput()
/hal_nxp-latest/s32/drivers/s32k3/Mcl/src/
DLcu_Ip_Hw_Access.c108 …oid HwAcc_Lcu_AsyncGetLogicInput (const uint8 LcuId, const uint8 HwLcInputId, uint8 * const Value);
110 …wAcc_Lcu_AsyncGetSwOverrideInput (const uint8 LcuId, const uint8 HwLcInputId, uint8 * const Value);
112 …id HwAcc_Lcu_AsyncGetLogicOutput(const uint8 LcuId, const uint8 HwLcOutputId, uint8 * const Value);
114 …id HwAcc_Lcu_AsyncGetForceOutput(const uint8 LcuId, const uint8 HwLcOutputId, uint8 * const Value);
116 …id HwAcc_Lcu_AsyncGetForceStatus(const uint8 LcuId, const uint8 HwLcOutputId, uint8 * const Value);
118 … HwAcc_Lcu_AsyncGetCombineForce (const uint8 LcuId, const uint8 HwLcOutputId, uint8 * const Value);
120 …void HwAcc_Lcu_AsyncGetLutStatus(const uint8 LcuId, const uint8 HwLcOutputId, uint8 * const Value);
562 …void HwAcc_Lcu_AsyncGetLogicInput (const uint8 LcuId, const uint8 HwLcInputId, uint8 * const Value) in HwAcc_Lcu_AsyncGetLogicInput() argument
565 *Value = (uint8)((Lcu_Ip_paxBaseInst[LcuId]->LCIN >> HwLcInputId) & 1U); in HwAcc_Lcu_AsyncGetLogicInput()
568 …HwAcc_Lcu_AsyncGetSwOverrideInput (const uint8 LcuId, const uint8 HwLcInputId, uint8 * const Value) in HwAcc_Lcu_AsyncGetSwOverrideInput() argument
[all …]
DLcu_Ip.c389 … DataValue[LocHwLcu] |= (uint32)(((uint32)(List[LocIndex].Value) & 1U) << LocHwLcInputId); in Lcu_Ip_SetSyncInputSwOverrideEnable()
481 … DataValue[LocHwLcu] |= (uint32)(((uint32)(List[LocIndex].Value) & 1U) << LocHwLcInputId); in Lcu_Ip_SetSyncInputSwOverrideValue()
581 MaskValue = ((List[LocIndex].Value) & LCU_MUXSEL_MUXSEL_MASK); in Lcu_Ip_SetSyncInputMuxSelect()
640 MaskValue = ((List[LocIndex].Value) & 1U); in Lcu_Ip_SetSyncInputSwSyncMode()
691 … DataValue[LocHwLcu] |= (uint32)(((uint32)(List[LocIndex].Value) & 1U) << LocHwLcOutputId); in Lcu_Ip_SetSyncOutputDebugMode()
782 … DataValue[LocHwLcu] |= (uint32)(((uint32)(List[LocIndex].Value) & 1U) << LocHwLcOutputId); in Lcu_Ip_SetSyncOutputEnable()
883 MaskValue = ((List[LocIndex].Value) & LCU_FCTRL_FORCE_SENSE_COMMON_MASK); in Lcu_Ip_SetSyncOutputForceInputSensitivity()
945 MaskValue = ((List[LocIndex].Value) & LCU_FCTRL_FORCE_MODE_COMMON_MASK); in Lcu_Ip_SetSyncOutputForceClearingMode()
1006 MaskValue = ((List[LocIndex].Value) & LCU_FCTRL_SYNC_SEL_COMMON_MASK); in Lcu_Ip_SetSyncOutputForceSyncSelect()
1067 MaskValue = ((List[LocIndex].Value) & 1U); in Lcu_Ip_SetSyncOutputPolarity()
[all …]
/hal_nxp-latest/s32/drivers/s32k1/Mcu/src/
DClock_Ip_Divider.c467 …uint32 DividerValue = Clock_Ip_au8DividerValueHardwareValue[Config->Value]; /* Hw value corres… in Clock_Ip_SetScgAsyncDiv1_TrustedCall()
482 …uint32 DividerValue = Clock_Ip_au8DividerValueHardwareValue[Config->Value]; /* Hw value corres… in Clock_Ip_SetScgAsyncDiv2_TrustedCall()
499 RegValue |= ((Config->Value - 1U) << SCG_RCCR_DIVCORE_SHIFT); in Clock_Ip_SetScgRunDivcore_TrustedCall()
512 RegValue |= ((Config->Value - 1U) << SCG_RCCR_DIVBUS_SHIFT); in Clock_Ip_SetScgRunDivbus_TrustedCall()
525 RegValue |= ((Config->Value - 1U) << SCG_RCCR_DIVSLOW_SHIFT); in Clock_Ip_SetScgRunDivslow_TrustedCall()
538 RegValue |= ((Config->Value - 1U) << SCG_VCCR_DIVCORE_SHIFT); in Clock_Ip_SetScgVlprDivcore_TrustedCall()
551 RegValue |= ((Config->Value - 1U) << SCG_VCCR_DIVBUS_SHIFT); in Clock_Ip_SetScgVlprDivbus_TrustedCall()
564 RegValue |= ((Config->Value - 1U) << SCG_VCCR_DIVSLOW_SHIFT); in Clock_Ip_SetScgVlprDivslow_TrustedCall()
577 RegValue |= ((Config->Value - 1U) << SCG_HCCR_DIVCORE_SHIFT); in Clock_Ip_SetScgHsrunDivcore_TrustedCall()
590 RegValue |= ((Config->Value - 1U) << SCG_HCCR_DIVBUS_SHIFT); in Clock_Ip_SetScgHsrunDivbus_TrustedCall()
[all …]
DClock_Ip_Specific.c384 …(uint32)(Clock_Ip_au16SelectorEntryHardwareValue[Config->Selectors[Index].Value]) << SIM_LPOCLKS_R… in SetSimLpoclksRegister_TrustedCall()
390 …int32)(Clock_Ip_au8SelectorEntrySIMHardwareValue[Config->Selectors[Index].Value]) << SIM_LPOCLKS_L… in SetSimLpoclksRegister_TrustedCall()
722 …SelectorConfigurations[SelectorConfigIndex].Value = ClockSource[(IP_SCG->RCCR & SCG_RCCR_SCS_MASK)… in getSelectorConfig()
725 …SelectorConfigurations[SelectorConfigIndex].Value = ClockSource[(IP_SCG->VCCR & SCG_VCCR_SCS_MASK)… in getSelectorConfig()
729 …SelectorConfigurations[SelectorConfigIndex].Value = ClockSource[(IP_SCG->HCCR & SCG_HCCR_SCS_MASK)… in getSelectorConfig()
786 …CoreDividerConfigurations[DividerConfigIndex].Value = ((IP_SCG->RCCR & SCG_RCCR_DIVCORE_MASK) >> S… in getCoreDividerConfig()
789 …CoreDividerConfigurations[DividerConfigIndex].Value = ((IP_SCG->VCCR & SCG_VCCR_DIVCORE_MASK) >> S… in getCoreDividerConfig()
793 …CoreDividerConfigurations[DividerConfigIndex].Value = ((IP_SCG->HCCR & SCG_HCCR_DIVCORE_MASK) >> S… in getCoreDividerConfig()
852 …BusDividerConfigurations[DividerConfigIndex].Value = ((IP_SCG->RCCR & SCG_RCCR_DIVBUS_MASK) >> SCG… in getBusDividerConfig()
855 …BusDividerConfigurations[DividerConfigIndex].Value = ((IP_SCG->VCCR & SCG_VCCR_DIVBUS_MASK) >> SCG… in getBusDividerConfig()
[all …]
DClock_Ip_Selector.c521 …uint32 SelectorValue = Clock_Ip_au8SelectorEntryScsHardwareValue[Config->Value]; /* Hw value co… in Clock_Ip_SetScgRunSel_TrustedCall()
535 …uint32 SelectorValue = Clock_Ip_au8SelectorEntryScsHardwareValue[Config->Value]; /* Hw value co… in Clock_Ip_SetScgVlprSel_TrustedCall()
561 …uint32 SelectorValue = Clock_Ip_au8SelectorEntryScsHardwareValue[Config->Value]; /* Hw value co… in Clock_Ip_SetScgHsrunSel_TrustedCall()
587 …uint32 SelectorValue = Clock_Ip_au16SelectorEntryHardwareValue[Config->Value]; /* Hw value corr… in Clock_Ip_SetSimRtcSel_TrustedCall()
613 …uint32 SelectorValue = Clock_Ip_au8SelectorEntrySIMHardwareValue[Config->Value]; /* Hw value co… in Clock_Ip_SetSimLpoSel_TrustedCall()
641 …uint32 SelectorValue = Clock_Ip_au8SelectorEntryScsHardwareValue[Config->Value]; /* Hw value co… in Clock_Ip_SetScgClkoutSel_TrustedCall()
678 …uint32 SelectorValue = Clock_Ip_au16SelectorEntryHardwareValue[Config->Value]; /* Hw value corr… in Clock_Ip_SetSimFtmoptSel_TrustedCall()
712 …uint32 SelectorValue = Clock_Ip_au16SelectorEntryHardwareValue[Config->Value]; /* Hw value corr… in Clock_Ip_SetSimClkoutSel_TrustedCall()
737 …uint32 SelectorValue = Clock_Ip_au8SelectorEntryPcsHardwareValue[Config->Value]; /* Hw value co… in Clock_Ip_SetPccPcsSelect_TrustedCall()
763 …uint32 SelectorValue = Clock_Ip_au16SelectorEntryHardwareValue[Config->Value]; /* Hw value corr… in Clock_Ip_SetSimTraceSel_TrustedCall()
/hal_nxp-latest/s32/drivers/s32ze/Uart/src/
DLinflexd_Uart_Ip.c1603 DmaTransferList[0].Value = (uint32)TxBuff; in Linflexd_Uart_Ip_StartSendUsingDma()
1605 DmaTransferList[1].Value = LINFLEXD_UART_IP_LSBW_ADDR(Base->BDRL); in Linflexd_Uart_Ip_StartSendUsingDma()
1608 DmaTransferList[3].Value = 0; in Linflexd_Uart_Ip_StartSendUsingDma()
1615 DmaTransferList[2].Value = 1; in Linflexd_Uart_Ip_StartSendUsingDma()
1616 DmaTransferList[4].Value = TxSize; in Linflexd_Uart_Ip_StartSendUsingDma()
1617 DmaTransferList[5].Value = 1; in Linflexd_Uart_Ip_StartSendUsingDma()
1618 DmaTransferList[6].Value = DMA_IP_TRANSFER_SIZE_1_BYTE; in Linflexd_Uart_Ip_StartSendUsingDma()
1619 DmaTransferList[7].Value = DMA_IP_TRANSFER_SIZE_1_BYTE; in Linflexd_Uart_Ip_StartSendUsingDma()
1623 DmaTransferList[2].Value = 2; in Linflexd_Uart_Ip_StartSendUsingDma()
1624 DmaTransferList[4].Value = TxSize/(uint32)2; in Linflexd_Uart_Ip_StartSendUsingDma()
[all …]
/hal_nxp-latest/s32/drivers/s32k3/Icu/src/
DEmios_Icu_Ip.c937 global_DmaChannelTransferList[0U].Value = Emios_Icu_Ip_GetStartAddress(instance, hwChannel); in Emios_Icu_Ip_StartTimestamp()
941 global_DmaChannelTransferList[1U].Value = (uint32)bufferPtr; in Emios_Icu_Ip_StartTimestamp()
943 global_DmaChannelTransferList[2U].Value = (uint32)DMA_IP_TRANSFER_SIZE_4_BYTE; in Emios_Icu_Ip_StartTimestamp()
945 global_DmaChannelTransferList[3U].Value = (uint32)DMA_IP_TRANSFER_SIZE_4_BYTE; in Emios_Icu_Ip_StartTimestamp()
947 global_DmaChannelTransferList[4U].Value = (uint32)0U; in Emios_Icu_Ip_StartTimestamp()
949 global_DmaChannelTransferList[5U].Value = (uint32)4U; in Emios_Icu_Ip_StartTimestamp()
951 global_DmaChannelTransferList[6U].Value = (uint32)0U; in Emios_Icu_Ip_StartTimestamp()
953 global_DmaChannelTransferList[7U].Value = (uint32)0U; in Emios_Icu_Ip_StartTimestamp()
958 global_DmaChannelTransferList[8U].Value = 4U; in Emios_Icu_Ip_StartTimestamp()
960 global_DmaChannelTransferList[9U].Value = bufferSize; in Emios_Icu_Ip_StartTimestamp()
[all …]
/hal_nxp-latest/s32/drivers/s32k3/Mcl/include/
DLcu_Ip.h156 uint8 Value; member
168 uint16 Value; member
180 uint8 Value; member
192 uint16 Value; member
861 …InputInfo(const uint8 LogicInput, const Lcu_Ip_LogicInputInfoParamType Param, uint8 * const Value);
881 …putInfo(const uint8 LogicOutput, const Lcu_Ip_LogicOutputInfoParamType Param, uint8 * const Value);
/hal_nxp-latest/s32/drivers/s32ze/Icu/src/
DEmios_Icu_Ip.c1065 global_DmaChannelTransferList[0U].Value = Emios_Icu_Ip_GetStartAddress(instance, hwChannel); in Emios_Icu_Ip_StartTimestamp()
1069 global_DmaChannelTransferList[1U].Value = (uint32)bufferPtr; in Emios_Icu_Ip_StartTimestamp()
1071 global_DmaChannelTransferList[2U].Value = (uint32)DMA_IP_TRANSFER_SIZE_4_BYTE; in Emios_Icu_Ip_StartTimestamp()
1073 global_DmaChannelTransferList[3U].Value = (uint32)DMA_IP_TRANSFER_SIZE_4_BYTE; in Emios_Icu_Ip_StartTimestamp()
1075 global_DmaChannelTransferList[4U].Value = (uint32)0U; in Emios_Icu_Ip_StartTimestamp()
1077 global_DmaChannelTransferList[5U].Value = (uint32)4U; in Emios_Icu_Ip_StartTimestamp()
1079 global_DmaChannelTransferList[6U].Value = (uint32)0U; in Emios_Icu_Ip_StartTimestamp()
1081 global_DmaChannelTransferList[7U].Value = (uint32)0U; in Emios_Icu_Ip_StartTimestamp()
1086 global_DmaChannelTransferList[8U].Value = 4U; in Emios_Icu_Ip_StartTimestamp()
1088 global_DmaChannelTransferList[9U].Value = bufferSize; in Emios_Icu_Ip_StartTimestamp()
[all …]
/hal_nxp-latest/mcux/mcux-sdk/components/video/display/it6161/
Dfsl_it6161.h106 #define HDMITX_SetI2C_Byte(handle, RegAddr, Mask, Value) \ argument
107 IT6161_I2C_ModifyReg(handle, HDMI_TX_ADDR, RegAddr, Mask, Value)
116 #define HDMITX_CEC_SetI2C_Byte(handle, RegAddr, Mask, Value) \ argument
117 IT6161_I2C_ModifyReg(handle, HDMI_TX_CEC_ADDR, RegAddr, Mask, Value)
123 #define MIPIRX_SetI2C_Byte(handle, RegAddr, Mask, Value) \ argument
124 IT6161_I2C_ModifyReg(handle, MIPI_RX_ADDR, RegAddr, Mask, Value)

12