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Searched refs:VPU_HEVC_SWREG226_SW_ENC_HWROI8SUPPORT_MASK (Results 1 – 6 of 6) sorted by relevance

/hal_nxp-latest/mcux/mcux-sdk/devices/MIMX8ML6/
DMIMX8ML6_cm7.h117659 #define VPU_HEVC_SWREG226_SW_ENC_HWROI8SUPPORT_MASK (0x200U) macro
117661 …)) << VPU_HEVC_SWREG226_SW_ENC_HWROI8SUPPORT_SHIFT)) & VPU_HEVC_SWREG226_SW_ENC_HWROI8SUPPORT_MASK)
/hal_nxp-latest/mcux/mcux-sdk/devices/MIMX8ML4/
DMIMX8ML4_cm7.h117659 #define VPU_HEVC_SWREG226_SW_ENC_HWROI8SUPPORT_MASK (0x200U) macro
117661 …)) << VPU_HEVC_SWREG226_SW_ENC_HWROI8SUPPORT_SHIFT)) & VPU_HEVC_SWREG226_SW_ENC_HWROI8SUPPORT_MASK)
/hal_nxp-latest/mcux/mcux-sdk/devices/MIMX8ML3/
DMIMX8ML3_cm7.h117659 #define VPU_HEVC_SWREG226_SW_ENC_HWROI8SUPPORT_MASK (0x200U) macro
117661 …)) << VPU_HEVC_SWREG226_SW_ENC_HWROI8SUPPORT_SHIFT)) & VPU_HEVC_SWREG226_SW_ENC_HWROI8SUPPORT_MASK)
/hal_nxp-latest/mcux/mcux-sdk/devices/MIMX8ML8/
DMIMX8ML8_dsp.h112827 #define VPU_HEVC_SWREG226_SW_ENC_HWROI8SUPPORT_MASK (0x200U) macro
112829 …)) << VPU_HEVC_SWREG226_SW_ENC_HWROI8SUPPORT_SHIFT)) & VPU_HEVC_SWREG226_SW_ENC_HWROI8SUPPORT_MASK)
DMIMX8ML8_cm7.h117659 #define VPU_HEVC_SWREG226_SW_ENC_HWROI8SUPPORT_MASK (0x200U) macro
117661 …)) << VPU_HEVC_SWREG226_SW_ENC_HWROI8SUPPORT_SHIFT)) & VPU_HEVC_SWREG226_SW_ENC_HWROI8SUPPORT_MASK)
DMIMX8ML8_ca53.h117692 #define VPU_HEVC_SWREG226_SW_ENC_HWROI8SUPPORT_MASK (0x200U) macro
117694 …)) << VPU_HEVC_SWREG226_SW_ENC_HWROI8SUPPORT_SHIFT)) & VPU_HEVC_SWREG226_SW_ENC_HWROI8SUPPORT_MASK)