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Searched refs:VPU_HEVC_SWREG222_SW_ENC_TOTALWLAST_MASK (Results 1 – 6 of 6) sorted by relevance

/hal_nxp-latest/mcux/mcux-sdk/devices/MIMX8ML6/
DMIMX8ML6_cm7.h117489 #define VPU_HEVC_SWREG222_SW_ENC_TOTALWLAST_MASK (0xFFFFFFFFU) macro
117491 …2_t)(x)) << VPU_HEVC_SWREG222_SW_ENC_TOTALWLAST_SHIFT)) & VPU_HEVC_SWREG222_SW_ENC_TOTALWLAST_MASK)
/hal_nxp-latest/mcux/mcux-sdk/devices/MIMX8ML4/
DMIMX8ML4_cm7.h117489 #define VPU_HEVC_SWREG222_SW_ENC_TOTALWLAST_MASK (0xFFFFFFFFU) macro
117491 …2_t)(x)) << VPU_HEVC_SWREG222_SW_ENC_TOTALWLAST_SHIFT)) & VPU_HEVC_SWREG222_SW_ENC_TOTALWLAST_MASK)
/hal_nxp-latest/mcux/mcux-sdk/devices/MIMX8ML3/
DMIMX8ML3_cm7.h117489 #define VPU_HEVC_SWREG222_SW_ENC_TOTALWLAST_MASK (0xFFFFFFFFU) macro
117491 …2_t)(x)) << VPU_HEVC_SWREG222_SW_ENC_TOTALWLAST_SHIFT)) & VPU_HEVC_SWREG222_SW_ENC_TOTALWLAST_MASK)
/hal_nxp-latest/mcux/mcux-sdk/devices/MIMX8ML8/
DMIMX8ML8_dsp.h112657 #define VPU_HEVC_SWREG222_SW_ENC_TOTALWLAST_MASK (0xFFFFFFFFU) macro
112659 …2_t)(x)) << VPU_HEVC_SWREG222_SW_ENC_TOTALWLAST_SHIFT)) & VPU_HEVC_SWREG222_SW_ENC_TOTALWLAST_MASK)
DMIMX8ML8_cm7.h117489 #define VPU_HEVC_SWREG222_SW_ENC_TOTALWLAST_MASK (0xFFFFFFFFU) macro
117491 …2_t)(x)) << VPU_HEVC_SWREG222_SW_ENC_TOTALWLAST_SHIFT)) & VPU_HEVC_SWREG222_SW_ENC_TOTALWLAST_MASK)
DMIMX8ML8_ca53.h117522 #define VPU_HEVC_SWREG222_SW_ENC_TOTALWLAST_MASK (0xFFFFFFFFU) macro
117524 …2_t)(x)) << VPU_HEVC_SWREG222_SW_ENC_TOTALWLAST_SHIFT)) & VPU_HEVC_SWREG222_SW_ENC_TOTALWLAST_MASK)