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Searched refs:VPU_HEVC_SWREG217_SW_ENC_TOTALAR_MASK (Results 1 – 6 of 6) sorted by relevance

/hal_nxp-latest/mcux/mcux-sdk/devices/MIMX8ML6/
DMIMX8ML6_cm7.h117449 #define VPU_HEVC_SWREG217_SW_ENC_TOTALAR_MASK (0xFFFFFFFFU) macro
117451 …(uint32_t)(x)) << VPU_HEVC_SWREG217_SW_ENC_TOTALAR_SHIFT)) & VPU_HEVC_SWREG217_SW_ENC_TOTALAR_MASK)
/hal_nxp-latest/mcux/mcux-sdk/devices/MIMX8ML4/
DMIMX8ML4_cm7.h117449 #define VPU_HEVC_SWREG217_SW_ENC_TOTALAR_MASK (0xFFFFFFFFU) macro
117451 …(uint32_t)(x)) << VPU_HEVC_SWREG217_SW_ENC_TOTALAR_SHIFT)) & VPU_HEVC_SWREG217_SW_ENC_TOTALAR_MASK)
/hal_nxp-latest/mcux/mcux-sdk/devices/MIMX8ML3/
DMIMX8ML3_cm7.h117449 #define VPU_HEVC_SWREG217_SW_ENC_TOTALAR_MASK (0xFFFFFFFFU) macro
117451 …(uint32_t)(x)) << VPU_HEVC_SWREG217_SW_ENC_TOTALAR_SHIFT)) & VPU_HEVC_SWREG217_SW_ENC_TOTALAR_MASK)
/hal_nxp-latest/mcux/mcux-sdk/devices/MIMX8ML8/
DMIMX8ML8_dsp.h112617 #define VPU_HEVC_SWREG217_SW_ENC_TOTALAR_MASK (0xFFFFFFFFU) macro
112619 …(uint32_t)(x)) << VPU_HEVC_SWREG217_SW_ENC_TOTALAR_SHIFT)) & VPU_HEVC_SWREG217_SW_ENC_TOTALAR_MASK)
DMIMX8ML8_cm7.h117449 #define VPU_HEVC_SWREG217_SW_ENC_TOTALAR_MASK (0xFFFFFFFFU) macro
117451 …(uint32_t)(x)) << VPU_HEVC_SWREG217_SW_ENC_TOTALAR_SHIFT)) & VPU_HEVC_SWREG217_SW_ENC_TOTALAR_MASK)
DMIMX8ML8_ca53.h117482 #define VPU_HEVC_SWREG217_SW_ENC_TOTALAR_MASK (0xFFFFFFFFU) macro
117484 …(uint32_t)(x)) << VPU_HEVC_SWREG217_SW_ENC_TOTALAR_SHIFT)) & VPU_HEVC_SWREG217_SW_ENC_TOTALAR_MASK)