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Searched refs:VPU_HEVC_SWREG208_SW_ENC_MDQPY_MASK (Results 1 – 6 of 6) sorted by relevance

/hal_nxp-latest/mcux/mcux-sdk/devices/MIMX8ML6/
DMIMX8ML6_cm7.h117333 #define VPU_HEVC_SWREG208_SW_ENC_MDQPY_MASK (0xFC000000U) macro
117335 …t)(((uint32_t)(x)) << VPU_HEVC_SWREG208_SW_ENC_MDQPY_SHIFT)) & VPU_HEVC_SWREG208_SW_ENC_MDQPY_MASK)
/hal_nxp-latest/mcux/mcux-sdk/devices/MIMX8ML4/
DMIMX8ML4_cm7.h117333 #define VPU_HEVC_SWREG208_SW_ENC_MDQPY_MASK (0xFC000000U) macro
117335 …t)(((uint32_t)(x)) << VPU_HEVC_SWREG208_SW_ENC_MDQPY_SHIFT)) & VPU_HEVC_SWREG208_SW_ENC_MDQPY_MASK)
/hal_nxp-latest/mcux/mcux-sdk/devices/MIMX8ML3/
DMIMX8ML3_cm7.h117333 #define VPU_HEVC_SWREG208_SW_ENC_MDQPY_MASK (0xFC000000U) macro
117335 …t)(((uint32_t)(x)) << VPU_HEVC_SWREG208_SW_ENC_MDQPY_SHIFT)) & VPU_HEVC_SWREG208_SW_ENC_MDQPY_MASK)
/hal_nxp-latest/mcux/mcux-sdk/devices/MIMX8ML8/
DMIMX8ML8_dsp.h112501 #define VPU_HEVC_SWREG208_SW_ENC_MDQPY_MASK (0xFC000000U) macro
112503 …t)(((uint32_t)(x)) << VPU_HEVC_SWREG208_SW_ENC_MDQPY_SHIFT)) & VPU_HEVC_SWREG208_SW_ENC_MDQPY_MASK)
DMIMX8ML8_cm7.h117333 #define VPU_HEVC_SWREG208_SW_ENC_MDQPY_MASK (0xFC000000U) macro
117335 …t)(((uint32_t)(x)) << VPU_HEVC_SWREG208_SW_ENC_MDQPY_SHIFT)) & VPU_HEVC_SWREG208_SW_ENC_MDQPY_MASK)
DMIMX8ML8_ca53.h117366 #define VPU_HEVC_SWREG208_SW_ENC_MDQPY_MASK (0xFC000000U) macro
117368 …t)(((uint32_t)(x)) << VPU_HEVC_SWREG208_SW_ENC_MDQPY_SHIFT)) & VPU_HEVC_SWREG208_SW_ENC_MDQPY_MASK)