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Searched refs:VPU_HEVC_SWREG111_SW_ENC_INTRACU8NUM_MASK (Results 1 – 6 of 6) sorted by relevance

/hal_nxp-latest/mcux/mcux-sdk/devices/MIMX8ML6/
DMIMX8ML6_cm7.h116331 #define VPU_HEVC_SWREG111_SW_ENC_INTRACU8NUM_MASK (0xFFFFF000U) macro
116333 …t)(x)) << VPU_HEVC_SWREG111_SW_ENC_INTRACU8NUM_SHIFT)) & VPU_HEVC_SWREG111_SW_ENC_INTRACU8NUM_MASK)
/hal_nxp-latest/mcux/mcux-sdk/devices/MIMX8ML4/
DMIMX8ML4_cm7.h116331 #define VPU_HEVC_SWREG111_SW_ENC_INTRACU8NUM_MASK (0xFFFFF000U) macro
116333 …t)(x)) << VPU_HEVC_SWREG111_SW_ENC_INTRACU8NUM_SHIFT)) & VPU_HEVC_SWREG111_SW_ENC_INTRACU8NUM_MASK)
/hal_nxp-latest/mcux/mcux-sdk/devices/MIMX8ML3/
DMIMX8ML3_cm7.h116331 #define VPU_HEVC_SWREG111_SW_ENC_INTRACU8NUM_MASK (0xFFFFF000U) macro
116333 …t)(x)) << VPU_HEVC_SWREG111_SW_ENC_INTRACU8NUM_SHIFT)) & VPU_HEVC_SWREG111_SW_ENC_INTRACU8NUM_MASK)
/hal_nxp-latest/mcux/mcux-sdk/devices/MIMX8ML8/
DMIMX8ML8_dsp.h111499 #define VPU_HEVC_SWREG111_SW_ENC_INTRACU8NUM_MASK (0xFFFFF000U) macro
111501 …t)(x)) << VPU_HEVC_SWREG111_SW_ENC_INTRACU8NUM_SHIFT)) & VPU_HEVC_SWREG111_SW_ENC_INTRACU8NUM_MASK)
DMIMX8ML8_cm7.h116331 #define VPU_HEVC_SWREG111_SW_ENC_INTRACU8NUM_MASK (0xFFFFF000U) macro
116333 …t)(x)) << VPU_HEVC_SWREG111_SW_ENC_INTRACU8NUM_SHIFT)) & VPU_HEVC_SWREG111_SW_ENC_INTRACU8NUM_MASK)
DMIMX8ML8_ca53.h116364 #define VPU_HEVC_SWREG111_SW_ENC_INTRACU8NUM_MASK (0xFFFFF000U) macro
116366 …t)(x)) << VPU_HEVC_SWREG111_SW_ENC_INTRACU8NUM_SHIFT)) & VPU_HEVC_SWREG111_SW_ENC_INTRACU8NUM_MASK)