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Searched refs:VPU_H264_SWREG80_SW_ENC_HWMAXVIDEOWIDTH_MASK (Results 1 – 6 of 6) sorted by relevance

/hal_nxp-latest/mcux/mcux-sdk/devices/MIMX8ML6/
DMIMX8ML6_cm7.h112525 #define VPU_H264_SWREG80_SW_ENC_HWMAXVIDEOWIDTH_MASK (0x1FFFU) macro
112527 … << VPU_H264_SWREG80_SW_ENC_HWMAXVIDEOWIDTH_SHIFT)) & VPU_H264_SWREG80_SW_ENC_HWMAXVIDEOWIDTH_MASK)
/hal_nxp-latest/mcux/mcux-sdk/devices/MIMX8ML4/
DMIMX8ML4_cm7.h112525 #define VPU_H264_SWREG80_SW_ENC_HWMAXVIDEOWIDTH_MASK (0x1FFFU) macro
112527 … << VPU_H264_SWREG80_SW_ENC_HWMAXVIDEOWIDTH_SHIFT)) & VPU_H264_SWREG80_SW_ENC_HWMAXVIDEOWIDTH_MASK)
/hal_nxp-latest/mcux/mcux-sdk/devices/MIMX8ML3/
DMIMX8ML3_cm7.h112525 #define VPU_H264_SWREG80_SW_ENC_HWMAXVIDEOWIDTH_MASK (0x1FFFU) macro
112527 … << VPU_H264_SWREG80_SW_ENC_HWMAXVIDEOWIDTH_SHIFT)) & VPU_H264_SWREG80_SW_ENC_HWMAXVIDEOWIDTH_MASK)
/hal_nxp-latest/mcux/mcux-sdk/devices/MIMX8ML8/
DMIMX8ML8_dsp.h107693 #define VPU_H264_SWREG80_SW_ENC_HWMAXVIDEOWIDTH_MASK (0x1FFFU) macro
107695 … << VPU_H264_SWREG80_SW_ENC_HWMAXVIDEOWIDTH_SHIFT)) & VPU_H264_SWREG80_SW_ENC_HWMAXVIDEOWIDTH_MASK)
DMIMX8ML8_cm7.h112525 #define VPU_H264_SWREG80_SW_ENC_HWMAXVIDEOWIDTH_MASK (0x1FFFU) macro
112527 … << VPU_H264_SWREG80_SW_ENC_HWMAXVIDEOWIDTH_SHIFT)) & VPU_H264_SWREG80_SW_ENC_HWMAXVIDEOWIDTH_MASK)
DMIMX8ML8_ca53.h112558 #define VPU_H264_SWREG80_SW_ENC_HWMAXVIDEOWIDTH_MASK (0x1FFFU) macro
112560 … << VPU_H264_SWREG80_SW_ENC_HWMAXVIDEOWIDTH_SHIFT)) & VPU_H264_SWREG80_SW_ENC_HWMAXVIDEOWIDTH_MASK)