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Searched refs:VPU_H264_SWREG1_SW_ENC_IRQ_MASK (Results 1 – 6 of 6) sorted by relevance

/hal_nxp-latest/mcux/mcux-sdk/devices/MIMX8ML6/
DMIMX8ML6_cm7.h111563 #define VPU_H264_SWREG1_SW_ENC_IRQ_MASK (0x1U) macro
111565 …(uint32_t)(((uint32_t)(x)) << VPU_H264_SWREG1_SW_ENC_IRQ_SHIFT)) & VPU_H264_SWREG1_SW_ENC_IRQ_MASK)
/hal_nxp-latest/mcux/mcux-sdk/devices/MIMX8ML4/
DMIMX8ML4_cm7.h111563 #define VPU_H264_SWREG1_SW_ENC_IRQ_MASK (0x1U) macro
111565 …(uint32_t)(((uint32_t)(x)) << VPU_H264_SWREG1_SW_ENC_IRQ_SHIFT)) & VPU_H264_SWREG1_SW_ENC_IRQ_MASK)
/hal_nxp-latest/mcux/mcux-sdk/devices/MIMX8ML3/
DMIMX8ML3_cm7.h111563 #define VPU_H264_SWREG1_SW_ENC_IRQ_MASK (0x1U) macro
111565 …(uint32_t)(((uint32_t)(x)) << VPU_H264_SWREG1_SW_ENC_IRQ_SHIFT)) & VPU_H264_SWREG1_SW_ENC_IRQ_MASK)
/hal_nxp-latest/mcux/mcux-sdk/devices/MIMX8ML8/
DMIMX8ML8_dsp.h106731 #define VPU_H264_SWREG1_SW_ENC_IRQ_MASK (0x1U) macro
106733 …(uint32_t)(((uint32_t)(x)) << VPU_H264_SWREG1_SW_ENC_IRQ_SHIFT)) & VPU_H264_SWREG1_SW_ENC_IRQ_MASK)
DMIMX8ML8_cm7.h111563 #define VPU_H264_SWREG1_SW_ENC_IRQ_MASK (0x1U) macro
111565 …(uint32_t)(((uint32_t)(x)) << VPU_H264_SWREG1_SW_ENC_IRQ_SHIFT)) & VPU_H264_SWREG1_SW_ENC_IRQ_MASK)
DMIMX8ML8_ca53.h111596 #define VPU_H264_SWREG1_SW_ENC_IRQ_MASK (0x1U) macro
111598 …(uint32_t)(((uint32_t)(x)) << VPU_H264_SWREG1_SW_ENC_IRQ_SHIFT)) & VPU_H264_SWREG1_SW_ENC_IRQ_MASK)