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Searched refs:VGPU_AQHICLOCKCONTROL_FSCALE_VAL_MASK (Results 1 – 2 of 2) sorted by relevance

/hal_nxp-latest/mcux/mcux-sdk/devices/MIMXRT798S/
DMIMXRT798S_ezhv.h95145 #define VGPU_AQHICLOCKCONTROL_FSCALE_VAL_MASK (0x1FCU) macro
95148 …(uint32_t)(x)) << VGPU_AQHICLOCKCONTROL_FSCALE_VAL_SHIFT)) & VGPU_AQHICLOCKCONTROL_FSCALE_VAL_MASK)
/hal_nxp-latest/mcux/mcux-sdk/devices/MIMXRT758S/
DMIMXRT758S_ezhv.h95121 #define VGPU_AQHICLOCKCONTROL_FSCALE_VAL_MASK (0x1FCU) macro
95124 …(uint32_t)(x)) << VGPU_AQHICLOCKCONTROL_FSCALE_VAL_SHIFT)) & VGPU_AQHICLOCKCONTROL_FSCALE_VAL_MASK)